forked from OSchip/llvm-project
[cpu-detection] Substantial refactor of Host CPU detection code (x86)
Summary: Following D20970 (committed as r271726). This is a substantial refactoring of the host CPU detection code. There is no functionality change intended, but the changes are extensive. Definitions of architecture types and subtypes are by no means exhaustive or perfectly defined, but a fair starting point. Suggestions for futher improvements are welcome. Reviewers: llvm-commits Differential Revision: http://reviews.llvm.org/D20988 llvm-svn: 271921
This commit is contained in:
Alina Sbirlea
parent
917a42d8b5
commit
76c4a855bc
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@ -73,6 +73,102 @@ static ssize_t LLVM_ATTRIBUTE_UNUSED readCpuInfo(void *Buf, size_t Size) {
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defined(_M_IX86) || defined(__x86_64__) || defined(_M_AMD64) || \
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defined(_M_X64)
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enum VendorSignatures {
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SIG_INTEL = 0x756e6547 /* Genu */,
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SIG_AMD = 0x68747541 /* Auth */
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};
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enum ProcessorVendors {
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VENDOR_INTEL = 1,
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VENDOR_AMD,
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VENDOR_OTHER,
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VENDOR_MAX
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};
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enum ProcessorTypes {
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INTEL_ATOM = 1,
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INTEL_CORE2,
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INTEL_COREI7,
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AMDFAM10H,
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AMDFAM15H,
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INTEL_i386,
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INTEL_i486,
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INTEL_PENTIUM,
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INTEL_PENTIUM_PRO,
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INTEL_PENTIUM_II,
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INTEL_PENTIUM_III,
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INTEL_PENTIUM_IV,
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INTEL_PENTIUM_M,
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INTEL_CORE_DUO,
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INTEL_XEONPHI,
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INTEL_X86_64,
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INTEL_NOCONA,
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INTEL_PRESCOTT,
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AMD_i486,
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AMDPENTIUM,
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AMDATHLON,
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AMDFAM14H,
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AMDFAM16H,
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CPU_TYPE_MAX
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};
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enum ProcessorSubtypes {
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INTEL_COREI7_NEHALEM = 1,
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INTEL_COREI7_WESTMERE,
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INTEL_COREI7_SANDYBRIDGE,
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AMDFAM10H_BARCELONA,
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AMDFAM10H_SHANGHAI,
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AMDFAM10H_ISTANBUL,
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AMDFAM15H_BDVER1,
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AMDFAM15H_BDVER2,
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INTEL_PENTIUM_MMX,
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INTEL_CORE2_65,
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INTEL_CORE2_45,
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INTEL_COREI7_IVYBRIDGE,
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INTEL_COREI7_HASWELL,
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INTEL_COREI7_BROADWELL,
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INTEL_COREI7_SKYLAKE,
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INTEL_COREI7_SKYLAKE_AVX512,
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INTEL_ATOM_BONNELL,
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INTEL_ATOM_SILVERMONT,
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INTEL_KNIGHTS_LANDING,
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AMDPENTIUM_K6,
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AMDPENTIUM_K62,
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AMDPENTIUM_K63,
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AMDPENTIUM_GEODE,
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AMDATHLON_TBIRD,
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AMDATHLON_MP,
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AMDATHLON_XP,
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AMDATHLON_K8SSE3,
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AMDATHLON_OPTERON,
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AMDATHLON_FX,
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AMDATHLON_64,
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AMD_BTVER1,
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AMD_BTVER2,
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AMDFAM15H_BDVER3,
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AMDFAM15H_BDVER4,
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CPU_SUBTYPE_MAX
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};
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enum ProcessorFeatures {
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FEATURE_CMOV = 0,
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FEATURE_MMX,
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FEATURE_POPCNT,
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FEATURE_SSE,
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FEATURE_SSE2,
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FEATURE_SSE3,
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FEATURE_SSSE3,
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FEATURE_SSE4_1,
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FEATURE_SSE4_2,
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FEATURE_AVX,
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FEATURE_AVX2,
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FEATURE_AVX512,
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FEATURE_AVX512SAVE,
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FEATURE_MOVBE,
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FEATURE_ADX,
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FEATURE_EM64T
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};
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/// getX86CpuIDAndInfo - Execute the specified cpuid and return the 4 values in
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/// the specified arguments. If we can't run cpuid on the host, return true.
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static bool getX86CpuIDAndInfo(unsigned value, unsigned *rEAX, unsigned *rEBX,
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@ -199,51 +295,16 @@ static void detectX86FamilyModel(unsigned EAX, unsigned *Family,
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}
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}
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StringRef sys::getHostCPUName() {
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unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
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if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
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return "generic";
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unsigned Family = 0;
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unsigned Model = 0;
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detectX86FamilyModel(EAX, &Family, &Model);
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union {
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unsigned u[3];
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char c[12];
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} text;
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unsigned MaxLeaf;
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getX86CpuIDAndInfo(0, &MaxLeaf, text.u + 0, text.u + 2, text.u + 1);
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bool HasMMX = (EDX >> 23) & 1;
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bool HasSSE = (EDX >> 25) & 1;
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bool HasSSE2 = (EDX >> 26) & 1;
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bool HasSSE3 = (ECX >> 0) & 1;
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bool HasSSSE3 = (ECX >> 9) & 1;
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bool HasSSE41 = (ECX >> 19) & 1;
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bool HasSSE42 = (ECX >> 20) & 1;
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bool HasMOVBE = (ECX >> 22) & 1;
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// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
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// indicates that the AVX registers will be saved and restored on context
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// switch, then we have full AVX support.
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const unsigned AVXBits = (1 << 27) | (1 << 28);
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bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
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((EAX & 0x6) == 0x6);
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bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
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bool HasLeaf7 =
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MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
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bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
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bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
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bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
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getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
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bool Em64T = (EDX >> 29) & 0x1;
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bool HasTBM = (ECX >> 21) & 0x1;
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if (memcmp(text.c, "GenuineIntel", 12) == 0) {
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static void
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getIntelProcessorTypeAndSubtype(unsigned int Family, unsigned int Model,
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unsigned int Brand_id, unsigned int Features,
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unsigned *Type, unsigned *Subtype) {
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if (Brand_id != 0)
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return;
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switch (Family) {
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case 3:
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return "i386";
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*Type = INTEL_i386;
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break;
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case 4:
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switch (Model) {
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case 0: // Intel486 DX processors
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@ -256,7 +317,8 @@ StringRef sys::getHostCPUName() {
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case 7: // Write-Back Enhanced IntelDX2 processors
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case 8: // IntelDX4 OverDrive processors, IntelDX4 processors
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default:
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return "i486";
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*Type = INTEL_i486;
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break;
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}
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case 5:
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switch (Model) {
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@ -267,117 +329,132 @@ StringRef sys::getHostCPUName() {
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// 150, 166, 200)
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case 3: // Pentium OverDrive processors for Intel486 processor-based
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// systems
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return "pentium";
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*Type = INTEL_PENTIUM;
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break;
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case 4: // Pentium OverDrive processor with MMX technology for Pentium
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// processor (75, 90, 100, 120, 133), Pentium processor with
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// MMX technology (166, 200)
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return "pentium-mmx";
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*Type = INTEL_PENTIUM;
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*Subtype = INTEL_PENTIUM_MMX;
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break;
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default:
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return "pentium";
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*Type = INTEL_PENTIUM;
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break;
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}
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case 6:
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switch (Model) {
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case 0x01: // Pentium Pro processor
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return "pentiumpro";
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*Type = INTEL_PENTIUM_PRO;
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break;
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case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
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// model 03
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case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
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// model 05, and Intel Celeron processor, model 05
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case 0x06: // Celeron processor, model 06
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return "pentium2";
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*Type = INTEL_PENTIUM_II;
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break;
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case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
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// processor, model 07
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case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
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// model 08, and Celeron processor, model 08
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case 0x0a: // Pentium III Xeon processor, model 0Ah
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case 0x0b: // Pentium III processor, model 0Bh
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return "pentium3";
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case 0x09: // Intel Pentium M processor, Intel Celeron M processor model
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// 09.
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*Type = INTEL_PENTIUM_III;
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break;
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case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
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case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
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// 0Dh. All processors are manufactured using the 90 nm
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// process.
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// 0Dh. All processors are manufactured using the 90 nm process.
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case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
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// Integrated Processor with Intel QuickAssist Technology
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return "pentium-m";
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*Type = INTEL_PENTIUM_M;
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break;
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case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
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// 0Eh. All processors are manufactured using the 65 nm
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// process.
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return "yonah";
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// 0Eh. All processors are manufactured using the 65 nm process.
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*Type = INTEL_CORE_DUO;
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break; // yonah
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case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
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// processor, Intel Core 2 Quad processor, Intel Core 2 Quad
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// mobile processor, Intel Core 2 Extreme processor, Intel
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// Pentium Dual-Core processor, Intel Xeon processor, model
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// 0Fh. All processors are manufactured using the 65 nm
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// process.
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// 0Fh. All processors are manufactured using the 65 nm process.
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case 0x16: // Intel Celeron processor model 16h. All processors are
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// manufactured using the 65 nm process
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return "core2";
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*Type = INTEL_CORE2; // "core2"
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*Subtype = INTEL_CORE2_65;
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break;
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case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
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// 17h. All processors are manufactured using the 45 nm
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// process.
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// 17h. All processors are manufactured using the 45 nm process.
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//
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// 45nm: Penryn , Wolfdale, Yorkfield (XE)
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case 0x1d: // Intel Xeon processor MP. All processors are manufactured
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// using
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case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
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// the 45 nm process.
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return "penryn";
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*Type = INTEL_CORE2; // "penryn"
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*Subtype = INTEL_CORE2_45;
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break;
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case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
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// processors are manufactured using the 45 nm process.
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case 0x1e: // Intel(R) Core(TM) i7 CPU 870 @ 2.93GHz.
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// As found in a Summer 2010 model iMac.
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case 0x1f:
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case 0x2e: // Nehalem EX
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return "nehalem";
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*Type = INTEL_COREI7; // "nehalem"
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*Subtype = INTEL_COREI7_NEHALEM;
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break;
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case 0x25: // Intel Core i7, laptop version.
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case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
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// processors are manufactured using the 32 nm process.
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case 0x2f: // Westmere EX
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return "westmere";
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*Type = INTEL_COREI7; // "westmere"
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*Subtype = INTEL_COREI7_WESTMERE;
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break;
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case 0x2a: // Intel Core i7 processor. All processors are manufactured
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// using the 32 nm process.
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case 0x2d:
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return "sandybridge";
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*Type = INTEL_COREI7; //"sandybridge"
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*Subtype = INTEL_COREI7_SANDYBRIDGE;
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break;
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case 0x3a:
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case 0x3e: // Ivy Bridge EP
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return "ivybridge";
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*Type = INTEL_COREI7; // "ivybridge"
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*Subtype = INTEL_COREI7_IVYBRIDGE;
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break;
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// Haswell:
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case 0x3c:
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case 0x3f:
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case 0x45:
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case 0x46:
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return "haswell";
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*Type = INTEL_COREI7; // "haswell"
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*Subtype = INTEL_COREI7_HASWELL;
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break;
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// Broadwell:
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case 0x3d:
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case 0x47:
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case 0x4f:
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case 0x56:
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return "broadwell";
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*Type = INTEL_COREI7; // "broadwell"
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*Subtype = INTEL_COREI7_BROADWELL;
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break;
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// Skylake:
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case 0x4e:
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return "skylake-avx512";
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*Type = INTEL_COREI7; // "skylake-avx512"
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*Subtype = INTEL_COREI7_SKYLAKE_AVX512;
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break;
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case 0x5e:
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return "skylake";
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*Type = INTEL_COREI7; // "skylake"
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*Subtype = INTEL_COREI7_SKYLAKE;
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break;
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case 0x1c: // Most 45 nm Intel Atom processors
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case 0x26: // 45 nm Atom Lincroft
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case 0x27: // 32 nm Atom Medfield
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case 0x35: // 32 nm Atom Midview
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case 0x36: // 32 nm Atom Midview
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return "bonnell";
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*Type = INTEL_ATOM;
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*Subtype = INTEL_ATOM_BONNELL;
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break; // "bonnell"
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// Atom Silvermont codes from the Intel software optimization guide.
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case 0x37:
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@ -386,35 +463,79 @@ StringRef sys::getHostCPUName() {
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case 0x5a:
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case 0x5d:
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case 0x4c: // really airmont
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return "silvermont";
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*Type = INTEL_ATOM;
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*Subtype = INTEL_ATOM_SILVERMONT;
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break; // "silvermont"
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case 0x57:
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return "knl";
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*Type = INTEL_XEONPHI; // knl
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*Subtype = INTEL_KNIGHTS_LANDING;
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break;
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default: // Unknown family 6 CPU, try to guess.
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if (HasAVX512)
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return "knl";
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if (HasADX)
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return "broadwell";
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if (HasAVX2)
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return "haswell";
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if (HasAVX)
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return "sandybridge";
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if (HasSSE42)
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return HasMOVBE ? "silvermont" : "nehalem";
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if (HasSSE41)
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return "penryn";
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if (HasSSSE3)
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return HasMOVBE ? "bonnell" : "core2";
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if (Em64T)
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return "x86-64";
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if (HasSSE2)
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return "pentium-m";
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if (HasSSE)
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return "pentium3";
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if (HasMMX)
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return "pentium2";
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return "pentiumpro";
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if (Features & (1 << FEATURE_AVX512)) {
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*Type = INTEL_XEONPHI; // knl
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*Subtype = INTEL_KNIGHTS_LANDING;
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break;
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}
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if (Features & (1 << FEATURE_ADX)) {
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*Type = INTEL_COREI7;
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*Subtype = INTEL_COREI7_BROADWELL;
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break;
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}
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if (Features & (1 << FEATURE_AVX2)) {
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*Type = INTEL_COREI7;
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*Subtype = INTEL_COREI7_HASWELL;
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break;
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}
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if (Features & (1 << FEATURE_AVX)) {
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*Type = INTEL_COREI7;
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*Subtype = INTEL_COREI7_SANDYBRIDGE;
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break;
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}
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if (Features & (1 << FEATURE_SSE4_2)) {
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if (Features & (1 << FEATURE_MOVBE)) {
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*Type = INTEL_ATOM;
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*Subtype = INTEL_ATOM_SILVERMONT;
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} else {
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*Type = INTEL_COREI7;
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*Subtype = INTEL_COREI7_NEHALEM;
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}
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break;
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}
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if (Features & (1 << FEATURE_SSE4_1)) {
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*Type = INTEL_CORE2; // "penryn"
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*Subtype = INTEL_CORE2_45;
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break;
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}
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if (Features & (1 << FEATURE_SSSE3)) {
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if (Features & (1 << FEATURE_MOVBE)) {
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*Type = INTEL_ATOM;
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*Subtype = INTEL_ATOM_BONNELL; // "bonnell"
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} else {
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*Type = INTEL_CORE2; // "core2"
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*Subtype = INTEL_CORE2_65;
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}
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break;
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}
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if (Features & (1 << FEATURE_EM64T)) {
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*Type = INTEL_X86_64;
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break; // x86-64
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}
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if (Features & (1 << FEATURE_SSE2)) {
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*Type = INTEL_PENTIUM_M;
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break;
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}
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if (Features & (1 << FEATURE_SSE)) {
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*Type = INTEL_PENTIUM_III;
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break;
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||||
}
|
||||
if (Features & (1 << FEATURE_MMX)) {
|
||||
*Type = INTEL_PENTIUM_II;
|
||||
break;
|
||||
}
|
||||
*Type = INTEL_PENTIUM_PRO;
|
||||
break;
|
||||
}
|
||||
case 15: {
|
||||
switch (Model) {
|
||||
|
|
@ -427,7 +548,9 @@ StringRef sys::getHostCPUName() {
|
|||
// Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
|
||||
// processor, and Mobile Intel Celeron processor. All processors
|
||||
// are model 02h and manufactured using the 0.13 micron process.
|
||||
return (Em64T) ? "x86-64" : "pentium4";
|
||||
*Type =
|
||||
((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV);
|
||||
break;
|
||||
|
||||
case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
|
||||
// processor. All processors are model 03h and manufactured using
|
||||
|
|
@ -440,86 +563,352 @@ StringRef sys::getHostCPUName() {
|
|||
// Extreme Edition, Intel Xeon processor, Intel Xeon processor
|
||||
// MP, Intel Celeron D processor. All processors are model 06h
|
||||
// and manufactured using the 65 nm process.
|
||||
return (Em64T) ? "nocona" : "prescott";
|
||||
*Type =
|
||||
((Features & (1 << FEATURE_EM64T)) ? INTEL_NOCONA : INTEL_PRESCOTT);
|
||||
break;
|
||||
|
||||
default:
|
||||
return (Em64T) ? "x86-64" : "pentium4";
|
||||
*Type =
|
||||
((Features & (1 << FEATURE_EM64T)) ? INTEL_X86_64 : INTEL_PENTIUM_IV);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
default:
|
||||
return "generic";
|
||||
break; /*"generic"*/
|
||||
}
|
||||
} else if (memcmp(text.c, "AuthenticAMD", 12) == 0) {
|
||||
}
|
||||
|
||||
static void getAMDProcessorTypeAndSubtype(unsigned int Family,
|
||||
unsigned int Model,
|
||||
unsigned int Features,
|
||||
unsigned *Type,
|
||||
unsigned *Subtype) {
|
||||
// FIXME: this poorly matches the generated SubtargetFeatureKV table. There
|
||||
// appears to be no way to generate the wide variety of AMD-specific targets
|
||||
// from the information returned from CPUID.
|
||||
switch (Family) {
|
||||
case 4:
|
||||
return "i486";
|
||||
*Type = AMD_i486;
|
||||
case 5:
|
||||
*Type = AMDPENTIUM;
|
||||
switch (Model) {
|
||||
case 6:
|
||||
case 7:
|
||||
return "k6";
|
||||
*Subtype = AMDPENTIUM_K6;
|
||||
break; // "k6"
|
||||
case 8:
|
||||
return "k6-2";
|
||||
*Subtype = AMDPENTIUM_K62;
|
||||
break; // "k6-2"
|
||||
case 9:
|
||||
case 13:
|
||||
return "k6-3";
|
||||
*Subtype = AMDPENTIUM_K63;
|
||||
break; // "k6-3"
|
||||
case 10:
|
||||
*Subtype = AMDPENTIUM_GEODE;
|
||||
break; // "geode"
|
||||
default:
|
||||
break;
|
||||
}
|
||||
case 6:
|
||||
*Type = AMDATHLON;
|
||||
switch (Model) {
|
||||
case 4:
|
||||
*Subtype = AMDATHLON_TBIRD;
|
||||
break; // "athlon-tbird"
|
||||
case 6:
|
||||
case 7:
|
||||
case 8:
|
||||
*Subtype = AMDATHLON_MP;
|
||||
break; // "athlon-mp"
|
||||
case 10:
|
||||
*Subtype = AMDATHLON_XP;
|
||||
break; // "athlon-xp"
|
||||
default:
|
||||
break;
|
||||
}
|
||||
case 15:
|
||||
*Type = AMDATHLON;
|
||||
if (Features & (1 << FEATURE_SSE3)) {
|
||||
*Subtype = AMDATHLON_K8SSE3;
|
||||
break; // "k8-sse3"
|
||||
}
|
||||
switch (Model) {
|
||||
case 1:
|
||||
*Subtype = AMDATHLON_OPTERON;
|
||||
break; // "opteron"
|
||||
case 5:
|
||||
*Subtype = AMDATHLON_FX;
|
||||
break; // "athlon-fx"; also opteron
|
||||
default:
|
||||
*Subtype = AMDATHLON_64;
|
||||
break; // "athlon64"
|
||||
}
|
||||
case 16:
|
||||
*Type = AMDFAM10H; // "amdfam10"
|
||||
switch (Model) {
|
||||
case 2:
|
||||
*Subtype = AMDFAM10H_BARCELONA;
|
||||
break;
|
||||
case 4:
|
||||
*Subtype = AMDFAM10H_SHANGHAI;
|
||||
break;
|
||||
case 8:
|
||||
*Subtype = AMDFAM10H_ISTANBUL;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
case 20:
|
||||
*Type = AMDFAM14H;
|
||||
*Subtype = AMD_BTVER1;
|
||||
break; // "btver1";
|
||||
case 21:
|
||||
*Type = AMDFAM15H;
|
||||
if (!(Features &
|
||||
(1 << FEATURE_AVX))) { // If no AVX support, provide a sane fallback.
|
||||
*Subtype = AMD_BTVER1;
|
||||
break; // "btver1"
|
||||
}
|
||||
if (Model >= 0x50 && Model <= 0x6f) {
|
||||
*Subtype = AMDFAM15H_BDVER4;
|
||||
break; // "bdver4"; 50h-6Fh: Excavator
|
||||
}
|
||||
if (Model >= 0x30 && Model <= 0x3f) {
|
||||
*Subtype = AMDFAM15H_BDVER3;
|
||||
break; // "bdver3"; 30h-3Fh: Steamroller
|
||||
}
|
||||
if (Model >= 0x10 && Model <= 0x1f) {
|
||||
*Subtype = AMDFAM15H_BDVER2;
|
||||
break; // "bdver2"; 10h-1Fh: Piledriver
|
||||
}
|
||||
if (Model <= 0x0f) {
|
||||
*Subtype = AMDFAM15H_BDVER1;
|
||||
break; // "bdver1"; 00h-0Fh: Bulldozer
|
||||
}
|
||||
break;
|
||||
case 22:
|
||||
*Type = AMDFAM16H;
|
||||
if (!(Features &
|
||||
(1 << FEATURE_AVX))) { // If no AVX support provide a sane fallback.
|
||||
*Subtype = AMD_BTVER1;
|
||||
break; // "btver1";
|
||||
}
|
||||
*Subtype = AMD_BTVER2;
|
||||
break; // "btver2"
|
||||
default:
|
||||
break; // "generic"
|
||||
}
|
||||
}
|
||||
|
||||
unsigned getAvailableFeatures(unsigned int ECX, unsigned int EDX,
|
||||
unsigned MaxLeaf) {
|
||||
unsigned Features = 0;
|
||||
unsigned int EAX, EBX;
|
||||
Features |= (((EDX >> 23) & 1) << FEATURE_MMX);
|
||||
Features |= (((EDX >> 25) & 1) << FEATURE_SSE);
|
||||
Features |= (((EDX >> 26) & 1) << FEATURE_SSE2);
|
||||
Features |= (((ECX >> 0) & 1) << FEATURE_SSE3);
|
||||
Features |= (((ECX >> 9) & 1) << FEATURE_SSSE3);
|
||||
Features |= (((ECX >> 19) & 1) << FEATURE_SSE4_1);
|
||||
Features |= (((ECX >> 20) & 1) << FEATURE_SSE4_2);
|
||||
Features |= (((ECX >> 22) & 1) << FEATURE_MOVBE);
|
||||
|
||||
// If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
|
||||
// indicates that the AVX registers will be saved and restored on context
|
||||
// switch, then we have full AVX support.
|
||||
const unsigned AVXBits = (1 << 27) | (1 << 28);
|
||||
bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
|
||||
((EAX & 0x6) == 0x6);
|
||||
bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
|
||||
bool HasLeaf7 =
|
||||
MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
|
||||
bool HasADX = HasLeaf7 && ((EBX >> 19) & 1);
|
||||
bool HasAVX2 = HasAVX && HasLeaf7 && (EBX & 0x20);
|
||||
bool HasAVX512 = HasLeaf7 && HasAVX512Save && ((EBX >> 16) & 1);
|
||||
Features |= (HasAVX << FEATURE_AVX);
|
||||
Features |= (HasAVX2 << FEATURE_AVX2);
|
||||
Features |= (HasAVX512 << FEATURE_AVX512);
|
||||
Features |= (HasAVX512Save << FEATURE_AVX512SAVE);
|
||||
Features |= (HasADX << FEATURE_ADX);
|
||||
|
||||
getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
|
||||
Features |= (((EDX >> 29) & 0x1) << FEATURE_EM64T);
|
||||
return Features;
|
||||
}
|
||||
|
||||
StringRef sys::getHostCPUName() {
|
||||
unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
|
||||
unsigned MaxLeaf, Vendor;
|
||||
|
||||
if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX))
|
||||
return "generic";
|
||||
if (getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX))
|
||||
return "generic";
|
||||
|
||||
unsigned Brand_id = EBX & 0xff;
|
||||
unsigned Family = 0, Model = 0;
|
||||
unsigned Features = 0;
|
||||
detectX86FamilyModel(EAX, &Family, &Model);
|
||||
Features = getAvailableFeatures(ECX, EDX, MaxLeaf);
|
||||
|
||||
unsigned Type;
|
||||
unsigned Subtype;
|
||||
|
||||
if (Vendor == SIG_INTEL) {
|
||||
getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features, &Type,
|
||||
&Subtype);
|
||||
switch (Type) {
|
||||
case INTEL_i386:
|
||||
return "i386";
|
||||
case INTEL_i486:
|
||||
return "i486";
|
||||
case INTEL_PENTIUM:
|
||||
if (Subtype == INTEL_PENTIUM_MMX)
|
||||
return "pentium-mmx";
|
||||
return "pentium";
|
||||
case INTEL_PENTIUM_PRO:
|
||||
return "pentiumpro";
|
||||
case INTEL_PENTIUM_II:
|
||||
return "pentium2";
|
||||
case INTEL_PENTIUM_III:
|
||||
return "pentium3";
|
||||
case INTEL_PENTIUM_IV:
|
||||
return "pentium4";
|
||||
case INTEL_PENTIUM_M:
|
||||
return "pentium-m";
|
||||
case INTEL_CORE_DUO:
|
||||
return "yonah";
|
||||
case INTEL_CORE2:
|
||||
switch (Subtype) {
|
||||
case INTEL_CORE2_65:
|
||||
return "core2";
|
||||
case INTEL_CORE2_45:
|
||||
return "penryn";
|
||||
default:
|
||||
return "core2";
|
||||
}
|
||||
case INTEL_COREI7:
|
||||
switch (Subtype) {
|
||||
case INTEL_COREI7_NEHALEM:
|
||||
return "nehalem";
|
||||
case INTEL_COREI7_WESTMERE:
|
||||
return "westmere";
|
||||
case INTEL_COREI7_SANDYBRIDGE:
|
||||
return "sandybridge";
|
||||
case INTEL_COREI7_IVYBRIDGE:
|
||||
return "ivybridge";
|
||||
case INTEL_COREI7_HASWELL:
|
||||
return "haswell";
|
||||
case INTEL_COREI7_BROADWELL:
|
||||
return "broadwell";
|
||||
case INTEL_COREI7_SKYLAKE:
|
||||
return "skylake";
|
||||
case INTEL_COREI7_SKYLAKE_AVX512:
|
||||
return "skylake-avx512";
|
||||
default:
|
||||
return "corei7";
|
||||
}
|
||||
case INTEL_ATOM:
|
||||
switch (Subtype) {
|
||||
case INTEL_ATOM_BONNELL:
|
||||
return "bonnell";
|
||||
case INTEL_ATOM_SILVERMONT:
|
||||
return "silvermont";
|
||||
default:
|
||||
return "atom";
|
||||
}
|
||||
case INTEL_XEONPHI:
|
||||
return "knl"; /*update for more variants added*/
|
||||
case INTEL_X86_64:
|
||||
return "x86-64";
|
||||
case INTEL_NOCONA:
|
||||
return "nocona";
|
||||
case INTEL_PRESCOTT:
|
||||
return "prescott";
|
||||
default:
|
||||
return "generic";
|
||||
}
|
||||
} else if (Vendor == SIG_AMD) {
|
||||
getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
|
||||
switch (Type) {
|
||||
case AMD_i486:
|
||||
return "i486";
|
||||
case AMDPENTIUM:
|
||||
switch (Subtype) {
|
||||
case AMDPENTIUM_K6:
|
||||
return "k6";
|
||||
case AMDPENTIUM_K62:
|
||||
return "k6-2";
|
||||
case AMDPENTIUM_K63:
|
||||
return "k6-3";
|
||||
case AMDPENTIUM_GEODE:
|
||||
return "geode";
|
||||
default:
|
||||
return "pentium";
|
||||
}
|
||||
case 6:
|
||||
switch (Model) {
|
||||
case 4:
|
||||
case AMDATHLON:
|
||||
switch (Subtype) {
|
||||
case AMDATHLON_TBIRD:
|
||||
return "athlon-tbird";
|
||||
case 6:
|
||||
case 7:
|
||||
case 8:
|
||||
case AMDATHLON_MP:
|
||||
return "athlon-mp";
|
||||
case 10:
|
||||
case AMDATHLON_XP:
|
||||
return "athlon-xp";
|
||||
case AMDATHLON_K8SSE3:
|
||||
return "k8-sse3";
|
||||
case AMDATHLON_OPTERON:
|
||||
return "opteron";
|
||||
case AMDATHLON_FX:
|
||||
return "athlon-fx";
|
||||
case AMDATHLON_64:
|
||||
return "athlon64";
|
||||
default:
|
||||
return "athlon";
|
||||
}
|
||||
case 15:
|
||||
if (HasSSE3)
|
||||
return "k8-sse3";
|
||||
switch (Model) {
|
||||
case 1:
|
||||
return "opteron";
|
||||
case 5:
|
||||
return "athlon-fx"; // also opteron
|
||||
case AMDFAM10H:
|
||||
switch (Subtype) {
|
||||
case AMDFAM10H_BARCELONA:
|
||||
return "amdfam10-barcelona";
|
||||
case AMDFAM10H_SHANGHAI:
|
||||
return "amdfam10-shanghai";
|
||||
case AMDFAM10H_ISTANBUL:
|
||||
return "amdfam10-istanbul";
|
||||
default:
|
||||
return "athlon64";
|
||||
}
|
||||
case 16:
|
||||
return "amdfam10";
|
||||
case 20:
|
||||
}
|
||||
case AMDFAM14H:
|
||||
return "btver1";
|
||||
case 21:
|
||||
if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
|
||||
case AMDFAM15H:
|
||||
switch (Subtype) {
|
||||
case AMDFAM15H_BDVER1:
|
||||
return "bdver1";
|
||||
case AMDFAM15H_BDVER2:
|
||||
return "bdver2";
|
||||
case AMDFAM15H_BDVER3:
|
||||
return "bdver3";
|
||||
case AMDFAM15H_BDVER4:
|
||||
return "bdver4";
|
||||
case AMD_BTVER1:
|
||||
return "btver1";
|
||||
if (Model >= 0x50)
|
||||
return "bdver4"; // 50h-6Fh: Excavator
|
||||
if (Model >= 0x30)
|
||||
return "bdver3"; // 30h-3Fh: Steamroller
|
||||
if (Model >= 0x10 || HasTBM)
|
||||
return "bdver2"; // 10h-1Fh: Piledriver
|
||||
return "bdver1"; // 00h-0Fh: Bulldozer
|
||||
case 22:
|
||||
if (!HasAVX) // If the OS doesn't support AVX provide a sane fallback.
|
||||
default:
|
||||
return "amdfam15";
|
||||
}
|
||||
case AMDFAM16H:
|
||||
switch (Subtype) {
|
||||
case AMD_BTVER1:
|
||||
return "btver1";
|
||||
case AMD_BTVER2:
|
||||
return "btver2";
|
||||
default:
|
||||
return "amdfam16";
|
||||
}
|
||||
default:
|
||||
return "generic";
|
||||
}
|
||||
}
|
||||
return "generic";
|
||||
}
|
||||
|
||||
#elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
|
||||
StringRef sys::getHostCPUName() {
|
||||
host_basic_info_data_t hostInfo;
|
||||
|
|
|
|||
Loading…
Reference in New Issue