maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Add patterns to generate copies for extract_subvector instead of 

using vextractf128. This will reduce the number of issued instruction
for several avx codes.

llvm-svn: 136323
This commit is contained in:
Bruno Cardoso Lopes 2011-07-28 01:26:50 +00:00
parent 3fb0b635bd
commit 76bc28bac6
2 changed files with 15 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
llvm/lib/Target/X86/X86InstrSSE.td
View File

@ -5452,6 +5452,18 @@ def : Pat<(vextractf128_extract:$ext VR256:$src1, (i32 imm)),
(v32i8 VR256:$src1),
(EXTRACT_get_vextractf128_imm VR128:$ext)))>;
// Special COPY patterns
def : Pat<(v4i32 (extract_subvector (v8i32 VR256:$src), (i32 0))),
(v4i32 (EXTRACT_SUBREG (v8i32 VR256:$src), sub_xmm))>;
def : Pat<(v4f32 (extract_subvector (v8f32 VR256:$src), (i32 0))),
(v4f32 (EXTRACT_SUBREG (v8f32 VR256:$src), sub_xmm))>;
def : Pat<(v2i64 (extract_subvector (v4i64 VR256:$src), (i32 0))),
(v2i64 (EXTRACT_SUBREG (v4i64 VR256:$src), sub_xmm))>;
def : Pat<(v2f64 (extract_subvector (v4f64 VR256:$src), (i32 0))),
(v2f64 (EXTRACT_SUBREG (v4f64 VR256:$src), sub_xmm))>;
//===----------------------------------------------------------------------===//
// VMASKMOV - Conditional SIMD Packed Loads and Stores
//

6
llvm/test/CodeGen/X86/avx-cast.ll
View File

@ -24,21 +24,21 @@ entry:
ret <4 x i64> %shuffle.i
}
; CHECK: vextractf128 $0
; CHECK-NOT: vextractf128 $0
define <4 x float> @castD(<8 x float> %m) nounwind uwtable readnone ssp {
entry:
%shuffle.i = shufflevector <8 x float> %m, <8 x float> %m, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x float> %shuffle.i
}
; CHECK: vextractf128 $0
; CHECK-NOT: vextractf128 $0
define <2 x i64> @castE(<4 x i64> %m) nounwind uwtable readnone ssp {
entry:
%shuffle.i = shufflevector <4 x i64> %m, <4 x i64> %m, <2 x i32> <i32 0, i32 1>
ret <2 x i64> %shuffle.i
}
; CHECK: vextractf128 $0
; CHECK-NOT: vextractf128 $0
define <2 x double> @castF(<4 x double> %m) nounwind uwtable readnone ssp {
entry:
%shuffle.i = shufflevector <4 x double> %m, <4 x double> %m, <2 x i32> <i32 0, i32 1>