forked from OSchip/llvm-project
parent
d771e05121
commit
76a97c5f8a
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@ -288,7 +288,7 @@ def pred : PredicateOperand<OtherVT, (ops i32imm, CCR),
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// Conditional code operand for conditional branches and conditional moves.
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// No AlwaysVal value.
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def ccop : ImmutablePredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> {
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def ccop : PredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> {
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let PrintMethod = "printPredicateOperand";
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}
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@ -272,8 +272,8 @@ def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
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// PowerPC Predicate operand. 20 = (0<<5)|20 = always, CR0 is a dummy reg
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// that doesn't matter.
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def pred : ImmutablePredicateOperand<OtherVT, (ops imm, CRRC),
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(ops (i32 20), CR0)> {
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def pred : PredicateOperand<OtherVT, (ops imm, CRRC),
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(ops (i32 20), CR0)> {
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let PrintMethod = "printPredicateOperand";
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}
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