forked from OSchip/llvm-project
[regcoalescing] bug fix for RegistersDefinedFromSameValue.
An improper SlotIndex->VNInfo lookup was leading to unsafe copy removal. Fixes PR10920 401.bzip2 miscompile with no IV rewrite. llvm-svn: 139765
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31412642a6
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@ -411,6 +411,14 @@ namespace llvm {
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return I == end() ? 0 : I->valno;
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}
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/// getVNInfoBefore - Return the VNInfo that is live up to but not
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/// necessarilly including Idx, or NULL. Use this to find the reaching def
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/// used by an instruction at this SlotIndex position.
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VNInfo *getVNInfoBefore(SlotIndex Idx) const {
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const_iterator I = FindLiveRangeContaining(Idx.getPrevIndex());
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return I == end() ? 0 : I->valno;
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}
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/// FindLiveRangeContaining - Return an iterator to the live range that
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/// contains the specified index, or end() if there is none.
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iterator FindLiveRangeContaining(SlotIndex Idx) {
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@ -692,7 +692,7 @@ bool RegisterCoalescer::RemoveCopyByCommutingDef(const CoalescerPair &CP,
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// If some of the uses of IntA.reg is already coalesced away, return false.
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// It's not possible to determine whether it's safe to perform the coalescing.
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for (MachineRegisterInfo::use_nodbg_iterator UI =
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for (MachineRegisterInfo::use_nodbg_iterator UI =
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MRI->use_nodbg_begin(IntA.reg),
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UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
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MachineInstr *UseMI = &*UI;
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@ -1370,6 +1370,7 @@ static unsigned ComputeUltimateVN(VNInfo *VNI,
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// which allows us to coalesce A and B.
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// VNI is the definition of B. LR is the life range of A that includes
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// the slot just before B. If we return true, we add "B = X" to DupCopies.
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// This implies that A dominates B.
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static bool RegistersDefinedFromSameValue(LiveIntervals &li,
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const TargetRegisterInfo &tri,
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CoalescerPair &CP,
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@ -1421,7 +1422,9 @@ static bool RegistersDefinedFromSameValue(LiveIntervals &li,
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// If the copies use two different value numbers of X, we cannot merge
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// A and B.
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LiveInterval &SrcInt = li.getInterval(Src);
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if (SrcInt.getVNInfoAt(Other->def) != SrcInt.getVNInfoAt(VNI->def))
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// getVNInfoBefore returns NULL for undef copies. In this case, the
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// optimization is still safe.
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if (SrcInt.getVNInfoBefore(Other->def) != SrcInt.getVNInfoBefore(VNI->def))
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return false;
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DupCopies.push_back(MI);
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@ -0,0 +1,115 @@
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; RUN: llc < %s -march=x86
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;
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; Test RegistersDefinedFromSameValue. We have multiple copies of the same vreg:
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; while.body85.i:
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; vreg1 = copy vreg2
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; vreg2 = add
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; critical edge from land.lhs.true.i -> if.end117.i:
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; vreg27 = vreg2
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; critical edge from land.lhs.true103.i -> if.end117.i:
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; vreg27 = vreg2
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; if.then108.i:
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; vreg27 = vreg1
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;
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; Prior to fixing PR10920 401.bzip miscompile, the coalescer would
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; consider vreg1 and vreg27 to be copies of the same value. It would
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; then remove one of the critical edge copes, which cannot safely be removed.
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
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@.str3 = external unnamed_addr constant [59 x i8], align 1
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define void @test() nounwind ssp {
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entry:
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br i1 undef, label %if.then68, label %if.end85
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if.then68: ; preds = %entry
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br label %for.body.i.i
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for.body.i.i: ; preds = %for.inc.i.i, %if.then68
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br i1 undef, label %for.inc.i.i, label %if.then.i.i
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if.then.i.i: ; preds = %for.body.i.i
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br label %for.inc.i.i
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for.inc.i.i: ; preds = %if.then.i.i, %for.body.i.i
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br i1 undef, label %makeMaps_e.exit.i, label %for.body.i.i
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makeMaps_e.exit.i: ; preds = %for.inc.i.i
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br i1 undef, label %for.cond19.preheader.i, label %for.cond.for.cond19.preheader_crit_edge.i
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for.cond.for.cond19.preheader_crit_edge.i: ; preds = %makeMaps_e.exit.i
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unreachable
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for.cond19.preheader.i: ; preds = %makeMaps_e.exit.i
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br i1 undef, label %if.then.i, label %if.end.i
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if.then.i: ; preds = %for.cond19.preheader.i
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br label %if.end.i
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if.end.i: ; preds = %if.then.i, %for.cond19.preheader.i
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br i1 undef, label %for.inc27.us.5.i, label %for.end30.i
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for.end30.i: ; preds = %if.end.i
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br i1 undef, label %if.end36.i, label %if.then35.i
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if.then35.i: ; preds = %for.end30.i
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unreachable
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if.end36.i: ; preds = %for.end30.i
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br label %while.body.i188
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for.cond182.preheader.i: ; preds = %for.cond138.preheader.i
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unreachable
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while.body.i188: ; preds = %for.cond138.preheader.i, %if.end36.i
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%sub.i187 = add nsw i32 0, -1
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br i1 undef, label %while.body85.i, label %if.end117.i
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while.body85.i: ; preds = %while.body85.i, %while.body.i188
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%ge.0519.i = phi i32 [ %inc87.i, %while.body85.i ], [ %sub.i187, %while.body.i188 ]
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%aFreq.0518.i = phi i32 [ %add93.i, %while.body85.i ], [ 0, %while.body.i188 ]
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%inc87.i = add nsw i32 %ge.0519.i, 1
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%tmp91.i = load i32* undef, align 4, !tbaa !0
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%add93.i = add nsw i32 %tmp91.i, %aFreq.0518.i
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%cmp84.i = icmp slt i32 %inc87.i, undef
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%or.cond514.i = and i1 undef, %cmp84.i
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br i1 %or.cond514.i, label %while.body85.i, label %while.end.i
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while.end.i: ; preds = %while.body85.i
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br i1 undef, label %land.lhs.true.i, label %if.end117.i
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land.lhs.true.i: ; preds = %while.end.i
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br i1 undef, label %if.end117.i, label %land.lhs.true103.i
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land.lhs.true103.i: ; preds = %land.lhs.true.i
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br i1 undef, label %if.then108.i, label %if.end117.i
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if.then108.i: ; preds = %land.lhs.true103.i
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br label %if.end117.i
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if.end117.i: ; preds = %if.then108.i, %land.lhs.true103.i, %land.lhs.true.i, %while.end.i, %while.body.i188
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%aFreq.1.i = phi i32 [ %aFreq.0518.i, %if.then108.i ], [ %add93.i, %land.lhs.true103.i ], [ %add93.i, %while.end.i ], [ 0, %while.body.i188 ], [ %add93.i, %land.lhs.true.i ]
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%cmp121.i = icmp sgt i32 undef, 2
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br i1 %cmp121.i, label %if.then122.i, label %for.cond138.preheader.i
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if.then122.i: ; preds = %if.end117.i
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call void (...)* @fprintf(i32 undef, i32 0, i32 undef, i32 %aFreq.1.i, double undef) nounwind
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unreachable
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for.cond138.preheader.i: ; preds = %if.end117.i
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%cmp73.i = icmp sgt i32 undef, 0
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br i1 %cmp73.i, label %while.body.i188, label %for.cond182.preheader.i
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for.inc27.us.5.i: ; preds = %if.end.i
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unreachable
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if.end85: ; preds = %entry
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ret void
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}
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declare void @fprintf(...) nounwind
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!0 = metadata !{metadata !"int", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
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