forked from OSchip/llvm-project
[X86] Allow masked VBROADCAST instructions to be turned into BLENDM with a broadcast load to avoid a copy.
The BLENDM instructions allow an 2 sources and an independent destination while masked VBROADCAST has the destination tied to the source. llvm-svn: 372068
This commit is contained in:
Craig Topper
parent
2cc57bedd5
commit
769dd59a27
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@ -1123,50 +1123,103 @@ multiclass avx512_broadcast_rm_split<bits<8> opc, string OpcodeStr,
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X86VectorVTInfo MaskInfo,
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X86VectorVTInfo DestInfo,
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X86VectorVTInfo SrcInfo,
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bit IsConvertibleToThreeAddress,
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SDPatternOperator UnmaskedOp = X86VBroadcast> {
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let ExeDomain = DestInfo.ExeDomain, hasSideEffects = 0 in {
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defm r : AVX512_maskable_split<opc, MRMSrcReg, MaskInfo,
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(outs MaskInfo.RC:$dst),
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(ins SrcInfo.RC:$src), OpcodeStr, "$src", "$src",
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(MaskInfo.VT
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(bitconvert
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(DestInfo.VT
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(UnmaskedOp (SrcInfo.VT SrcInfo.RC:$src))))),
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(MaskInfo.VT
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(bitconvert
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(DestInfo.VT
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(X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src)))))>,
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T8PD, EVEX, Sched<[SchedRR]>;
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let mayLoad = 1 in
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defm m : AVX512_maskable_split<opc, MRMSrcMem, MaskInfo,
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(outs MaskInfo.RC:$dst),
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(ins SrcInfo.ScalarMemOp:$src), OpcodeStr, "$src", "$src",
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(MaskInfo.VT
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(bitconvert
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(DestInfo.VT (UnmaskedOp
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(SrcInfo.ScalarLdFrag addr:$src))))),
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(MaskInfo.VT
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(bitconvert
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(DestInfo.VT (X86VBroadcast
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(SrcInfo.ScalarLdFrag addr:$src)))))>,
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T8PD, EVEX, EVEX_CD8<SrcInfo.EltSize, CD8VT1>,
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Sched<[SchedRM]>;
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}
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let hasSideEffects = 0 in
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def r : AVX512PI<opc, MRMSrcReg, (outs MaskInfo.RC:$dst), (ins SrcInfo.RC:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set MaskInfo.RC:$dst,
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(MaskInfo.VT
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(bitconvert
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(DestInfo.VT
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(UnmaskedOp (SrcInfo.VT SrcInfo.RC:$src))))))],
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DestInfo.ExeDomain>, T8PD, EVEX, Sched<[SchedRR]>;
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def rkz : AVX512PI<opc, MRMSrcReg, (outs MaskInfo.RC:$dst),
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(ins MaskInfo.KRCWM:$mask, SrcInfo.RC:$src),
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!strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
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"${dst} {${mask}} {z}, $src}"),
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[(set MaskInfo.RC:$dst,
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(vselect MaskInfo.KRCWM:$mask,
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(MaskInfo.VT
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(bitconvert
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(DestInfo.VT
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(X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))))),
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MaskInfo.ImmAllZerosV))],
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DestInfo.ExeDomain>, T8PD, EVEX, EVEX_KZ, Sched<[SchedRR]>;
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let Constraints = "$src0 = $dst" in
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def rk : AVX512PI<opc, MRMSrcReg, (outs MaskInfo.RC:$dst),
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(ins MaskInfo.RC:$src0, MaskInfo.KRCWM:$mask,
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SrcInfo.RC:$src),
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!strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}}|",
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"${dst} {${mask}}, $src}"),
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[(set MaskInfo.RC:$dst,
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(vselect MaskInfo.KRCWM:$mask,
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(MaskInfo.VT
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(bitconvert
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(DestInfo.VT
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(X86VBroadcast (SrcInfo.VT SrcInfo.RC:$src))))),
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MaskInfo.RC:$src0))],
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DestInfo.ExeDomain>, T8PD, EVEX, EVEX_K, Sched<[SchedRR]>;
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let hasSideEffects = 0, mayLoad = 1 in
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def m : AVX512PI<opc, MRMSrcMem, (outs MaskInfo.RC:$dst),
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(ins SrcInfo.ScalarMemOp:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set MaskInfo.RC:$dst,
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(MaskInfo.VT
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(bitconvert
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(DestInfo.VT
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(UnmaskedOp (SrcInfo.ScalarLdFrag addr:$src))))))],
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DestInfo.ExeDomain>, T8PD, EVEX,
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EVEX_CD8<SrcInfo.EltSize, CD8VT1>, Sched<[SchedRM]>;
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def mkz : AVX512PI<opc, MRMSrcMem, (outs MaskInfo.RC:$dst),
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(ins MaskInfo.KRCWM:$mask, SrcInfo.ScalarMemOp:$src),
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!strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
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"${dst} {${mask}} {z}, $src}"),
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[(set MaskInfo.RC:$dst,
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(vselect MaskInfo.KRCWM:$mask,
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(MaskInfo.VT
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(bitconvert
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(DestInfo.VT
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(X86VBroadcast (SrcInfo.ScalarLdFrag addr:$src))))),
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MaskInfo.ImmAllZerosV))],
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DestInfo.ExeDomain>, T8PD, EVEX, EVEX_KZ,
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EVEX_CD8<SrcInfo.EltSize, CD8VT1>, Sched<[SchedRM]>;
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let Constraints = "$src0 = $dst",
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isConvertibleToThreeAddress = IsConvertibleToThreeAddress in
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def mk : AVX512PI<opc, MRMSrcMem, (outs MaskInfo.RC:$dst),
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(ins MaskInfo.RC:$src0, MaskInfo.KRCWM:$mask,
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SrcInfo.ScalarMemOp:$src),
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!strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}}|",
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"${dst} {${mask}}, $src}"),
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[(set MaskInfo.RC:$dst,
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(vselect MaskInfo.KRCWM:$mask,
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(MaskInfo.VT
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(bitconvert
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(DestInfo.VT
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(X86VBroadcast (SrcInfo.ScalarLdFrag addr:$src))))),
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MaskInfo.RC:$src0))],
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DestInfo.ExeDomain>, T8PD, EVEX, EVEX_K,
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EVEX_CD8<SrcInfo.EltSize, CD8VT1>, Sched<[SchedRM]>;
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}
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// Helper class to force mask and broadcast result to same type.
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multiclass avx512_broadcast_rm<bits<8> opc, string OpcodeStr, string Name,
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SchedWrite SchedRR, SchedWrite SchedRM,
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X86VectorVTInfo DestInfo,
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X86VectorVTInfo SrcInfo> :
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X86VectorVTInfo SrcInfo,
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bit IsConvertibleToThreeAddress> :
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avx512_broadcast_rm_split<opc, OpcodeStr, Name, SchedRR, SchedRM,
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DestInfo, DestInfo, SrcInfo>;
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DestInfo, DestInfo, SrcInfo,
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IsConvertibleToThreeAddress>;
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multiclass avx512_fp_broadcast_sd<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo _> {
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let Predicates = [HasAVX512] in {
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defm Z : avx512_broadcast_rm<opc, OpcodeStr, NAME, WriteFShuffle256,
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WriteFShuffle256Ld, _.info512, _.info128>,
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WriteFShuffle256Ld, _.info512, _.info128, 1>,
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avx512_broadcast_scalar<opc, OpcodeStr, NAME, _.info512,
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_.info128>,
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EVEX_V512;
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@ -1174,7 +1227,7 @@ multiclass avx512_fp_broadcast_sd<bits<8> opc, string OpcodeStr,
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let Predicates = [HasVLX] in {
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defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, NAME, WriteFShuffle256,
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WriteFShuffle256Ld, _.info256, _.info128>,
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WriteFShuffle256Ld, _.info256, _.info128, 1>,
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avx512_broadcast_scalar<opc, OpcodeStr, NAME, _.info256,
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_.info128>,
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EVEX_V256;
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@ -1185,7 +1238,7 @@ multiclass avx512_fp_broadcast_ss<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo _> {
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let Predicates = [HasAVX512] in {
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defm Z : avx512_broadcast_rm<opc, OpcodeStr, NAME, WriteFShuffle256,
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WriteFShuffle256Ld, _.info512, _.info128>,
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WriteFShuffle256Ld, _.info512, _.info128, 1>,
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avx512_broadcast_scalar<opc, OpcodeStr, NAME, _.info512,
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_.info128>,
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EVEX_V512;
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@ -1193,12 +1246,12 @@ multiclass avx512_fp_broadcast_ss<bits<8> opc, string OpcodeStr,
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let Predicates = [HasVLX] in {
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defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, NAME, WriteFShuffle256,
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WriteFShuffle256Ld, _.info256, _.info128>,
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WriteFShuffle256Ld, _.info256, _.info128, 1>,
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avx512_broadcast_scalar<opc, OpcodeStr, NAME, _.info256,
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_.info128>,
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EVEX_V256;
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defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, NAME, WriteFShuffle256,
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WriteFShuffle256Ld, _.info128, _.info128>,
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WriteFShuffle256Ld, _.info128, _.info128, 1>,
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avx512_broadcast_scalar<opc, OpcodeStr, NAME, _.info128,
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_.info128>,
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EVEX_V128;
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@ -1283,30 +1336,34 @@ defm VPBROADCASTQr : avx512_int_broadcast_reg_vl<0x7C, avx512vl_i64_info,
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X86VBroadcast, GR64, HasAVX512>, VEX_W;
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multiclass avx512_int_broadcast_rm_vl<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo _, Predicate prd> {
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AVX512VLVectorVTInfo _, Predicate prd,
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bit IsConvertibleToThreeAddress> {
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let Predicates = [prd] in {
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defm Z : avx512_broadcast_rm<opc, OpcodeStr, NAME, WriteShuffle256,
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WriteShuffle256Ld, _.info512, _.info128>,
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WriteShuffle256Ld, _.info512, _.info128,
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IsConvertibleToThreeAddress>,
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EVEX_V512;
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}
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let Predicates = [prd, HasVLX] in {
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defm Z256 : avx512_broadcast_rm<opc, OpcodeStr, NAME, WriteShuffle256,
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WriteShuffle256Ld, _.info256, _.info128>,
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WriteShuffle256Ld, _.info256, _.info128,
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IsConvertibleToThreeAddress>,
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EVEX_V256;
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defm Z128 : avx512_broadcast_rm<opc, OpcodeStr, NAME, WriteShuffle,
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WriteShuffleXLd, _.info128, _.info128>,
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WriteShuffleXLd, _.info128, _.info128,
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IsConvertibleToThreeAddress>,
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EVEX_V128;
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}
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}
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defm VPBROADCASTB : avx512_int_broadcast_rm_vl<0x78, "vpbroadcastb",
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avx512vl_i8_info, HasBWI>;
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avx512vl_i8_info, HasBWI, 0>;
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defm VPBROADCASTW : avx512_int_broadcast_rm_vl<0x79, "vpbroadcastw",
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avx512vl_i16_info, HasBWI>;
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avx512vl_i16_info, HasBWI, 0>;
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defm VPBROADCASTD : avx512_int_broadcast_rm_vl<0x58, "vpbroadcastd",
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avx512vl_i32_info, HasAVX512>;
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avx512vl_i32_info, HasAVX512, 1>;
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defm VPBROADCASTQ : avx512_int_broadcast_rm_vl<0x59, "vpbroadcastq",
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avx512vl_i64_info, HasAVX512>, VEX_W1X;
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avx512vl_i64_info, HasAVX512, 1>, VEX_W1X;
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multiclass avx512_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
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X86VectorVTInfo _Dst, X86VectorVTInfo _Src> {
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@ -1612,12 +1669,12 @@ multiclass avx512_common_broadcast_32x2<bits<8> opc, string OpcodeStr,
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let Predicates = [HasDQI] in
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defm Z : avx512_broadcast_rm_split<opc, OpcodeStr, NAME, WriteShuffle256,
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WriteShuffle256Ld, _Dst.info512,
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_Src.info512, _Src.info128, null_frag>,
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_Src.info512, _Src.info128, 0, null_frag>,
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EVEX_V512;
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let Predicates = [HasDQI, HasVLX] in
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defm Z256 : avx512_broadcast_rm_split<opc, OpcodeStr, NAME, WriteShuffle256,
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WriteShuffle256Ld, _Dst.info256,
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_Src.info256, _Src.info128, null_frag>,
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_Src.info256, _Src.info128, 0, null_frag>,
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EVEX_V256;
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}
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@ -1628,7 +1685,7 @@ multiclass avx512_common_broadcast_i32x2<bits<8> opc, string OpcodeStr,
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let Predicates = [HasDQI, HasVLX] in
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defm Z128 : avx512_broadcast_rm_split<opc, OpcodeStr, NAME, WriteShuffle,
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WriteShuffleXLd, _Dst.info128,
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_Src.info128, _Src.info128, null_frag>,
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_Src.info128, _Src.info128, 0, null_frag>,
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EVEX_V128;
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}
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@ -1913,7 +1970,7 @@ multiclass WriteFVarBlendask<bits<8> opc, string OpcodeStr,
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}
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multiclass WriteFVarBlendask_rmb<bits<8> opc, string OpcodeStr,
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X86FoldableSchedWrite sched, X86VectorVTInfo _> {
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let mayLoad = 1, hasSideEffects = 0 in {
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let ExeDomain = _.ExeDomain, mayLoad = 1, hasSideEffects = 0 in {
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def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
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!strconcat(OpcodeStr,
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@ -1177,40 +1177,62 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
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case X86::VMOVUPDZrmk: case X86::VMOVAPDZrmk:
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case X86::VMOVUPSZ128rmk: case X86::VMOVAPSZ128rmk:
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case X86::VMOVUPSZ256rmk: case X86::VMOVAPSZ256rmk:
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case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk: {
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case X86::VMOVUPSZrmk: case X86::VMOVAPSZrmk:
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case X86::VBROADCASTSDZ256mk:
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case X86::VBROADCASTSDZmk:
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case X86::VBROADCASTSSZ128mk:
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case X86::VBROADCASTSSZ256mk:
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case X86::VBROADCASTSSZmk:
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case X86::VPBROADCASTDZ128mk:
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case X86::VPBROADCASTDZ256mk:
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case X86::VPBROADCASTDZmk:
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case X86::VPBROADCASTQZ128mk:
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case X86::VPBROADCASTQZ256mk:
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case X86::VPBROADCASTQZmk: {
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unsigned Opc;
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switch (MIOpc) {
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default: llvm_unreachable("Unreachable!");
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case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break;
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case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break;
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case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break;
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case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
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case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
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case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break;
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case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
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case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
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case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
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case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
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case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
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case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
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case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
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case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
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case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
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case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
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case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
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case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
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case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
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case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
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case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
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case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
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case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
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case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
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case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
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case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
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case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
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case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
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case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
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case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
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case X86::VMOVDQU8Z128rmk: Opc = X86::VPBLENDMBZ128rmk; break;
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case X86::VMOVDQU8Z256rmk: Opc = X86::VPBLENDMBZ256rmk; break;
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case X86::VMOVDQU8Zrmk: Opc = X86::VPBLENDMBZrmk; break;
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case X86::VMOVDQU16Z128rmk: Opc = X86::VPBLENDMWZ128rmk; break;
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case X86::VMOVDQU16Z256rmk: Opc = X86::VPBLENDMWZ256rmk; break;
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case X86::VMOVDQU16Zrmk: Opc = X86::VPBLENDMWZrmk; break;
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case X86::VMOVDQU32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
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case X86::VMOVDQU32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
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case X86::VMOVDQU32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
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case X86::VMOVDQU64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
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case X86::VMOVDQU64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
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case X86::VMOVDQU64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
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case X86::VMOVUPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
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case X86::VMOVUPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
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case X86::VMOVUPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
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case X86::VMOVUPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
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case X86::VMOVUPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
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||||
case X86::VMOVUPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
|
||||
case X86::VMOVDQA32Z128rmk: Opc = X86::VPBLENDMDZ128rmk; break;
|
||||
case X86::VMOVDQA32Z256rmk: Opc = X86::VPBLENDMDZ256rmk; break;
|
||||
case X86::VMOVDQA32Zrmk: Opc = X86::VPBLENDMDZrmk; break;
|
||||
case X86::VMOVDQA64Z128rmk: Opc = X86::VPBLENDMQZ128rmk; break;
|
||||
case X86::VMOVDQA64Z256rmk: Opc = X86::VPBLENDMQZ256rmk; break;
|
||||
case X86::VMOVDQA64Zrmk: Opc = X86::VPBLENDMQZrmk; break;
|
||||
case X86::VMOVAPDZ128rmk: Opc = X86::VBLENDMPDZ128rmk; break;
|
||||
case X86::VMOVAPDZ256rmk: Opc = X86::VBLENDMPDZ256rmk; break;
|
||||
case X86::VMOVAPDZrmk: Opc = X86::VBLENDMPDZrmk; break;
|
||||
case X86::VMOVAPSZ128rmk: Opc = X86::VBLENDMPSZ128rmk; break;
|
||||
case X86::VMOVAPSZ256rmk: Opc = X86::VBLENDMPSZ256rmk; break;
|
||||
case X86::VMOVAPSZrmk: Opc = X86::VBLENDMPSZrmk; break;
|
||||
case X86::VBROADCASTSDZ256mk: Opc = X86::VBLENDMPDZ256rmbk; break;
|
||||
case X86::VBROADCASTSDZmk: Opc = X86::VBLENDMPDZrmbk; break;
|
||||
case X86::VBROADCASTSSZ128mk: Opc = X86::VBLENDMPSZ128rmbk; break;
|
||||
case X86::VBROADCASTSSZ256mk: Opc = X86::VBLENDMPSZ256rmbk; break;
|
||||
case X86::VBROADCASTSSZmk: Opc = X86::VBLENDMPSZrmbk; break;
|
||||
case X86::VPBROADCASTDZ128mk: Opc = X86::VPBLENDMDZ128rmbk; break;
|
||||
case X86::VPBROADCASTDZ256mk: Opc = X86::VPBLENDMDZ256rmbk; break;
|
||||
case X86::VPBROADCASTDZmk: Opc = X86::VPBLENDMDZrmbk; break;
|
||||
case X86::VPBROADCASTQZ128mk: Opc = X86::VPBLENDMQZ128rmbk; break;
|
||||
case X86::VPBROADCASTQZ256mk: Opc = X86::VPBLENDMQZ256rmbk; break;
|
||||
case X86::VPBROADCASTQZmk: Opc = X86::VPBLENDMQZrmbk; break;
|
||||
}
|
||||
|
||||
NewMI = BuildMI(MF, MI.getDebugLoc(), get(Opc))
|
||||
|
|
@ -1224,6 +1246,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
|
|||
.add(MI.getOperand(7));
|
||||
break;
|
||||
}
|
||||
|
||||
case X86::VMOVDQU8Z128rrk:
|
||||
case X86::VMOVDQU8Z256rrk:
|
||||
case X86::VMOVDQU8Zrrk:
|
||||
|
|
|
|||
|
|
@ -4458,8 +4458,7 @@ define void @bcast_unfold_cmp_v8f32_refold(float* nocapture %0) {
|
|||
; CHECK-NEXT: .p2align 4, 0x90
|
||||
; CHECK-NEXT: .LBB126_1: # =>This Inner Loop Header: Depth=1
|
||||
; CHECK-NEXT: vcmpgtps 4096(%rdi,%rax), %ymm0, %k1
|
||||
; CHECK-NEXT: vmovaps %ymm1, %ymm2
|
||||
; CHECK-NEXT: vbroadcastss {{.*}}(%rip), %ymm2 {%k1}
|
||||
; CHECK-NEXT: vblendmps {{.*}}(%rip){1to8}, %ymm1, %ymm2 {%k1}
|
||||
; CHECK-NEXT: vmovups %ymm2, 4096(%rdi,%rax)
|
||||
; CHECK-NEXT: addq $32, %rax
|
||||
; CHECK-NEXT: jne .LBB126_1
|
||||
|
|
|
|||
Loading…
Reference in New Issue