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[DAGCombine] (x - C) - y -> (x - y) - C fold 

Summary:
Again only vectors affected. Frustrating. Let me take a look into that..

https://rise4fun.com/Alive/AAq

Reviewers: RKSimon, craig.topper, spatel

Reviewed By: RKSimon

Subscribers: javed.absar, JDevlieghere, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62294

llvm-svn: 361856
This commit is contained in:
Roman Lebedev 2019-05-28 17:54:21 +00:00
parent 8c9b3e4e4a
commit 7669665432
3 changed files with 10 additions and 3 deletions
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7
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -2957,6 +2957,13 @@ SDValue DAGCombiner::visitSUB(SDNode *N) {
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0)); SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0, N1.getOperand(0));
return DAG.getNode(ISD::SUB, DL, VT, Sub, N1.getOperand(1)); return DAG.getNode(ISD::SUB, DL, VT, Sub, N1.getOperand(1));
} }
// (x - C) - y -> (x - y) - C
// This is necessary because SUB(X,C) -> ADD(X,-C) doesn't work for vectors.
if (N0.hasOneUse() && N0.getOpcode() == ISD::SUB &&
isConstantOrConstantVector(N0.getOperand(1))) {
SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1);
return DAG.getNode(ISD::SUB, DL, VT, Sub, N0.getOperand(1));
}
// If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1' // If the target's bool is represented as 0/-1, prefer to make this 'add 0/-1'
// rather than 'sub 0/1' (the sext should get folded). // rather than 'sub 0/1' (the sext should get folded).

2
llvm/test/CodeGen/AArch64/sink-addsub-of-const.ll
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@ -314,8 +314,8 @@ define <4 x i32> @vec_sink_sub_of_const_to_sub(<4 x i32> %a, <4 x i32> %b, <4 x
; CHECK-NEXT: adrp x8, .LCPI20_0 ; CHECK-NEXT: adrp x8, .LCPI20_0
; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI20_0] ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI20_0]
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: sub v0.4s, v0.4s, v3.4s
; CHECK-NEXT: sub v0.4s, v0.4s, v2.4s ; CHECK-NEXT: sub v0.4s, v0.4s, v2.4s
; CHECK-NEXT: sub v0.4s, v0.4s, v3.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%t0 = sub <4 x i32> %a, %b %t0 = sub <4 x i32> %a, %b
%t1 = sub <4 x i32> %t0, <i32 42, i32 24, i32 undef, i32 46> %t1 = sub <4 x i32> %t0, <i32 42, i32 24, i32 undef, i32 46>

4
llvm/test/CodeGen/X86/sink-addsub-of-const.ll
View File

@ -460,15 +460,15 @@ define <4 x i32> @vec_sink_sub_of_const_to_sub(<4 x i32> %a, <4 x i32> %b, <4 x
; X32-LABEL: vec_sink_sub_of_const_to_sub: ; X32-LABEL: vec_sink_sub_of_const_to_sub:
; X32: # %bb.0: ; X32: # %bb.0:
; X32-NEXT: psubd %xmm1, %xmm0 ; X32-NEXT: psubd %xmm1, %xmm0
; X32-NEXT: psubd {{\.LCPI.*}}, %xmm0
; X32-NEXT: psubd %xmm2, %xmm0 ; X32-NEXT: psubd %xmm2, %xmm0
; X32-NEXT: psubd {{\.LCPI.*}}, %xmm0
; X32-NEXT: retl ; X32-NEXT: retl
; ;
; X64-LABEL: vec_sink_sub_of_const_to_sub: ; X64-LABEL: vec_sink_sub_of_const_to_sub:
; X64: # %bb.0: ; X64: # %bb.0:
; X64-NEXT: psubd %xmm1, %xmm0 ; X64-NEXT: psubd %xmm1, %xmm0
; X64-NEXT: psubd {{.*}}(%rip), %xmm0
; X64-NEXT: psubd %xmm2, %xmm0 ; X64-NEXT: psubd %xmm2, %xmm0
; X64-NEXT: psubd {{.*}}(%rip), %xmm0
; X64-NEXT: retq ; X64-NEXT: retq
%t0 = sub <4 x i32> %a, %b %t0 = sub <4 x i32> %a, %b
%t1 = sub <4 x i32> %t0, <i32 42, i32 24, i32 undef, i32 46> %t1 = sub <4 x i32> %t0, <i32 42, i32 24, i32 undef, i32 46>