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Regenerate PR19420 tests

This commit is contained in:
Simon Pilgrim 2020-07-02 18:30:34 +01:00
parent 769af95e65
commit 76673c65e7
1 changed files with 13 additions and 12 deletions
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25
llvm/test/Transforms/InstCombine/pr19420.ll
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@ -1,8 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -instcombine < %s | FileCheck %s
define <4 x i32> @test_FoldShiftByConstant_CreateSHL(<4 x i32> %in) {
; CHECK-LABEL: @test_FoldShiftByConstant_CreateSHL(
; CHECK-NEXT: [[VSHL_N:%.*]] = mul <4 x i32> %in, <i32 0, i32 -32, i32 0, i32 -32>
; CHECK-NEXT: [[VSHL_N:%.*]] = mul <4 x i32> [[IN:%.*]], <i32 0, i32 -32, i32 0, i32 -32>
; CHECK-NEXT: ret <4 x i32> [[VSHL_N]]
;
%mul.i = mul <4 x i32> %in, <i32 0, i32 -1, i32 0, i32 -1>
@ -12,7 +13,7 @@ define <4 x i32> @test_FoldShiftByConstant_CreateSHL(<4 x i32> %in) {
define <8 x i16> @test_FoldShiftByConstant_CreateSHL2(<8 x i16> %in) {
; CHECK-LABEL: @test_FoldShiftByConstant_CreateSHL2(
; CHECK-NEXT: [[VSHL_N:%.*]] = mul <8 x i16> %in, <i16 0, i16 -32, i16 0, i16 -32, i16 0, i16 -32, i16 0, i16 -32>
; CHECK-NEXT: [[VSHL_N:%.*]] = mul <8 x i16> [[IN:%.*]], <i16 0, i16 -32, i16 0, i16 -32, i16 0, i16 -32, i16 0, i16 -32>
; CHECK-NEXT: ret <8 x i16> [[VSHL_N]]
;
%mul.i = mul <8 x i16> %in, <i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1>
@ -22,8 +23,8 @@ define <8 x i16> @test_FoldShiftByConstant_CreateSHL2(<8 x i16> %in) {
define <16 x i8> @test_FoldShiftByConstant_CreateAnd(<16 x i8> %in0) {
; CHECK-LABEL: @test_FoldShiftByConstant_CreateAnd(
; CHECK-NEXT: [[VSRA_N2:%.*]] = mul <16 x i8> %in0, <i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33>
; CHECK-NEXT: [[VSHL_N:%.*]] = and <16 x i8> [[VSRA_N2]], <i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32>
; CHECK-NEXT: [[TMP1:%.*]] = mul <16 x i8> [[IN0:%.*]], <i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33, i8 33>
; CHECK-NEXT: [[VSHL_N:%.*]] = and <16 x i8> [[TMP1]], <i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32, i8 -32>
; CHECK-NEXT: ret <16 x i8> [[VSHL_N]]
;
%vsra_n = ashr <16 x i8> %in0, <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>
@ -34,8 +35,8 @@ define <16 x i8> @test_FoldShiftByConstant_CreateAnd(<16 x i8> %in0) {
define i32 @bar(i32 %x, i32 %y) {
; CHECK-LABEL: @bar(
; CHECK-NEXT: [[B1:%.*]] = shl i32 %y, 4
; CHECK-NEXT: [[A2:%.*]] = add i32 [[B1]], %x
; CHECK-NEXT: [[B1:%.*]] = shl i32 [[Y:%.*]], 4
; CHECK-NEXT: [[A2:%.*]] = add i32 [[B1]], [[X:%.*]]
; CHECK-NEXT: [[C:%.*]] = and i32 [[A2]], -16
; CHECK-NEXT: ret i32 [[C]]
;
@ -47,8 +48,8 @@ define i32 @bar(i32 %x, i32 %y) {
define <2 x i32> @bar_v2i32(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @bar_v2i32(
; CHECK-NEXT: [[B1:%.*]] = shl <2 x i32> %y, <i32 5, i32 5>
; CHECK-NEXT: [[A2:%.*]] = add <2 x i32> [[B1]], %x
; CHECK-NEXT: [[B1:%.*]] = shl <2 x i32> [[Y:%.*]], <i32 5, i32 5>
; CHECK-NEXT: [[A2:%.*]] = add <2 x i32> [[B1]], [[X:%.*]]
; CHECK-NEXT: [[C:%.*]] = and <2 x i32> [[A2]], <i32 -32, i32 -32>
; CHECK-NEXT: ret <2 x i32> [[C]]
;
@ -60,8 +61,8 @@ define <2 x i32> @bar_v2i32(<2 x i32> %x, <2 x i32> %y) {
define i32 @foo(i32 %x, i32 %y) {
; CHECK-LABEL: @foo(
; CHECK-NEXT: [[C1:%.*]] = shl i32 %y, 4
; CHECK-NEXT: [[X_MASK:%.*]] = and i32 %x, 128
; CHECK-NEXT: [[C1:%.*]] = shl i32 [[Y:%.*]], 4
; CHECK-NEXT: [[X_MASK:%.*]] = and i32 [[X:%.*]], 128
; CHECK-NEXT: [[D:%.*]] = add i32 [[X_MASK]], [[C1]]
; CHECK-NEXT: ret i32 [[D]]
;
@ -74,9 +75,9 @@ define i32 @foo(i32 %x, i32 %y) {
define <2 x i32> @foo_v2i32(<2 x i32> %x, <2 x i32> %y) {
; CHECK-LABEL: @foo_v2i32(
; CHECK-NEXT: [[A:%.*]] = lshr <2 x i32> %x, <i32 4, i32 4>
; CHECK-NEXT: [[A:%.*]] = lshr <2 x i32> [[X:%.*]], <i32 4, i32 4>
; CHECK-NEXT: [[B:%.*]] = and <2 x i32> [[A]], <i32 8, i32 8>
; CHECK-NEXT: [[C:%.*]] = add <2 x i32> [[B]], %y
; CHECK-NEXT: [[C:%.*]] = add <2 x i32> [[B]], [[Y:%.*]]
; CHECK-NEXT: [[D:%.*]] = shl <2 x i32> [[C]], <i32 4, i32 4>
; CHECK-NEXT: ret <2 x i32> [[D]]
;