forked from OSchip/llvm-project
[RISCV64] Emit correct lib call for fp(float/double) to ui/si
Since i32 is not legal in riscv64, it always promoted to i64 before emitting lib call and for conversions like float/double to int and float/double to unsigned int wrong lib call was emitted. This commit fix it using custom lowering. Differential Revision: https://reviews.llvm.org/D80526
This commit is contained in:
Kamlesh Kumar
parent
b2f2adee00
commit
7622ea5835
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@ -197,6 +197,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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setTruncStoreAction(MVT::f64, MVT::f16, Expand);
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}
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if (Subtarget.is64Bit() &&
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!(Subtarget.hasStdExtD() || Subtarget.hasStdExtF())) {
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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setOperationAction(ISD::STRICT_FP_TO_UINT, MVT::i32, Custom);
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setOperationAction(ISD::STRICT_FP_TO_SINT, MVT::i32, Custom);
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}
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setOperationAction(ISD::GlobalAddress, XLenVT, Custom);
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setOperationAction(ISD::BlockAddress, XLenVT, Custom);
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setOperationAction(ISD::ConstantPool, XLenVT, Custom);
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@ -904,6 +912,32 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
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switch (N->getOpcode()) {
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default:
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llvm_unreachable("Don't know how to custom type legalize this operation!");
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case ISD::STRICT_FP_TO_SINT:
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case ISD::STRICT_FP_TO_UINT:
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case ISD::FP_TO_SINT:
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case ISD::FP_TO_UINT: {
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bool IsStrict = N->isStrictFPOpcode();
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assert(N->getValueType(0) == MVT::i32 && Subtarget.is64Bit() &&
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"Unexpected custom legalisation");
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SDValue Op0 = IsStrict ? N->getOperand(1) : N->getOperand(0);
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RTLIB::Libcall LC;
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if (N->getOpcode() == ISD::FP_TO_SINT ||
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N->getOpcode() == ISD::STRICT_FP_TO_SINT)
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LC = RTLIB::getFPTOSINT(Op0.getValueType(), N->getValueType(0));
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else
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LC = RTLIB::getFPTOUINT(Op0.getValueType(), N->getValueType(0));
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MakeLibCallOptions CallOptions;
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EVT OpVT = Op0.getValueType();
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CallOptions.setTypeListBeforeSoften(OpVT, N->getValueType(0), true);
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SDValue Chain = IsStrict ? N->getOperand(0) : SDValue();
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SDValue Result;
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std::tie(Result, Chain) =
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makeLibCall(DAG, LC, N->getValueType(0), Op0, CallOptions, DL, Chain);
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Results.push_back(Result);
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if (IsStrict)
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Results.push_back(Chain);
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break;
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}
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case ISD::READCYCLECOUNTER: {
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assert(!Subtarget.is64Bit() &&
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"READCYCLECOUNTER only has custom type legalization on riscv32");
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@ -174,7 +174,7 @@ define i32 @fcvt_w_s(float %a) nounwind {
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: call __fixsfdi
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; RV64I-NEXT: call __fixsfsi
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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@ -187,7 +187,7 @@ define i32 @fcvt_wu_s(float %a) nounwind {
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: call __fixunssfdi
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; RV64I-NEXT: call __fixunssfsi
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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@ -710,3 +710,123 @@ define float @fp_trunc(double %a) nounwind {
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%conv = fptrunc double %a to float
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ret float %conv
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}
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define i32 @fp32_to_ui32(float %a) nounwind {
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; RV64I-LABEL: fp32_to_ui32:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: call __fixunssfsi
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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entry:
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%conv = fptoui float %a to i32
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ret i32 %conv
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}
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define i32 @fp32_to_si32(float %a) nounwind {
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; RV64I-LABEL: fp32_to_si32:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: call __fixsfsi
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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entry:
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%conv = fptosi float %a to i32
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ret i32 %conv
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}
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define i32 @fp64_to_ui32(double %a) nounwind {
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; RV64I-LABEL: fp64_to_ui32:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: call __fixunsdfsi
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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entry:
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%conv = fptoui double %a to i32
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ret i32 %conv
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}
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define i32 @fp64_to_si32(double %a) nounwind {
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; RV64I-LABEL: fp64_to_si32:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: call __fixdfsi
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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entry:
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%conv = fptosi double %a to i32
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ret i32 %conv
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}
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declare i32 @llvm.experimental.constrained.fptoui.i32.f32(float, metadata)
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declare i32 @llvm.experimental.constrained.fptosi.i32.f32(float, metadata)
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declare i32 @llvm.experimental.constrained.fptosi.i32.f64(double, metadata)
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declare i32 @llvm.experimental.constrained.fptoui.i32.f64(double, metadata)
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define i32 @strict_fp32_to_ui32(float %a) nounwind strictfp {
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; RV64I-LABEL: strict_fp32_to_ui32:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: call __fixunssfsi
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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entry:
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%conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f32(float %a, metadata !"fpexcept.strict")
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ret i32 %conv
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}
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define i32 @strict_fp32_to_si32(float %a) nounwind strictfp {
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; RV64I-LABEL: strict_fp32_to_si32:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: call __fixsfsi
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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entry:
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%conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f32(float %a, metadata !"fpexcept.strict")
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ret i32 %conv
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}
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define i32 @strict_fp64_to_ui32(double %a) nounwind strictfp {
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; RV64I-LABEL: strict_fp64_to_ui32:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: call __fixunsdfsi
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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entry:
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%conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.f64(double %a, metadata !"fpexcept.strict")
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ret i32 %conv
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}
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define i32 @struct_fp64_to_si32(double %a) nounwind strictfp {
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; RV64I-LABEL: struct_fp64_to_si32:
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; RV64I: # %bb.0: # %entry
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: call __fixdfsi
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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entry:
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%conv = tail call i32 @llvm.experimental.constrained.fptosi.i32.f64(double %a, metadata !"fpexcept.strict")
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ret i32 %conv
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}
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