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Fix a few doc typos, to cycle bots.

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Nico Weber 2019-12-08 18:51:48 -05:00
parent 0a5703458b
commit 761dd780ea
1 changed files with 6 additions and 6 deletions
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12
llvm/docs/AMDGPUUsage.rst
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@ -2134,23 +2134,23 @@ supported except by flat and scratch instructions in GFX9-GFX10.
The generic address space uses the hardware flat address support available in The generic address space uses the hardware flat address support available in
GFX7-GFX10. This uses two fixed ranges of virtual addresses (the private and GFX7-GFX10. This uses two fixed ranges of virtual addresses (the private and
local appertures), that are outside the range of addressible global memory, to local apertures), that are outside the range of addressible global memory, to
map from a flat address to a private or local address. map from a flat address to a private or local address.
FLAT instructions can take a flat address and access global, private (scratch) FLAT instructions can take a flat address and access global, private (scratch)
and group (LDS) memory depending in if the address is within one of the and group (LDS) memory depending in if the address is within one of the
apperture ranges. Flat access to scratch requires hardware aperture setup and aperture ranges. Flat access to scratch requires hardware aperture setup and
setup in the kernel prologue (see :ref:`amdgpu-amdhsa-flat-scratch`). Flat setup in the kernel prologue (see :ref:`amdgpu-amdhsa-flat-scratch`). Flat
access to LDS requires hardware aperture setup and M0 (GFX7-GFX8) register setup access to LDS requires hardware aperture setup and M0 (GFX7-GFX8) register setup
(see :ref:`amdgpu-amdhsa-m0`). (see :ref:`amdgpu-amdhsa-m0`).
To convert between a segment address and a flat address the base address of the To convert between a segment address and a flat address the base address of the
appertures address can be used. For GFX7-GFX8 these are available in the apertures address can be used. For GFX7-GFX8 these are available in the
:ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with :ref:`amdgpu-amdhsa-hsa-aql-queue` the address of which can be obtained with
Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For Queue Ptr SGPR (see :ref:`amdgpu-amdhsa-initial-kernel-execution-state`). For
GFX9-GFX10 the appature base addresses are directly available as inline constant GFX9-GFX10 the aperture base addresses are directly available as inline constant
registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``. In 64 bit registers ``SRC_SHARED_BASE/LIMIT`` and ``SRC_PRIVATE_BASE/LIMIT``. In 64 bit
address mode the apperture sizes are 2^32 bytes and the base is aligned to 2^32 address mode the aperture sizes are 2^32 bytes and the base is aligned to 2^32
which makes it easier to convert from flat to segment or segment to flat. which makes it easier to convert from flat to segment or segment to flat.
Image and Samplers Image and Samplers
@ -2884,7 +2884,7 @@ SGPR register initial state is defined in
FLAT SCRATCH BASE in flat FLAT SCRATCH BASE in flat
memory instructions that memory instructions that
access the scratch access the scratch
apperture. aperture.
The second SGPR is 32 bit The second SGPR is 32 bit
byte size of a single byte size of a single