maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[mips] Return an ArrayRef from MipsCC::intArgRegs() and remove MipsCC::numIntArgRegs() 

Summary: No functional change.

Reviewers: vmedic

Reviewed By: vmedic

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5265

llvm-svn: 217485
This commit is contained in:
Daniel Sanders 2014-09-10 10:37:03 +00:00
parent f5c90062ca
commit 75ee6b4302
2 changed files with 19 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
llvm/lib/Target/Mips/MipsISelLowering.cpp
View File

@ -3533,17 +3533,14 @@ void MipsTargetLowering::MipsCC::handleByValArg(unsigned ValNo, MVT ValVT,
ByValArgs.push_back(ByVal);
}
unsigned MipsTargetLowering::MipsCC::numIntArgRegs() const {
return Subtarget.isABI_O32() ? array_lengthof(O32IntRegs)
: array_lengthof(Mips64IntRegs);
}
unsigned MipsTargetLowering::MipsCC::reservedArgArea() const {
return (Subtarget.isABI_O32() && (CallConv != CallingConv::Fast)) ? 16 : 0;
}
const MCPhysReg *MipsTargetLowering::MipsCC::intArgRegs() const {
return Subtarget.isABI_O32() ? O32IntRegs : Mips64IntRegs;
const ArrayRef<MCPhysReg> MipsTargetLowering::MipsCC::intArgRegs() const {
if (Subtarget.isABI_O32())
return makeArrayRef(O32IntRegs);
return makeArrayRef(Mips64IntRegs);
}
llvm::CCAssignFn *MipsTargetLowering::MipsCC::fixedArgFn() const {
@ -3571,13 +3568,14 @@ void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
unsigned ByValSize,
unsigned Align) {
unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
unsigned NumIntArgRegs = numIntArgRegs();
const MCPhysReg *IntArgRegs = intArgRegs(), *ShadowRegs = shadowRegs();
const ArrayRef<MCPhysReg> IntArgRegs = intArgRegs();
const MCPhysReg *ShadowRegs = shadowRegs();
assert(!(ByValSize % RegSizeInBytes) && !(Align % RegSizeInBytes) &&
"Byval argument's size and alignment should be a multiple of"
"RegSizeInBytes.");
ByVal.FirstIdx = CCInfo.getFirstUnallocated(IntArgRegs, NumIntArgRegs);
ByVal.FirstIdx =
CCInfo.getFirstUnallocated(IntArgRegs.data(), IntArgRegs.size());
// If Align > RegSizeInBytes, the first arg register must be even.
if ((Align > RegSizeInBytes) && (ByVal.FirstIdx % 2)) {
@ -3586,7 +3584,7 @@ void MipsTargetLowering::MipsCC::allocateRegs(ByValArgInfo &ByVal,
}
// Mark the registers allocated.
for (unsigned I = ByVal.FirstIdx; ByValSize && (I < NumIntArgRegs);
for (unsigned I = ByVal.FirstIdx; ByValSize && (I < IntArgRegs.size());
ByValSize -= RegSizeInBytes, ++I, ++ByVal.NumRegs)
CCInfo.AllocateReg(IntArgRegs[I], ShadowRegs[I]);
}
@ -3621,7 +3619,7 @@ copyByValRegs(SDValue Chain, SDLoc DL, std::vector<SDValue> &OutChains,
if (RegAreaSize)
FrameObjOffset =
(int)CC.reservedArgArea() -
(int)((CC.numIntArgRegs() - ByVal.FirstIdx) * GPRSizeInBytes);
(int)((CC.intArgRegs().size() - ByVal.FirstIdx) * GPRSizeInBytes);
else
FrameObjOffset = ByVal.Address;
@ -3666,7 +3664,7 @@ passByValArg(SDValue Chain, SDLoc DL,
EVT PtrTy = getPointerTy(), RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
if (ByVal.NumRegs) {
const MCPhysReg *ArgRegs = CC.intArgRegs();
const ArrayRef<MCPhysReg> ArgRegs = CC.intArgRegs();
bool LeftoverBytes = (ByVal.NumRegs * RegSizeInBytes > ByValSizeInBytes);
unsigned I = 0;
@ -3752,10 +3750,9 @@ passByValArg(SDValue Chain, SDLoc DL,
void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
const MipsCC &CC, SDValue Chain,
SDLoc DL, SelectionDAG &DAG) const {
unsigned NumRegs = CC.numIntArgRegs();
const MCPhysReg *ArgRegs = CC.intArgRegs();
const ArrayRef<MCPhysReg> ArgRegs = CC.intArgRegs();
const CCState &CCInfo = CC.getCCInfo();
unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs);
unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs.data(), ArgRegs.size());
unsigned RegSizeInBytes = Subtarget.getGPRSizeInBytes();
MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8);
const TargetRegisterClass *RC = getRegClassFor(RegTy);
@ -3766,12 +3763,12 @@ void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
// Offset of the first variable argument from stack pointer.
int VaArgOffset;
if (NumRegs == Idx)
if (ArgRegs.size() == Idx)
VaArgOffset =
RoundUpToAlignment(CCInfo.getNextStackOffset(), RegSizeInBytes);
else
VaArgOffset =
(int)CC.reservedArgArea() - (int)(RegSizeInBytes * (NumRegs - Idx));
VaArgOffset = (int)CC.reservedArgArea() -
(int)(RegSizeInBytes * (ArgRegs.size() - Idx));
// Record the frame index of the first variable argument
// which is a value necessary to VASTART.
@ -3782,7 +3779,8 @@ void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains,
// to the argument register save area. For O32, the save area is allocated
// in the caller's stack frame, while for N32/64, it is allocated in the
// callee's stack frame.
for (unsigned I = Idx; I < NumRegs; ++I, VaArgOffset += RegSizeInBytes) {
for (unsigned I = Idx; I < ArgRegs.size();
++I, VaArgOffset += RegSizeInBytes) {
unsigned Reg = addLiveIn(MF, ArgRegs[I], RC);
SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy);
FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true);

5
llvm/lib/Target/Mips/MipsISelLowering.h
View File

@ -379,15 +379,12 @@ namespace llvm {
/// hasByValArg - Returns true if function has byval arguments.
bool hasByValArg() const { return !ByValArgs.empty(); }
/// numIntArgRegs - Number of integer registers available for calls.
unsigned numIntArgRegs() const;
/// reservedArgArea - The size of the area the caller reserves for
/// register arguments. This is 16-byte if ABI is O32.
unsigned reservedArgArea() const;
/// Return pointer to array of integer argument registers.
const MCPhysReg *intArgRegs() const;
const ArrayRef<MCPhysReg> intArgRegs() const;
typedef SmallVectorImpl<ByValArgInfo>::const_iterator byval_iterator;
byval_iterator byval_begin() const { return ByValArgs.begin(); }