forked from OSchip/llvm-project
GlobalISel: refactor legalization of G_INSERT.
Now that G_INSERT instructions can only insert one register, this code was overly general. In another direction it didn't handle registers that crossed split boundaries properly, which needed to be fixed. llvm-svn: 297042
This commit is contained in:
Tim Northover
parent
c494239bd8
commit
75e0b91e59
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@ -95,15 +95,6 @@ private:
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void extractParts(unsigned Reg, LLT Ty, int NumParts,
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SmallVectorImpl<unsigned> &Ops);
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/// Set \p CurOp and \p EndOp to the range of G_INSERT operands that fall
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/// inside the bit-range specified by \DstStart and \p DstEnd. Assumes \p
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/// CurOp is initially pointing at one of the (Reg, Offset) pairs in \p MI (or
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/// at the end), which should be a G_INSERT instruction.
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void findInsertionsForRange(int64_t DstStart, int64_t DstEnd,
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MachineInstr::mop_iterator &CurOp,
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MachineInstr::mop_iterator &EndOp,
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MachineInstr &MI);
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MachineIRBuilder MIRBuilder;
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MachineRegisterInfo &MRI;
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};
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@ -127,17 +127,6 @@ LegalizerHelper::libcall(MachineInstr &MI) {
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}
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}
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void LegalizerHelper::findInsertionsForRange(
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int64_t DstStart, int64_t DstEnd, MachineInstr::mop_iterator &CurOp,
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MachineInstr::mop_iterator &EndOp, MachineInstr &MI) {
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while (CurOp != MI.operands_end() && std::next(CurOp)->getImm() < DstStart)
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CurOp += 2;
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EndOp = CurOp;
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while (EndOp != MI.operands_end() && std::next(EndOp)->getImm() < DstEnd)
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EndOp += 2;
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}
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LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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unsigned TypeIdx,
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LLT NarrowTy) {
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@ -181,7 +170,7 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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if (TypeIdx != 0)
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return UnableToLegalize;
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unsigned NarrowSize = NarrowTy.getSizeInBits();
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int64_t NarrowSize = NarrowTy.getSizeInBits();
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int NumParts =
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MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
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@ -189,44 +178,41 @@ LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
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SmallVector<uint64_t, 2> Indexes;
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extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
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MachineInstr::mop_iterator CurOp = MI.operands_begin() + 2, EndOp;
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unsigned OpReg = MI.getOperand(2).getReg();
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int64_t OpStart = MI.getOperand(3).getImm();
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int64_t OpSize = MRI.getType(OpReg).getSizeInBits();
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for (int i = 0; i < NumParts; ++i) {
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unsigned DstStart = i * NarrowSize;
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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findInsertionsForRange(DstStart, DstStart + NarrowSize, CurOp, EndOp, MI);
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if (CurOp == EndOp) {
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if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
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// No part of the insert affects this subregister, forward the original.
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DstRegs.push_back(SrcRegs[i]);
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continue;
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} else if (MRI.getType(CurOp->getReg()) == NarrowTy &&
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std::next(CurOp)->getImm() == DstStart) {
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} else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
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// The entire subregister is defined by this insert, forward the new
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// value.
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DstRegs.push_back(CurOp->getReg());
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DstRegs.push_back(OpReg);
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continue;
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}
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auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_INSERT)
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.addDef(DstReg)
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.addUse(SrcRegs[i]);
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for (; CurOp != EndOp; CurOp += 2) {
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unsigned Reg = CurOp->getReg();
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uint64_t Offset = std::next(CurOp)->getImm() - DstStart;
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// Make sure we don't have a cross-register insert.
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if (Offset + MRI.getType(Reg).getSizeInBits() > NarrowSize) {
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// FIXME: we should handle this case, though it's unlikely to be
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// common given ABI-related layout restrictions.
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return UnableToLegalize;
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}
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MIB.addUse(Reg);
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MIB.addImm(Offset);
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int64_t OpSegStart = DstStart - OpStart;
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int64_t OpSegSize =
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std::min(NarrowSize - OpSegStart, OpSegStart + OpSize);
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unsigned OpSegReg = OpReg;
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if (OpSegSize != OpSize) {
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// A genuine extract is needed.
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OpSegReg = MRI.createGenericVirtualRegister(LLT::scalar(OpSegSize));
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MIRBuilder.buildExtract(OpSegReg, std::max(OpSegStart, (int64_t)0),
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OpReg);
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}
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unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
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MIRBuilder.buildInstr(TargetOpcode::G_INSERT)
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.addDef(DstReg)
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.addUse(SrcRegs[i])
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.addUse(OpSegReg)
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.addImm(std::max((int64_t)0, -OpSegStart));
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DstRegs.push_back(DstReg);
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}
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@ -73,7 +73,7 @@ define void @odd_type(i42* %addr) {
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; RegBankSelect crashed when given invalid mappings, and AArch64's
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; implementation produce valid-but-nonsense mappings for G_SEQUENCE.
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction: %vreg0<def>(s128) = G_SEQUENCE %vreg1, 0, %vreg2, 64; GPR:%vreg1,%vreg2 (in function: sequence_mapping)
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for sequence_mapping
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; FALLBACK-WITH-REPORT-OUT-LABEL: sequence_mapping:
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define void @sequence_mapping([2 x i64] %in) {
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@ -81,7 +81,7 @@ define void @sequence_mapping([2 x i64] %in) {
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}
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; Legalizer was asserting when it enountered an unexpected default action.
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg9<def>(s128) = G_INSERT %vreg10, %vreg0, 32; (in function: legal_default)
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; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction
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; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for legal_default
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; FALLBACK-WITH-REPORT-LABEL: legal_default:
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define void @legal_default([8 x i8] %in) {
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@ -7,6 +7,7 @@
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define void @test_inserts_2() { ret void }
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define void @test_inserts_3() { ret void }
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define void @test_inserts_4() { ret void }
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define void @test_inserts_5() { ret void }
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...
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---
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@ -98,3 +99,24 @@ body: |
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G_STORE %3(s8), %2(p0) :: (store 1)
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RET_ReallyLR
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...
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---
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name: test_inserts_5
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body: |
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bb.0:
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liveins: %x0, %x1, %x2
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; CHECK-LABEL: name: test_inserts_5
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; CHECK: [[INS_LO:%[0-9]+]](s32) = G_EXTRACT %2(s64), 0
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; CHECK: [[VAL_LO:%[0-9]+]](s64) = G_INSERT %0, [[INS_LO]](s32), 32
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; CHECK: [[INS_HI:%[0-9]+]](s32) = G_EXTRACT %2(s64), 32
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; CHECK: [[VAL_HI:%[0-9]+]](s64) = G_INSERT %1, [[INS_HI]](s32), 0
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; CHECK: %4(s128) = G_MERGE_VALUES [[VAL_LO]](s64), [[VAL_HI]](s64)
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%0:_(s64) = COPY %x0
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%1:_(s64) = COPY %x1
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%2:_(s64) = COPY %x2
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%3:_(s128) = G_MERGE_VALUES %0, %1
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%4:_(s128) = G_INSERT %3, %2, 32
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RET_ReallyLR
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...
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