forked from OSchip/llvm-project
[AArch64][SVE2] Asm: support Floating Point Widening Multiply-Add
Summary: Patch adds support for the indexed and unpredicated vectors forms of the FMLALB, FMLALT, FMLSLB and FMLSLT instructions. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: chill Differential Revision: https://reviews.llvm.org/D62386 llvm-svn: 361935
This commit is contained in:
Cullen Rhodes
parent
d61cb749f4
commit
75dfbdc2da
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@ -1301,6 +1301,18 @@ let Predicates = [HasSVE2] in {
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defm FMAXP_ZPmZZ : sve2_fp_pairwise_pred<0b110, "fmaxp">;
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defm FMINP_ZPmZZ : sve2_fp_pairwise_pred<0b111, "fminp">;
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// SVE2 floating-point multiply-add long (indexed)
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def FMLALB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b00, "fmlalb">;
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def FMLALT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b01, "fmlalt">;
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def FMLSLB_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b10, "fmlslb">;
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def FMLSLT_ZZZI_SHH : sve2_fp_mla_long_by_indexed_elem<0b11, "fmlslt">;
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// SVE2 floating-point multiply-add long
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def FMLALB_ZZZ_SHH : sve2_fp_mla_long<0b00, "fmlalb">;
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def FMLALT_ZZZ_SHH : sve2_fp_mla_long<0b01, "fmlalt">;
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def FMLSLB_ZZZ_SHH : sve2_fp_mla_long<0b10, "fmlslb">;
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def FMLSLT_ZZZ_SHH : sve2_fp_mla_long<0b11, "fmlslt">;
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// Predicated shifts
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defm SQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0110, "sqshl">;
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defm UQSHL_ZPmI : sve_int_bin_pred_shift_imm_left< 0b0111, "uqshl">;
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@ -1505,6 +1505,62 @@ multiclass sve2_fp_pairwise_pred<bits<3> opc, string asm> {
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def _D : sve2_fp_pairwise_pred<0b11, opc, asm, ZPR64>;
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}
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//===----------------------------------------------------------------------===//
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// SVE2 Floating Point Widening Multiply-Add - Indexed Group
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//===----------------------------------------------------------------------===//
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class sve2_fp_mla_long_by_indexed_elem<bits<2> opc, string asm>
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: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR3b16:$Zm,
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VectorIndexH:$iop),
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asm, "\t$Zda, $Zn, $Zm$iop",
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"",
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[]>, Sched<[]> {
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bits<5> Zda;
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bits<5> Zn;
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bits<3> Zm;
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bits<3> iop;
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let Inst{31-21} = 0b01100100101;
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let Inst{20-19} = iop{2-1};
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let Inst{18-16} = Zm;
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let Inst{15-14} = 0b01;
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let Inst{13} = opc{1};
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let Inst{12} = 0b0;
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let Inst{11} = iop{0};
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let Inst{10} = opc{0};
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zda;
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let Constraints = "$Zda = $_Zda";
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let DestructiveInstType = Destructive;
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let ElementSize = ElementSizeNone;
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}
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//===----------------------------------------------------------------------===//
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// SVE2 Floating Point Widening Multiply-Add Group
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//===----------------------------------------------------------------------===//
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class sve2_fp_mla_long<bits<2> opc, string asm>
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: I<(outs ZPR32:$Zda), (ins ZPR32:$_Zda, ZPR16:$Zn, ZPR16:$Zm),
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asm, "\t$Zda, $Zn, $Zm",
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"",
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[]>, Sched<[]> {
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bits<5> Zda;
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bits<5> Zn;
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bits<5> Zm;
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let Inst{31-21} = 0b01100100101;
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let Inst{20-16} = Zm;
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let Inst{15-14} = 0b10;
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let Inst{13} = opc{1};
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let Inst{12-11} = 0b00;
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let Inst{10} = opc{0};
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let Inst{9-5} = Zn;
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let Inst{4-0} = Zda;
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let Constraints = "$Zda = $_Zda";
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let DestructiveInstType = Destructive;
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let ElementSize = ElementSizeNone;
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}
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//===----------------------------------------------------------------------===//
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// SVE Stack Allocation Group
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//===----------------------------------------------------------------------===//
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@ -110,6 +110,16 @@ mla z0.d, p0/m, z0.d, z2.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Destination used in other operand (ternary + indexed)
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movprfx z0, z1
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sdot z0.s, z1.b, z0.b[3]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a movprfx and destination also used as non-destructive source
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// CHECK-NEXT: sdot z0.s, z1.b, z0.b[3]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Different general predicate (unary)
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@ -0,0 +1,71 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// z register out of range for index
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fmlalb z0.s, z1.h, z8.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fmlalb z0.s, z1.h, z8.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Index out of bounds
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fmlalb z0.s, z1.h, z7.h[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmlalb z0.s, z1.h, z7.h[8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[8]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element width
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fmlalb z0.s, z1.b, z2.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmlalb z0.s, z1.b, z2.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmlalb z0.s, z1.s, z2.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmlalb z0.s, z1.s, z2.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmlalb z0.s, z1.d, z2.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmlalb z0.s, z1.d, z2.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmlalb z0.s, z1.b, z2.b[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmlalb z0.s, z1.b, z2.b[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmlalb z0.s, z1.s, z2.s[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmlalb z0.s, z1.s, z2.s[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmlalb z0.s, z1.d, z2.d[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmlalb z0.s, z1.d, z2.d[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z29.s, p0/z, z7.s
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fmlalb z29.s, z30.h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: fmlalb z29.s, z30.h, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0.s, p0/z, z7.s
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fmlalb z0.s, z1.h, z7.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: fmlalb z0.s, z1.h, z7.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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@ -0,0 +1,54 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
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// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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fmlalb z29.s, z30.h, z31.h
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// CHECK-INST: fmlalb z29.s, z30.h, z31.h
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// CHECK-ENCODING: [0xdd,0x83,0xbf,0x64]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: dd 83 bf 64 <unknown>
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fmlalb z0.s, z1.h, z7.h[0]
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// CHECK-INST: fmlalb z0.s, z1.h, z7.h[0]
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// CHECK-ENCODING: [0x20,0x40,0xa7,0x64]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: 20 40 a7 64 <unknown>
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fmlalb z30.s, z31.h, z7.h[7]
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// CHECK-INST: fmlalb z30.s, z31.h, z7.h[7]
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// CHECK-ENCODING: [0xfe,0x4b,0xbf,0x64]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: fe 4b bf 64 <unknown>
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// --------------------------------------------------------------------------//
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// Test compatibility with MOVPRFX instruction.
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movprfx z29, z28
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// CHECK-INST: movprfx z29, z28
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// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
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fmlalb z29.s, z30.h, z31.h
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// CHECK-INST: fmlalb z29.s, z30.h, z31.h
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// CHECK-ENCODING: [0xdd,0x83,0xbf,0x64]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: dd 83 bf 64 <unknown>
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movprfx z21, z28
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// CHECK-INST: movprfx z21, z28
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// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
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fmlalb z21.s, z1.h, z7.h[7]
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// CHECK-INST: fmlalb z21.s, z1.h, z7.h[7]
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// CHECK-ENCODING: [0x35,0x48,0xbf,0x64]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: 35 48 bf 64 <unknown>
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@ -0,0 +1,71 @@
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
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// ------------------------------------------------------------------------- //
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// z register out of range for index
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fmlalt z0.s, z1.h, z8.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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// CHECK-NEXT: fmlalt z0.s, z1.h, z8.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Index out of bounds
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fmlalt z0.s, z1.h, z7.h[-1]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[-1]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmlalt z0.s, z1.h, z7.h[8]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
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// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[8]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// ------------------------------------------------------------------------- //
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// Invalid element width
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fmlalt z0.s, z1.b, z2.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmlalt z0.s, z1.b, z2.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmlalt z0.s, z1.s, z2.s
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmlalt z0.s, z1.s, z2.s
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmlalt z0.s, z1.d, z2.d
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmlalt z0.s, z1.d, z2.d
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmlalt z0.s, z1.b, z2.b[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmlalt z0.s, z1.b, z2.b[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmlalt z0.s, z1.s, z2.s[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmlalt z0.s, z1.s, z2.s[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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fmlalt z0.s, z1.d, z2.d[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
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// CHECK-NEXT: fmlalt z0.s, z1.d, z2.d[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// --------------------------------------------------------------------------//
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// Negative tests for instructions that are incompatible with movprfx
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movprfx z29.s, p0/z, z7.s
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fmlalt z29.s, z30.h, z31.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: fmlalt z29.s, z30.h, z31.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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movprfx z0.s, p0/z, z7.s
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fmlalt z0.s, z1.h, z7.h[0]
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
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// CHECK-NEXT: fmlalt z0.s, z1.h, z7.h[0]
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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@ -0,0 +1,54 @@
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// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
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// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
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// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
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// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
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// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
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// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
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// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
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fmlalt z29.s, z30.h, z31.h
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// CHECK-INST: fmlalt z29.s, z30.h, z31.h
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// CHECK-ENCODING: [0xdd,0x87,0xbf,0x64]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: dd 87 bf 64 <unknown>
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fmlalt z0.s, z1.h, z7.h[0]
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// CHECK-INST: fmlalt z0.s, z1.h, z7.h[0]
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// CHECK-ENCODING: [0x20,0x44,0xa7,0x64]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: 20 44 a7 64 <unknown>
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fmlalt z30.s, z31.h, z7.h[7]
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// CHECK-INST: fmlalt z30.s, z31.h, z7.h[7]
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// CHECK-ENCODING: [0xfe,0x4f,0xbf,0x64]
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// CHECK-ERROR: instruction requires: sve2
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// CHECK-UNKNOWN: fe 4f bf 64 <unknown>
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// --------------------------------------------------------------------------//
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// Test compatibility with MOVPRFX instruction.
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movprfx z29, z28
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// CHECK-INST: movprfx z29, z28
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// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
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// CHECK-ERROR: instruction requires: sve
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// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
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fmlalt z29.s, z30.h, z31.h
|
||||
// CHECK-INST: fmlalt z29.s, z30.h, z31.h
|
||||
// CHECK-ENCODING: [0xdd,0x87,0xbf,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve2
|
||||
// CHECK-UNKNOWN: dd 87 bf 64 <unknown>
|
||||
|
||||
movprfx z21, z28
|
||||
// CHECK-INST: movprfx z21, z28
|
||||
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
|
||||
|
||||
fmlalt z21.s, z1.h, z7.h[7]
|
||||
// CHECK-INST: fmlalt z21.s, z1.h, z7.h[7]
|
||||
// CHECK-ENCODING: [0x35,0x4c,0xbf,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve2
|
||||
// CHECK-UNKNOWN: 35 4c bf 64 <unknown>
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// z register out of range for index
|
||||
|
||||
fmlslb z0.s, z1.h, z8.h[0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: fmlslb z0.s, z1.h, z8.h[0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Index out of bounds
|
||||
|
||||
fmlslb z0.s, z1.h, z7.h[-1]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
|
||||
// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[-1]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fmlslb z0.s, z1.h, z7.h[8]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
|
||||
// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[8]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Invalid element width
|
||||
|
||||
fmlslb z0.s, z1.b, z2.b
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fmlslb z0.s, z1.b, z2.b
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fmlslb z0.s, z1.s, z2.s
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fmlslb z0.s, z1.s, z2.s
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fmlslb z0.s, z1.d, z2.d
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fmlslb z0.s, z1.d, z2.d
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fmlslb z0.s, z1.b, z2.b[0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fmlslb z0.s, z1.b, z2.b[0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fmlslb z0.s, z1.s, z2.s[0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fmlslb z0.s, z1.s, z2.s[0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fmlslb z0.s, z1.d, z2.d[0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fmlslb z0.s, z1.d, z2.d[0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Negative tests for instructions that are incompatible with movprfx
|
||||
|
||||
movprfx z29.s, p0/z, z7.s
|
||||
fmlslb z29.s, z30.h, z31.h
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
|
||||
// CHECK-NEXT: fmlslb z29.s, z30.h, z31.h
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
movprfx z0.s, p0/z, z7.s
|
||||
fmlslb z0.s, z1.h, z7.h[0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
|
||||
// CHECK-NEXT: fmlslb z0.s, z1.h, z7.h[0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
|
||||
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
|
||||
fmlslb z29.s, z30.h, z31.h
|
||||
// CHECK-INST: fmlslb z29.s, z30.h, z31.h
|
||||
// CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve2
|
||||
// CHECK-UNKNOWN: dd a3 bf 64 <unknown>
|
||||
|
||||
fmlslb z0.s, z1.h, z7.h[0]
|
||||
// CHECK-INST: fmlslb z0.s, z1.h, z7.h[0]
|
||||
// CHECK-ENCODING: [0x20,0x60,0xa7,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve2
|
||||
// CHECK-UNKNOWN: 20 60 a7 64 <unknown>
|
||||
|
||||
fmlslb z30.s, z31.h, z7.h[7]
|
||||
// CHECK-INST: fmlslb z30.s, z31.h, z7.h[7]
|
||||
// CHECK-ENCODING: [0xfe,0x6b,0xbf,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve2
|
||||
// CHECK-UNKNOWN: fe 6b bf 64 <unknown>
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Test compatibility with MOVPRFX instruction.
|
||||
|
||||
movprfx z29, z28
|
||||
// CHECK-INST: movprfx z29, z28
|
||||
// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
|
||||
|
||||
fmlslb z29.s, z30.h, z31.h
|
||||
// CHECK-INST: fmlslb z29.s, z30.h, z31.h
|
||||
// CHECK-ENCODING: [0xdd,0xa3,0xbf,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve2
|
||||
// CHECK-UNKNOWN: dd a3 bf 64 <unknown>
|
||||
|
||||
movprfx z21, z28
|
||||
// CHECK-INST: movprfx z21, z28
|
||||
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
|
||||
|
||||
fmlslb z21.s, z1.h, z7.h[7]
|
||||
// CHECK-INST: fmlslb z21.s, z1.h, z7.h[7]
|
||||
// CHECK-ENCODING: [0x35,0x68,0xbf,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve2
|
||||
// CHECK-UNKNOWN: 35 68 bf 64 <unknown>
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 2>&1 < %s| FileCheck %s
|
||||
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// z register out of range for index
|
||||
|
||||
fmlslt z0.s, z1.h, z8.h[0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
|
||||
// CHECK-NEXT: fmlslt z0.s, z1.h, z8.h[0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Index out of bounds
|
||||
|
||||
fmlslt z0.s, z1.h, z7.h[-1]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
|
||||
// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[-1]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fmlslt z0.s, z1.h, z7.h[8]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
|
||||
// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[8]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
// ------------------------------------------------------------------------- //
|
||||
// Invalid element width
|
||||
|
||||
fmlslt z0.s, z1.b, z2.b
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fmlslt z0.s, z1.b, z2.b
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fmlslt z0.s, z1.s, z2.s
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fmlslt z0.s, z1.s, z2.s
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fmlslt z0.s, z1.d, z2.d
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fmlslt z0.s, z1.d, z2.d
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fmlslt z0.s, z1.b, z2.b[0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fmlslt z0.s, z1.b, z2.b[0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fmlslt z0.s, z1.s, z2.s[0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fmlslt z0.s, z1.s, z2.s[0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
fmlslt z0.s, z1.d, z2.d[0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
|
||||
// CHECK-NEXT: fmlslt z0.s, z1.d, z2.d[0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Negative tests for instructions that are incompatible with movprfx
|
||||
|
||||
movprfx z29.s, p0/z, z7.s
|
||||
fmlslt z29.s, z30.h, z31.h
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
|
||||
// CHECK-NEXT: fmlslt z29.s, z30.h, z31.h
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
||||
movprfx z0.s, p0/z, z7.s
|
||||
fmlslt z0.s, z1.h, z7.h[0]
|
||||
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
|
||||
// CHECK-NEXT: fmlslt z0.s, z1.h, z7.h[0]
|
||||
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2 < %s \
|
||||
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
|
||||
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
|
||||
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
|
||||
// RUN: | llvm-objdump -d -mattr=+sve2 - | FileCheck %s --check-prefix=CHECK-INST
|
||||
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2 < %s \
|
||||
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
|
||||
|
||||
|
||||
fmlslt z29.s, z30.h, z31.h
|
||||
// CHECK-INST: fmlslt z29.s, z30.h, z31.h
|
||||
// CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve2
|
||||
// CHECK-UNKNOWN: dd a7 bf 64 <unknown>
|
||||
|
||||
fmlslt z0.s, z1.h, z7.h[0]
|
||||
// CHECK-INST: fmlslt z0.s, z1.h, z7.h[0]
|
||||
// CHECK-ENCODING: [0x20,0x64,0xa7,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve2
|
||||
// CHECK-UNKNOWN: 20 64 a7 64 <unknown>
|
||||
|
||||
fmlslt z30.s, z31.h, z7.h[7]
|
||||
// CHECK-INST: fmlslt z30.s, z31.h, z7.h[7]
|
||||
// CHECK-ENCODING: [0xfe,0x6f,0xbf,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve2
|
||||
// CHECK-UNKNOWN: fe 6f bf 64 <unknown>
|
||||
|
||||
// --------------------------------------------------------------------------//
|
||||
// Test compatibility with MOVPRFX instruction.
|
||||
|
||||
movprfx z29, z28
|
||||
// CHECK-INST: movprfx z29, z28
|
||||
// CHECK-ENCODING: [0x9d,0xbf,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 9d bf 20 04 <unknown>
|
||||
|
||||
fmlslt z29.s, z30.h, z31.h
|
||||
// CHECK-INST: fmlslt z29.s, z30.h, z31.h
|
||||
// CHECK-ENCODING: [0xdd,0xa7,0xbf,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve2
|
||||
// CHECK-UNKNOWN: dd a7 bf 64 <unknown>
|
||||
|
||||
movprfx z21, z28
|
||||
// CHECK-INST: movprfx z21, z28
|
||||
// CHECK-ENCODING: [0x95,0xbf,0x20,0x04]
|
||||
// CHECK-ERROR: instruction requires: sve
|
||||
// CHECK-UNKNOWN: 95 bf 20 04 <unknown>
|
||||
|
||||
fmlslt z21.s, z1.h, z7.h[7]
|
||||
// CHECK-INST: fmlslt z21.s, z1.h, z7.h[7]
|
||||
// CHECK-ENCODING: [0x35,0x6c,0xbf,0x64]
|
||||
// CHECK-ERROR: instruction requires: sve2
|
||||
// CHECK-UNKNOWN: 35 6c bf 64 <unknown>
|
||||
Loading…
Reference in New Issue