forked from OSchip/llvm-project
[GlobalISel] Translate shufflevector
Reviewers: qcolombet, aditya_nandakumar, t.p.northover, javed.absar, ab, dsanders Reviewed By: javed.absar Subscribers: dberris, rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D30962 llvm-svn: 298347
This commit is contained in:
Volkan Keles
parent
9353e2dbfb
commit
75bdc7690e
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@ -299,6 +299,8 @@ private:
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bool translateExtractElement(const User &U, MachineIRBuilder &MIRBuilder);
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bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder);
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// Stubs to keep the compiler happy while we implement the rest of the
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// translation.
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bool translateResume(const User &U, MachineIRBuilder &MIRBuilder) {
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@ -337,9 +339,6 @@ private:
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bool translateUserOp2(const User &U, MachineIRBuilder &MIRBuilder) {
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return false;
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}
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bool translateShuffleVector(const User &U, MachineIRBuilder &MIRBuilder) {
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return false;
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}
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/// @}
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@ -537,4 +537,11 @@ def G_EXTRACT_VECTOR_ELT : Instruction {
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let hasSideEffects = 0;
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}
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// Generic shufflevector.
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def G_SHUFFLE_VECTOR: Instruction {
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let OutOperandList = (outs type0:$dst);
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let InOperandList = (ins type1:$v1, type1:$v2, type2:$mask);
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let hasSideEffects = 0;
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}
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// TODO: Add the other generic opcodes.
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@ -401,12 +401,15 @@ HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT)
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/// Generic extractelement.
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HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT)
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/// Generic shufflevector.
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HANDLE_TARGET_OPCODE(G_SHUFFLE_VECTOR)
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// TODO: Add more generic opcodes as we move along.
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/// Marker for the end of the generic opcode.
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/// This is used to check if an opcode is in the range of the
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/// generic opcodes.
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HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_EXTRACT_VECTOR_ELT)
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HANDLE_TARGET_OPCODE_MARKER(PRE_ISEL_GENERIC_OPCODE_END, G_SHUFFLE_VECTOR)
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/// BUILTIN_OP_END - This must be the last enum value in this list.
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/// The target-specific post-isel opcode values start here.
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@ -1005,6 +1005,16 @@ bool IRTranslator::translateExtractElement(const User &U,
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return true;
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}
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bool IRTranslator::translateShuffleVector(const User &U,
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MachineIRBuilder &MIRBuilder) {
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MIRBuilder.buildInstr(TargetOpcode::G_SHUFFLE_VECTOR)
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.addDef(getOrCreateVReg(U))
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.addUse(getOrCreateVReg(*U.getOperand(0)))
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.addUse(getOrCreateVReg(*U.getOperand(1)))
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.addUse(getOrCreateVReg(*U.getOperand(2)));
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return true;
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}
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bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
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const PHINode &PI = cast<PHINode>(U);
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auto MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
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@ -1411,3 +1411,111 @@ define float @test_different_call_conv_target(float %x) {
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%res = call ghccc float @different_call_conv_target(float %x)
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ret float %res
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}
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define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) {
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; CHECK-LABEL: name: test_shufflevector_s32_v2s32
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; CHECK: [[ARG:%[0-9]+]](s32) = COPY %w0
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; CHECK: [[UNDEF:%[0-9]+]](s32) = IMPLICIT_DEF
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; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
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; CHECK: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
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; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
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; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
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%vec = insertelement <1 x i32> undef, i32 %arg, i32 0
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%res = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer
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ret <2 x i32> %res
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}
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define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) {
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; CHECK-LABEL: name: test_shufflevector_v2s32_s32
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; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
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; CHECK: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
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; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
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; CHECK: [[RES:%[0-9]+]](s32) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[C1]](s32)
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; CHECK: %w0 = COPY [[RES]](s32)
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%vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <1 x i32> <i32 1>
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%res = extractelement <1 x i32> %vec, i32 0
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ret i32 %res
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}
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define <2 x i32> @test_shufflevector_v2s32_v2s32(<2 x i32> %arg) {
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; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32
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; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
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; CHECK: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
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; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
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; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
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; CHECK: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32)
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; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
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; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
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%res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
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ret <2 x i32> %res
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}
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define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) {
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; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
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; CHECK: [[ARG:%[0-9]+]](<2 x s32>) = COPY %d0
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; CHECK: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
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; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
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; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
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; CHECK: [[MASK:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
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; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>)
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; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
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%vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>
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%res = extractelement <3 x i32> %vec, i32 0
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ret i32 %res
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}
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define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg2) {
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; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
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; CHECK: [[ARG1:%[0-9]+]](<2 x s32>) = COPY %d0
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; CHECK: [[ARG2:%[0-9]+]](<2 x s32>) = COPY %d1
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; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
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; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
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; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
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; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
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; CHECK: [[MASK:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32)
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; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], [[MASK]](<4 x s32>)
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; CHECK: %q0 = COPY [[VEC]](<4 x s32>)
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%res = shufflevector <2 x i32> %arg1, <2 x i32> %arg2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i32> %res
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}
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define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) {
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; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
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; CHECK: [[ARG:%[0-9]+]](<4 x s32>) = COPY %q0
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; CHECK: [[UNDEF:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
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; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
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; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
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; CHECK: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
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; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
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; CHECK: %d0 = COPY [[VEC]](<2 x s32>)
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%res = shufflevector <4 x i32> %arg, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
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ret <2 x i32> %res
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}
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define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2) {
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; CHECK-LABEL: name: test_shufflevector_v8s8_v16s8
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; CHECK: [[ARG1:%[0-9]+]](<8 x s8>) = COPY %d0
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; CHECK: [[ARG2:%[0-9]+]](<8 x s8>) = COPY %d1
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; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
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; CHECK: [[C8:%[0-9]+]](s32) = G_CONSTANT i32 8
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; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
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; CHECK: [[C9:%[0-9]+]](s32) = G_CONSTANT i32 9
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; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
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; CHECK: [[C10:%[0-9]+]](s32) = G_CONSTANT i32 10
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; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
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; CHECK: [[C11:%[0-9]+]](s32) = G_CONSTANT i32 11
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; CHECK: [[C4:%[0-9]+]](s32) = G_CONSTANT i32 4
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; CHECK: [[C12:%[0-9]+]](s32) = G_CONSTANT i32 12
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; CHECK: [[C5:%[0-9]+]](s32) = G_CONSTANT i32 5
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; CHECK: [[C13:%[0-9]+]](s32) = G_CONSTANT i32 13
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; CHECK: [[C6:%[0-9]+]](s32) = G_CONSTANT i32 6
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; CHECK: [[C14:%[0-9]+]](s32) = G_CONSTANT i32 14
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; CHECK: [[C7:%[0-9]+]](s32) = G_CONSTANT i32 7
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; CHECK: [[C15:%[0-9]+]](s32) = G_CONSTANT i32 15
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; CHECK: [[MASK:%[0-9]+]](<16 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C8]](s32), [[C1]](s32), [[C9]](s32), [[C2]](s32), [[C10]](s32), [[C3]](s32), [[C11]](s32), [[C4]](s32), [[C12]](s32), [[C5]](s32), [[C13]](s32), [[C6]](s32), [[C14]](s32), [[C7]](s32), [[C15]](s32)
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; CHECK: [[VEC:%[0-9]+]](<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], [[MASK]](<16 x s32>)
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; CHECK: %q0 = COPY [[VEC]](<16 x s8>)
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%res = shufflevector <8 x i8> %arg1, <8 x i8> %arg2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15>
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ret <16 x i8> %res
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}
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@ -543,3 +543,83 @@ entry:
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%r = notail call arm_aapcscc float @different_call_conv_target(float %x)
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ret float %r
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}
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define i32 @test_shufflevector_s32_v2s32(i32 %arg) {
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; CHECK-LABEL: name: test_shufflevector_s32_v2s32
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; CHECK: [[ARG:%[0-9]+]](s32) = COPY %r0
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; CHECK: [[UNDEF:%[0-9]+]](s32) = IMPLICIT_DEF
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; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
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; CHECK: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32)
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; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>)
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; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>)
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%vec = insertelement <1 x i32> undef, i32 %arg, i32 0
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%shuffle = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer
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%res = extractelement <2 x i32> %shuffle, i32 0
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ret i32 %res
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}
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define i32 @test_shufflevector_v2s32_v3s32(i32 %arg1, i32 %arg2) {
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; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %r0
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; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %r1
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; CHECK: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
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; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
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; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
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; CHECK: [[MASK:%[0-9]+]](<3 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C0]](s32), [[C1]](s32)
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; CHECK: [[V1:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
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; CHECK: [[V2:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
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; CHECK: [[VEC:%[0-9]+]](<3 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>)
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; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>)
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%v1 = insertelement <2 x i32> undef, i32 %arg1, i32 0
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%v2 = insertelement <2 x i32> %v1, i32 %arg2, i32 1
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%shuffle = shufflevector <2 x i32> %v2, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1>
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%res = extractelement <3 x i32> %shuffle, i32 0
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ret i32 %res
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}
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define i32 @test_shufflevector_v2s32_v4s32(i32 %arg1, i32 %arg2) {
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; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %r0
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; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %r1
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; CHECK: [[UNDEF:%[0-9]+]](<2 x s32>) = IMPLICIT_DEF
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; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
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; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
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; CHECK: [[MASK:%[0-9]+]](<4 x s32>) = G_MERGE_VALUES [[C0]](s32), [[C0]](s32), [[C0]](s32), [[C0]](s32)
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; CHECK: [[V1:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
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; CHECK: [[V2:%[0-9]+]](<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
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; CHECK: [[VEC:%[0-9]+]](<4 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], [[MASK]](<4 x s32>)
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; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<4 x s32>)
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%v1 = insertelement <2 x i32> undef, i32 %arg1, i32 0
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%v2 = insertelement <2 x i32> %v1, i32 %arg2, i32 1
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%shuffle = shufflevector <2 x i32> %v2, <2 x i32> undef, <4 x i32> zeroinitializer
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%res = extractelement <4 x i32> %shuffle, i32 0
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ret i32 %res
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}
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define i32 @test_shufflevector_v4s32_v2s32(i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4) {
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; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32
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; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %r0
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; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %r1
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; CHECK: [[ARG3:%[0-9]+]](s32) = COPY %r2
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; CHECK: [[ARG4:%[0-9]+]](s32) = COPY %r3
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; CHECK: [[UNDEF:%[0-9]+]](<4 x s32>) = IMPLICIT_DEF
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; CHECK: [[C0:%[0-9]+]](s32) = G_CONSTANT i32 0
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; CHECK: [[C1:%[0-9]+]](s32) = G_CONSTANT i32 1
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; CHECK: [[C2:%[0-9]+]](s32) = G_CONSTANT i32 2
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; CHECK: [[C3:%[0-9]+]](s32) = G_CONSTANT i32 3
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; CHECK: [[MASK:%[0-9]+]](<2 x s32>) = G_MERGE_VALUES [[C1]](s32), [[C3]](s32)
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; CHECK: [[V1:%[0-9]+]](<4 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32)
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; CHECK: [[V2:%[0-9]+]](<4 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32)
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; CHECK: [[V3:%[0-9]+]](<4 x s32>) = G_INSERT_VECTOR_ELT [[V2]], [[ARG3]](s32), [[C2]](s32)
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; CHECK: [[V4:%[0-9]+]](<4 x s32>) = G_INSERT_VECTOR_ELT [[V3]], [[ARG4]](s32), [[C3]](s32)
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; CHECK: [[VEC:%[0-9]+]](<2 x s32>) = G_SHUFFLE_VECTOR [[V4]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>)
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; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>)
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%v1 = insertelement <4 x i32> undef, i32 %arg1, i32 0
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%v2 = insertelement <4 x i32> %v1, i32 %arg2, i32 1
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%v3 = insertelement <4 x i32> %v2, i32 %arg3, i32 2
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%v4 = insertelement <4 x i32> %v3, i32 %arg4, i32 3
|
||||
%shuffle = shufflevector <4 x i32> %v4, <4 x i32> undef, <2 x i32> <i32 1, i32 3>
|
||||
%res = extractelement <2 x i32> %shuffle, i32 0
|
||||
ret i32 %res
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue