forked from OSchip/llvm-project
[X86] Replace repeated isa/cast<ConstantSDNode> calls with single single dyn_cast<>. NFCI.
Noticed while looking at D101944
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@ -3845,17 +3845,17 @@ bool X86DAGToDAGISel::tryShiftAmountMod(SDNode *N) {
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if (ShiftAmt->getOpcode() == ISD::ADD || ShiftAmt->getOpcode() == ISD::SUB) {
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SDValue Add0 = ShiftAmt->getOperand(0);
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SDValue Add1 = ShiftAmt->getOperand(1);
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auto *Add0C = dyn_cast<ConstantSDNode>(Add0);
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auto *Add1C = dyn_cast<ConstantSDNode>(Add1);
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// If we are shifting by X+/-N where N == 0 mod Size, then just shift by X
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// to avoid the ADD/SUB.
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if (isa<ConstantSDNode>(Add1) &&
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cast<ConstantSDNode>(Add1)->getZExtValue() % Size == 0) {
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if (Add1C && Add1C->getAPIntValue().urem(Size) == 0) {
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NewShiftAmt = Add0;
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// If we are shifting by N-X where N == 0 mod Size, then just shift by -X to
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// generate a NEG instead of a SUB of a constant.
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} else if (ShiftAmt->getOpcode() == ISD::SUB &&
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isa<ConstantSDNode>(Add0) &&
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cast<ConstantSDNode>(Add0)->getZExtValue() != 0 &&
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cast<ConstantSDNode>(Add0)->getZExtValue() % Size == 0) {
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// If we are shifting by N-X where N == 0 mod Size, then just shift by -X
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// to generate a NEG instead of a SUB of a constant.
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} else if (ShiftAmt->getOpcode() == ISD::SUB && Add0C &&
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Add0C->getAPIntValue() != 0 &&
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Add0C->getAPIntValue().urem(Size) == 0) {
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// Insert a negate op.
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// TODO: This isn't guaranteed to replace the sub if there is a logic cone
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// that uses it that's not a shift.
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