diff --git a/llvm/lib/CodeGen/InstrSched/SchedGraph.cpp b/llvm/lib/CodeGen/InstrSched/SchedGraph.cpp
index 03771fe01d17..e3b3cba5249d 100644
--- a/llvm/lib/CodeGen/InstrSched/SchedGraph.cpp
+++ b/llvm/lib/CodeGen/InstrSched/SchedGraph.cpp
@@ -21,6 +21,7 @@
 #include "llvm/Target/TargetMachine.h"
 #include "../../Target/SparcV9/MachineCodeForInstruction.h"
 #include "../../Target/SparcV9/SparcV9RegInfo.h"
+#include "../../Target/SparcV9/SparcV9InstrInfo.h"
 #include "Support/STLExtras.h"
 #include <iostream>
 
@@ -561,7 +562,7 @@ void SchedGraph::buildNodesForBB(const TargetMachine& target,
   unsigned i = 0;
   for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E;
        ++I, ++i)
-    if (!mii.isDummyPhiInstr(I->getOpcode())) {
+    if (I->getOpcode() != V9::PHI) {
       SchedGraphNode* node = new SchedGraphNode(getNumNodes(), &MBB, i, target);
       noteGraphNodeForInstr(I, node);
       
diff --git a/llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp b/llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp
index 8e11dd1da5c3..dadc38570c63 100644
--- a/llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp
+++ b/llvm/lib/CodeGen/ModuloScheduling/ModuloScheduling.cpp
@@ -1444,8 +1444,7 @@ void ModuloSchedulingPass::removePHIs(const MachineBasicBlock *origBB, std::vect
   //Start with the kernel and for each phi insert a copy for the phi def and for each arg
   for(MachineBasicBlock::iterator I = kernelBB->begin(), E = kernelBB->end(); I != E; ++I) {
     //Get op code and check if its a phi
-     MachineOpCode OC = I->getOpcode();
-     if(TMI->isDummyPhiInstr(OC)) {
+     if(I->getOpcode() == V9::PHI) {
        Instruction *tmp = 0;
        for(unsigned i = 0; i < I->getNumOperands(); ++i) {
 	 //Get Operand
@@ -1491,8 +1490,7 @@ void ModuloSchedulingPass::removePHIs(const MachineBasicBlock *origBB, std::vect
   for(std::vector<MachineBasicBlock*>::iterator MB = epilogues.begin(), ME = epilogues.end(); MB != ME; ++MB) {
     for(MachineBasicBlock::iterator I = (*MB)->begin(), E = (*MB)->end(); I != E; ++I) {
       //Get op code and check if its a phi
-      MachineOpCode OC = I->getOpcode();
-      if(TMI->isDummyPhiInstr(OC)) {
+      if(I->getOpcode() == V9::PHI) {
 	Instruction *tmp = 0;
 	for(unsigned i = 0; i < I->getNumOperands(); ++i) {
 	  //Get Operand
diff --git a/llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 2fd8e558fdc7..02f18fc7389f 100644
--- a/llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -484,7 +484,7 @@ void PhyRegAlloc::updateMachineCode()
     // their assigned registers or insert spill code, as appropriate. 
     // Also, fix operands of call/return instructions.
     for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
-      if (! TM.getInstrInfo()->isDummyPhiInstr(MII->getOpcode()))
+      if (MII->getOpcode() != V9::PHI)
         updateInstruction(MII, MBB);
 
     // Now, move code out of delay slots of branches and returns if needed.
@@ -552,7 +552,7 @@ void PhyRegAlloc::updateMachineCode()
       MachineInstr *MInst = MII; 
 
       // do not process Phis
-      if (TM.getInstrInfo()->isDummyPhiInstr(MInst->getOpcode()))
+      if (MInst->getOpcode() == V9::PHI)
 	continue;
 
       // if there are any added instructions...
diff --git a/llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
index 58f589d485d9..36deae09d82b 100644
--- a/llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
+++ b/llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
@@ -283,8 +283,8 @@ SparcV9AsmPrinter::printOneOperand(const MachineOperand &mop,
 void SparcV9AsmPrinter::emitMachineInst(const MachineInstr *MI) {
   unsigned Opcode = MI->getOpcode();
 
-  if (TM.getInstrInfo()->isDummyPhiInstr(Opcode))
-    return;  // IGNORE PHI NODES
+  if (Opcode == V9::PHI)
+    return;  // Ignore Machine-PHI nodes.
 
   O << "\t" << TM.getInstrInfo()->getName(Opcode) << "\t";