forked from OSchip/llvm-project
[RISCV] Add double test cases to vfmerge-rv32.ll. NFC
This commit is contained in:
Craig Topper
parent
9e7895a868
commit
7583ae48a3
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@ -1,4 +1,4 @@
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+f,+experimental-zfh -verify-machineinstrs \
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; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
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; RUN: --riscv-no-aliases < %s | FileCheck %s
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declare <vscale x 1 x half> @llvm.riscv.vfmerge.nxv1f16.nxv1f16(
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<vscale x 1 x half>,
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@ -440,6 +440,166 @@ entry:
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ret <vscale x 16 x float> %a
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}
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declare <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.nxv1f64(
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<vscale x 1 x double>,
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<vscale x 1 x double>,
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<vscale x 1 x i1>,
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i32);
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define <vscale x 1 x double> @intrinsic_vfmerge_vvm_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv1f64_nxv1f64_nxv1f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1
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; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
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%a = call <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.nxv1f64(
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<vscale x 1 x double> %0,
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<vscale x 1 x double> %1,
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<vscale x 1 x i1> %2,
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i32 %3)
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ret <vscale x 1 x double> %a
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}
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declare <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.f64(
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<vscale x 1 x double>,
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double,
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<vscale x 1 x i1>,
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i32);
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define <vscale x 1 x double> @intrinsic_vfmerge_vfm_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv1f64_nxv1f64_f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1
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; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
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%a = call <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.f64(
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<vscale x 1 x double> %0,
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double %1,
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<vscale x 1 x i1> %2,
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i32 %3)
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ret <vscale x 1 x double> %a
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}
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declare <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.nxv2f64(
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<vscale x 2 x double>,
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<vscale x 2 x double>,
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<vscale x 2 x i1>,
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i32);
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define <vscale x 2 x double> @intrinsic_vfmerge_vvm_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv2f64_nxv2f64_nxv2f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2
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; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
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%a = call <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.nxv2f64(
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<vscale x 2 x double> %0,
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<vscale x 2 x double> %1,
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<vscale x 2 x i1> %2,
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i32 %3)
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ret <vscale x 2 x double> %a
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}
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declare <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.f64(
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<vscale x 2 x double>,
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double,
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<vscale x 2 x i1>,
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i32);
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define <vscale x 2 x double> @intrinsic_vfmerge_vfm_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv2f64_nxv2f64_f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2
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; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
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%a = call <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.f64(
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<vscale x 2 x double> %0,
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double %1,
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<vscale x 2 x i1> %2,
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i32 %3)
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ret <vscale x 2 x double> %a
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}
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declare <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.nxv4f64(
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<vscale x 4 x double>,
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<vscale x 4 x double>,
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<vscale x 4 x i1>,
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i32);
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define <vscale x 4 x double> @intrinsic_vfmerge_vvm_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv4f64_nxv4f64_nxv4f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4
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; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
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%a = call <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.nxv4f64(
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<vscale x 4 x double> %0,
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<vscale x 4 x double> %1,
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<vscale x 4 x i1> %2,
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i32 %3)
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ret <vscale x 4 x double> %a
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}
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declare <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.f64(
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<vscale x 4 x double>,
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double,
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<vscale x 4 x i1>,
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i32);
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define <vscale x 4 x double> @intrinsic_vfmerge_vfm_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv4f64_nxv4f64_f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4
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; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
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%a = call <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.f64(
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<vscale x 4 x double> %0,
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double %1,
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<vscale x 4 x i1> %2,
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i32 %3)
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ret <vscale x 4 x double> %a
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}
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declare <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.nxv8f64(
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<vscale x 8 x double>,
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<vscale x 8 x double>,
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<vscale x 8 x i1>,
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i32);
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define <vscale x 8 x double> @intrinsic_vfmerge_vvm_nxv8f64_nxv8f64_nxv8f64(<vscale x 8 x double> %0, <vscale x 8 x double> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfmerge_vvm_nxv8f64_nxv8f64_nxv8f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8
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; CHECK: vmerge.vvm {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, v0
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%a = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.nxv8f64(
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<vscale x 8 x double> %0,
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<vscale x 8 x double> %1,
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<vscale x 8 x i1> %2,
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i32 %3)
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ret <vscale x 8 x double> %a
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}
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declare <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64(
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<vscale x 8 x double>,
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double,
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<vscale x 8 x i1>,
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i32);
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define <vscale x 8 x double> @intrinsic_vfmerge_vfm_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, double %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfmerge_vfm_nxv8f64_nxv8f64_f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8
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; CHECK: vfmerge.vfm {{v[0-9]+}}, {{v[0-9]+}}, {{ft[0-9]+}}, v0
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%a = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64(
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<vscale x 8 x double> %0,
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double %1,
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<vscale x 8 x i1> %2,
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i32 %3)
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ret <vscale x 8 x double> %a
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}
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define <vscale x 1 x half> @intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16(<vscale x 1 x half> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f16_nxv1f16_f16
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@ -593,3 +753,59 @@ entry:
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ret <vscale x 16 x float> %a
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}
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define <vscale x 1 x double> @intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64(<vscale x 1 x double> %0, <vscale x 1 x i1> %1, i32 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv1f64_nxv1f64_f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m1,ta,mu
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; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
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%a = call <vscale x 1 x double> @llvm.riscv.vfmerge.nxv1f64.f64(
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<vscale x 1 x double> %0,
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double zeroinitializer,
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<vscale x 1 x i1> %1,
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i32 %2)
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ret <vscale x 1 x double> %a
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}
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define <vscale x 2 x double> @intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64(<vscale x 2 x double> %0, <vscale x 2 x i1> %1, i32 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv2f64_nxv2f64_f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m2,ta,mu
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; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
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%a = call <vscale x 2 x double> @llvm.riscv.vfmerge.nxv2f64.f64(
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<vscale x 2 x double> %0,
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double zeroinitializer,
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<vscale x 2 x i1> %1,
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i32 %2)
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ret <vscale x 2 x double> %a
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}
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define <vscale x 4 x double> @intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64(<vscale x 4 x double> %0, <vscale x 4 x i1> %1, i32 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv4f64_nxv4f64_f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m4,ta,mu
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; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
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%a = call <vscale x 4 x double> @llvm.riscv.vfmerge.nxv4f64.f64(
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<vscale x 4 x double> %0,
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double zeroinitializer,
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<vscale x 4 x i1> %1,
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i32 %2)
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ret <vscale x 4 x double> %a
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}
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define <vscale x 8 x double> @intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64(<vscale x 8 x double> %0, <vscale x 8 x i1> %1, i32 %2) nounwind {
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entry:
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; CHECK-LABEL: intrinsic_vfmerge_vzm_nxv8f64_nxv8f64_f64
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; CHECK: vsetvli {{.*}}, {{a[0-9]+}}, e64,m8,ta,mu
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; CHECK: vmerge.vim {{v[0-9]+}}, {{v[0-9]+}}, 0, v0
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%a = call <vscale x 8 x double> @llvm.riscv.vfmerge.nxv8f64.f64(
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<vscale x 8 x double> %0,
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double zeroinitializer,
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<vscale x 8 x i1> %1,
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i32 %2)
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ret <vscale x 8 x double> %a
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}
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