forked from OSchip/llvm-project
[PowerPC][Future] Initial support for PCRel addressing for constant pool loads
Add initial support for PC Relative addressing for constant pool loads. This includes adding a new relocation for @pcrel and adding a new PowerPC flag to identify PC relative addressing. Differential Revision: https://reviews.llvm.org/D74486
This commit is contained in:
Stefan Pintilie
Kamau Bridgeman
parent
015dee1ac8
commit
75828ef615
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@ -97,6 +97,7 @@
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#undef R_PPC64_DTPREL16_HIGH
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#undef R_PPC64_DTPREL16_HIGHA
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#undef R_PPC64_REL24_NOTOC
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#undef R_PPC64_PCREL34
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#undef R_PPC64_IRELATIVE
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#undef R_PPC64_REL16
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#undef R_PPC64_REL16_LO
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@ -192,6 +193,7 @@ ELF_RELOC(R_PPC64_TPREL16_HIGHA, 113)
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ELF_RELOC(R_PPC64_DTPREL16_HIGH, 114)
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ELF_RELOC(R_PPC64_DTPREL16_HIGHA, 115)
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ELF_RELOC(R_PPC64_REL24_NOTOC, 116)
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ELF_RELOC(R_PPC64_PCREL34, 132)
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ELF_RELOC(R_PPC64_IRELATIVE, 248)
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ELF_RELOC(R_PPC64_REL16, 249)
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ELF_RELOC(R_PPC64_REL16_LO, 250)
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@ -45,6 +45,8 @@ static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
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return Value & 0xffff;
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case PPC::fixup_ppc_half16ds:
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return Value & 0xfffc;
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case PPC::fixup_ppc_pcrel34:
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return Value & 0x3ffffffff;
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}
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}
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@ -65,6 +67,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
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case PPC::fixup_ppc_br24abs:
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case PPC::fixup_ppc_br24_notoc:
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return 4;
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case PPC::fixup_ppc_pcrel34:
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case FK_Data_8:
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return 8;
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case PPC::fixup_ppc_nofixup:
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@ -96,6 +99,7 @@ public:
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{ "fixup_ppc_brcond14abs", 16, 14, 0 },
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{ "fixup_ppc_half16", 0, 16, 0 },
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{ "fixup_ppc_half16ds", 0, 14, 0 },
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{ "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_nofixup", 0, 0, 0 }
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};
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const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = {
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@ -107,6 +111,7 @@ public:
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{ "fixup_ppc_brcond14abs", 2, 14, 0 },
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{ "fixup_ppc_half16", 0, 16, 0 },
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{ "fixup_ppc_half16ds", 2, 14, 0 },
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{ "fixup_ppc_pcrel34", 0, 34, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_ppc_nofixup", 0, 0, 0 }
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};
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@ -128,6 +128,9 @@ unsigned PPCELFObjectWriter::getRelocType(MCContext &Ctx, const MCValue &Target,
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Target.print(errs());
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errs() << '\n';
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report_fatal_error("Invalid PC-relative half16ds relocation");
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case PPC::fixup_ppc_pcrel34:
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Type = ELF::R_PPC64_PCREL34;
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break;
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case FK_Data_4:
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case FK_PCRel_4:
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Type = ELF::R_PPC_REL32;
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@ -40,6 +40,9 @@ enum Fixups {
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/// instrs like 'std'.
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fixup_ppc_half16ds,
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// A 34-bit fixup corresponding to PC-relative paddi.
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fixup_ppc_pcrel34,
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/// Not a true fixup, but ties a symbol to a call to __tls_get_addr for the
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/// TLS general and local dynamic models, or inserts the thread-pointer
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/// register number.
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@ -400,10 +400,14 @@ void PPCInstPrinter::printS16ImmOperand(const MCInst *MI, unsigned OpNo,
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void PPCInstPrinter::printS34ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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if (MI->getOperand(OpNo).isImm()) {
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long long Value = MI->getOperand(OpNo).getImm();
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assert(isInt<34>(Value) && "Invalid s34imm argument!");
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O << (long long)Value;
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}
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else
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printOperand(MI, OpNo, O);
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}
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void PPCInstPrinter::printU16ImmOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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@ -104,6 +104,20 @@ unsigned PPCMCCodeEmitter::getImm16Encoding(const MCInst &MI, unsigned OpNo,
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return 0;
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}
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unsigned long
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PPCMCCodeEmitter::getImm34Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm())
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return getMachineOpValue(MI, MO, Fixups, STI);
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// Add a fixup for the immediate field.
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Fixups.push_back(MCFixup::create(IsLittleEndian? 0 : 1, MO.getExpr(),
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(MCFixupKind)PPC::fixup_ppc_pcrel34));
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return 0;
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}
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unsigned PPCMCCodeEmitter::getMemRIEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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@ -175,6 +189,16 @@ PPCMCCodeEmitter::getMemRI34PCRelEncoding(const MCInst &MI, unsigned OpNo,
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report_fatal_error("Operand must be 0");
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isExpr()) {
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const MCExpr *Expr = MO.getExpr();
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const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(Expr);
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assert(SRE->getKind() == MCSymbolRefExpr::VK_PCREL &&
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"VariantKind must be VK_PCREL");
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Fixups.push_back(
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MCFixup::create(IsLittleEndian ? 0 : 1, Expr,
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static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
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return 0;
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}
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return ((getMachineOpValue(MI, MO, Fixups, STI)) & 0x3FFFFFFFFUL) | RegBits;
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}
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@ -50,6 +50,9 @@ public:
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unsigned getImm16Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned long getImm34Encoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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@ -98,24 +98,28 @@ namespace llvm {
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/// the function's picbase, e.g. lo16(symbol-picbase).
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MO_PIC_FLAG = 2,
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/// MO_PCREL_FLAG - If this bit is set, the symbol reference is relative to
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/// the current instruction address(pc), e.g., var@pcrel. Fixup is VK_PCREL.
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MO_PCREL_FLAG = 4,
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/// The next are not flags but distinct values.
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MO_ACCESS_MASK = 0xf0,
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MO_ACCESS_MASK = 0xf00,
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/// MO_LO, MO_HA - lo16(symbol) and ha16(symbol)
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MO_LO = 1 << 4,
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MO_HA = 2 << 4,
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MO_LO = 1 << 8,
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MO_HA = 2 << 8,
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MO_TPREL_LO = 4 << 4,
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MO_TPREL_HA = 3 << 4,
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MO_TPREL_LO = 4 << 8,
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MO_TPREL_HA = 3 << 8,
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/// These values identify relocations on immediates folded
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/// into memory operations.
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MO_DTPREL_LO = 5 << 4,
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MO_TLSLD_LO = 6 << 4,
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MO_TOC_LO = 7 << 4,
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MO_DTPREL_LO = 5 << 8,
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MO_TLSLD_LO = 6 << 8,
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MO_TOC_LO = 7 << 8,
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// Symbol for VK_PPC_TLS fixup attached to an ADD instruction
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MO_TLS = 8 << 4
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MO_TLS = 8 << 8
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};
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} // end namespace PPCII
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@ -296,6 +296,10 @@ namespace {
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return true;
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}
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bool SelectAddrPCRel(SDValue N, SDValue &Base) {
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return PPCLowering->SelectAddressPCRel(N, Base);
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}
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/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
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/// inline asm expressions. It is always correct to compute the value into
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/// a register. The case of adding a (possibly relocatable) constant to a
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@ -1480,6 +1480,7 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
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case PPCISD::EXTSWSLI: return "PPCISD::EXTSWSLI";
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case PPCISD::LD_VSX_LH: return "PPCISD::LD_VSX_LH";
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case PPCISD::FP_EXTEND_HALF: return "PPCISD::FP_EXTEND_HALF";
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case PPCISD::MAT_PCREL_ADDR: return "PPCISD::MAT_PCREL_ADDR";
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case PPCISD::LD_SPLAT: return "PPCISD::LD_SPLAT";
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}
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return nullptr;
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@ -2346,6 +2347,11 @@ bool PPCTargetLowering::SelectAddressEVXRegReg(SDValue N, SDValue &Base,
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bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
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SDValue &Index, SelectionDAG &DAG,
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unsigned EncodingAlignment) const {
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// If we have a PC Relative target flag don't select as [reg+reg]. It will be
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// a [pc+imm].
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if (SelectAddressPCRel(N, Base))
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return false;
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int16_t imm = 0;
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if (N.getOpcode() == ISD::ADD) {
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// Is there any SPE load/store (f64), which can't handle 16bit offset?
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@ -2435,6 +2441,12 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
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unsigned EncodingAlignment) const {
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// FIXME dl should come from parent load or store, not from address
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SDLoc dl(N);
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// If we have a PC Relative target flag don't select as [reg+imm]. It will be
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// a [pc+imm].
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if (SelectAddressPCRel(N, Base))
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return false;
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// If this can be more profitably realized as r+r, fail.
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if (SelectAddressRegReg(N, Disp, Base, DAG, EncodingAlignment))
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return false;
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@ -2558,6 +2570,21 @@ bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
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return true;
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}
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/// Returns true if this address is a PC Relative address.
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/// PC Relative addresses are marked with the flag PPCII::MO_PCREL_FLAG.
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bool PPCTargetLowering::SelectAddressPCRel(SDValue N, SDValue &Base) const {
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ConstantPoolSDNode *ConstPoolNode =
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dyn_cast<ConstantPoolSDNode>(N.getNode());
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bool HasFlag = ConstPoolNode &&
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ConstPoolNode->getTargetFlags() == PPCII::MO_PCREL_FLAG;
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bool HasNode = N.getOpcode() == PPCISD::MAT_PCREL_ADDR;
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if (HasFlag || HasNode) {
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Base = N;
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return true;
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}
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return false;
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}
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/// Returns true if we should use a direct load into vector instruction
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/// (such as lxsd or lfd), instead of a load into gpr + direct move sequence.
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static bool usePartialVectorLoads(SDNode *N, const PPCSubtarget& ST) {
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@ -2763,6 +2790,15 @@ SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
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// 64-bit SVR4 ABI and AIX ABI code are always position-independent.
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// The actual address of the GlobalValue is stored in the TOC.
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if (Subtarget.is64BitELFABI() || Subtarget.isAIXABI()) {
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if (Subtarget.hasPCRelativeMemops()) {
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SDLoc DL(CP);
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EVT Ty = getPointerTy(DAG.getDataLayout());
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SDValue ConstPool = DAG.getTargetConstantPool(C, Ty,
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CP->getAlignment(),
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CP->getOffset(),
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PPCII::MO_PCREL_FLAG);
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return DAG.getNode(PPCISD::MAT_PCREL_ADDR, DL, Ty, ConstPool);
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}
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setUsesTOCBasePtr(DAG);
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SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
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return getTOCEntry(DAG, SDLoc(CP), GA);
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@ -428,6 +428,11 @@ namespace llvm {
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/// lower (IDX=1) half of v4f32 to v2f64.
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FP_EXTEND_HALF,
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/// MAT_PCREL_ADDR = Materialize a PC Relative address. This can be done
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/// either through an add like PADDI or through a PC Relative load like
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/// PLD.
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MAT_PCREL_ADDR,
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/// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
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/// byte-swapping store instruction. It byte-swaps the low "Type" bits of
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/// the GPRC input, then stores it through Ptr. Type can be either i16 or
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@ -730,6 +735,10 @@ namespace llvm {
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bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
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SelectionDAG &DAG) const;
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/// SelectAddressPCRel - Represent the specified address as pc relative to
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/// be represented as [pc+imm]
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bool SelectAddressPCRel(SDValue N, SDValue &Base) const;
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Sched::Preference getSchedulingPreference(SDNode *N) const override;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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@ -2046,7 +2046,9 @@ ArrayRef<std::pair<unsigned, const char *>>
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PPCInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
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using namespace PPCII;
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static const std::pair<unsigned, const char *> TargetFlags[] = {
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{MO_PLT, "ppc-plt"}, {MO_PIC_FLAG, "ppc-pic"}};
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{MO_PLT, "ppc-plt"},
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{MO_PIC_FLAG, "ppc-pic"},
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{MO_PCREL_FLAG, "ppc-pcrel"}};
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return makeArrayRef(TargetFlags);
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}
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@ -319,6 +319,9 @@ def SDTDynAreaOp : SDTypeProfile<1, 1, []>;
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def PPCdynalloc : SDNode<"PPCISD::DYNALLOC", SDTDynOp, [SDNPHasChain]>;
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def PPCdynareaoffset : SDNode<"PPCISD::DYNAREAOFFSET", SDTDynAreaOp, [SDNPHasChain]>;
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// PC Relative Specific Nodes
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def PPCmatpcreladdr : SDNode<"PPCISD::MAT_PCREL_ADDR", SDTIntUnaryOp, []>;
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//===----------------------------------------------------------------------===//
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// PowerPC specific transformation functions and pattern fragments.
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//
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@ -730,6 +733,7 @@ def PPCS34ImmAsmOperand : AsmOperandClass {
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}
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def s34imm : Operand<i64> {
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let PrintMethod = "printS34ImmOperand";
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let EncoderMethod = "getImm34Encoding";
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let ParserMatchClass = PPCS34ImmAsmOperand;
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let DecoderMethod = "decodeSImmOperand<34>";
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}
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@ -977,6 +981,9 @@ def addr : ComplexPattern<iPTR, 1, "SelectAddr",[], []>;
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/// This is just the offset part of iaddr, used for preinc.
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def iaddroff : ComplexPattern<iPTR, 1, "SelectAddrImmOffs", [], []>;
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// PC Relative Address
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def pcreladdr : ComplexPattern<iPTR, 1, "SelectAddrPCRel", [], []>;
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Predicate Definitions.
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def In32BitMode : Predicate<"!PPCSubTarget->isPPC64()">;
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@ -337,3 +337,43 @@ let Predicates = [PrefixInstrs] in {
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}
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}
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// TODO: We have an added complexity of 500 here. This is only a temporary
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// solution to have tablegen consider these patterns first. The way we do
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// addressing for PowerPC is complex depending on available D form, X form, or
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// aligned D form loads/stores like DS and DQ forms. The prefixed
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// instructions in this file also add additional PC Relative loads/stores
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// and D form loads/stores with 34 bit immediates. It is very difficult to force
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// instruction selection to consistently pick these first without the current
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// added complexity. Once pc-relative implementation is complete, a set of
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// follow-up patches will address this refactoring and the AddedComplexity will
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// be removed.
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let Predicates = [PCRelativeMemops], AddedComplexity = 500 in {
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// Load f32
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def : Pat<(f32 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLFSpc $addr, 0)>;
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// Load f64
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def : Pat<(f64 (extloadf32 (PPCmatpcreladdr pcreladdr:$addr))),
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(COPY_TO_REGCLASS (PLFSpc $addr, 0), VSFRC)>;
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def : Pat<(f64 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLFDpc $addr, 0)>;
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// Load f128
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def : Pat<(f128 (load (PPCmatpcreladdr pcreladdr:$addr))),
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(COPY_TO_REGCLASS (PLXVpc $addr, 0), VRRC)>;
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// Load v4i32
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def : Pat<(v4i32 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>;
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// Load v2i64
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def : Pat<(v2i64 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>;
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// Load v4f32
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def : Pat<(v4f32 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>;
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// Load v2f64
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def : Pat<(v2f64 (load (PPCmatpcreladdr pcreladdr:$addr))), (PLXVpc $addr, 0)>;
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// If the PPCmatpcreladdr node is not caught by any other pattern it should be
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// caught here and turned into a paddi instruction to materialize the address.
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def : Pat<(PPCmatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>;
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}
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@ -80,6 +80,8 @@ static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
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if (MO.getTargetFlags() == PPCII::MO_PLT)
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RefKind = MCSymbolRefExpr::VK_PLT;
|
||||
else if (MO.getTargetFlags() == PPCII::MO_PCREL_FLAG)
|
||||
RefKind = MCSymbolRefExpr::VK_PCREL;
|
||||
|
||||
const MachineInstr *MI = MO.getParent();
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,92 @@
|
|||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
|
||||
; RUN: -mcpu=future -enable-ppc-quad-precision -ppc-asm-full-reg-names \
|
||||
; RUN: < %s | FileCheck %s
|
||||
|
||||
define float @FloatConstantPool() {
|
||||
; CHECK-LABEL: FloatConstantPool:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: plfs f1, .LCPI0_0@PCREL(0), 1
|
||||
entry:
|
||||
ret float 0x380FFFF840000000
|
||||
}
|
||||
|
||||
define double @DoubleConstantPool() {
|
||||
; CHECK-LABEL: DoubleConstantPool:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: plfd f1, .LCPI1_0@PCREL(0), 1
|
||||
entry:
|
||||
ret double 2.225070e-308
|
||||
}
|
||||
|
||||
define ppc_fp128 @LongDoubleConstantPool() {
|
||||
; CHECK-LABEL: LongDoubleConstantPool:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: plfd f1, .LCPI2_0@PCREL(0), 1
|
||||
; CHECK-NEXT: plfd f2, .LCPI2_1@PCREL(0), 1
|
||||
entry:
|
||||
ret ppc_fp128 0xM03600000DBA876CC800D16974FD9D27B
|
||||
}
|
||||
|
||||
define fp128 @__Float128ConstantPool() {
|
||||
; CHECK-LABEL: __Float128ConstantPool:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: plxv vs34, .LCPI3_0@PCREL(0), 1
|
||||
entry:
|
||||
ret fp128 0xL00000000000000003C00FFFFC5D02B3A
|
||||
}
|
||||
|
||||
define <16 x i8> @VectorCharConstantPool() {
|
||||
; CHECK-LABEL: VectorCharConstantPool:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: plxv vs34, .LCPI4_0@PCREL(0), 1
|
||||
entry:
|
||||
ret <16 x i8> <i8 -128, i8 -127, i8 -126, i8 -125, i8 -124, i8 -123, i8 -122, i8 -121, i8 -120, i8 -119, i8 -118, i8 -117, i8 -116, i8 -115, i8 -114, i8 -113>
|
||||
}
|
||||
|
||||
define <8 x i16> @VectorShortConstantPool() {
|
||||
; CHECK-LABEL: VectorShortConstantPool:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: plxv vs34, .LCPI5_0@PCREL(0), 1
|
||||
entry:
|
||||
ret <8 x i16> <i16 -32768, i16 -32767, i16 -32766, i16 -32765, i16 -32764, i16 -32763, i16 -32762, i16 -32761>
|
||||
}
|
||||
|
||||
define <4 x i32> @VectorIntConstantPool() {
|
||||
; CHECK-LABEL: VectorIntConstantPool:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: plxv vs34, .LCPI6_0@PCREL(0), 1
|
||||
entry:
|
||||
ret <4 x i32> <i32 -2147483648, i32 -2147483647, i32 -2147483646, i32 -2147483645>
|
||||
}
|
||||
|
||||
define <2 x i64> @VectorLongLongConstantPool() {
|
||||
; CHECK-LABEL: VectorLongLongConstantPool:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: plxv vs34, .LCPI7_0@PCREL(0), 1
|
||||
entry:
|
||||
ret <2 x i64> <i64 -9223372036854775808, i64 -9223372036854775807>
|
||||
}
|
||||
|
||||
define <1 x i128> @VectorInt128ConstantPool() {
|
||||
; CHECK-LABEL: VectorInt128ConstantPool:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: plxv vs34, .LCPI8_0@PCREL(0), 1
|
||||
entry:
|
||||
ret <1 x i128> <i128 -27670116110564327424>
|
||||
}
|
||||
|
||||
define <4 x float> @VectorFloatConstantPool() {
|
||||
; CHECK-LABEL: VectorFloatConstantPool:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: plxv vs34, .LCPI9_0@PCREL(0), 1
|
||||
entry:
|
||||
ret <4 x float> <float 0x380FFFF840000000, float 0x380FFF57C0000000, float 0x3843FFFB20000000, float 0x3843FF96C0000000>
|
||||
}
|
||||
|
||||
define <2 x double> @VectorDoubleConstantPool() {
|
||||
; CHECK-LABEL: VectorDoubleConstantPool:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: plxv vs34, .LCPI10_0@PCREL(0), 1
|
||||
entry:
|
||||
ret <2 x double> <double 2.225070e-308, double 2.225000e-308>
|
||||
}
|
||||
|
|
@ -162,12 +162,9 @@ entry:
|
|||
|
||||
define dso_local double @UsesX2AsConstPoolTOC() local_unnamed_addr {
|
||||
; CHECK-S-LABEL: UsesX2AsConstPoolTOC:
|
||||
; CHECK-S: addis r2, r12, .TOC.-.Lfunc_gep7@ha
|
||||
; CHECK-S-NEXT: addi r2, r2, .TOC.-.Lfunc_gep7@l
|
||||
; CHECK-S: .localentry UsesX2AsConstPoolTOC, .Lfunc_lep7-.Lfunc_gep7
|
||||
; CHECK-S-NOT: .localentry
|
||||
; CHECK-S: # %bb.0: # %entry
|
||||
; CHECK-S-NEXT: addis r3, r2, .LCPI7_0@toc@ha
|
||||
; CHECK-S-NEXT: lfd f1, .LCPI7_0@toc@l(r3)
|
||||
; CHECK-S-NEXT: plfd f1, .LCPI7_0@PCREL(0), 1
|
||||
; CHECK-S-NEXT: blr
|
||||
entry:
|
||||
ret double 0x404124A4EBDD334C
|
||||
|
|
|
|||
|
|
@ -0,0 +1,23 @@
|
|||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
|
||||
; RUN: -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
|
||||
; RUN: FileCheck %s --check-prefix=CHECK-S
|
||||
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
|
||||
; RUN: -mcpu=future -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
|
||||
; RUN: --filetype=obj < %s | \
|
||||
; RUN: llvm-objdump --mcpu=future -dr - | FileCheck %s --check-prefix=CHECK-O
|
||||
|
||||
; Constant Pool Index.
|
||||
; CHECK-S-LABEL: ConstPool
|
||||
; CHECK-S: plfd f1, .LCPI0_0@PCREL(0), 1
|
||||
; CHECK-S: blr
|
||||
|
||||
; CHECK-O-LABEL: ConstPool
|
||||
; CHECK-O: plfd 1, 0(0), 1
|
||||
; CHECK-O-NEXT: R_PPC64_PCREL34 .rodata.cst8
|
||||
; CHECK-O: blr
|
||||
define dso_local double @ConstPool() local_unnamed_addr {
|
||||
entry:
|
||||
ret double 0x406ECAB439581062
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue