forked from OSchip/llvm-project
AMDGPU/GlobalISel: Legalize workgroup ID intrinsics
llvm-svn: 364834
This commit is contained in:
Matt Arsenault
parent
e2c86cce3a
commit
756d81905f
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@ -203,6 +203,33 @@ static void allocateSystemSGPRs(CCState &CCInfo,
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SIMachineFunctionInfo &Info,
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CallingConv::ID CallConv,
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bool IsShader) {
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const LLT S32 = LLT::scalar(32);
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MachineRegisterInfo &MRI = MF.getRegInfo();
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if (Info.hasWorkGroupIDX()) {
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Register Reg = Info.addWorkGroupIDX();
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MRI.setType(MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass), S32);
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CCInfo.AllocateReg(Reg);
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}
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if (Info.hasWorkGroupIDY()) {
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Register Reg = Info.addWorkGroupIDY();
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MRI.setType(MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass), S32);
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CCInfo.AllocateReg(Reg);
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}
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if (Info.hasWorkGroupIDZ()) {
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unsigned Reg = Info.addWorkGroupIDZ();
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MRI.setType(MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass), S32);
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CCInfo.AllocateReg(Reg);
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}
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if (Info.hasWorkGroupInfo()) {
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unsigned Reg = Info.addWorkGroupInfo();
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MRI.setType(MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass), S32);
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CCInfo.AllocateReg(Reg);
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}
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if (Info.hasPrivateSegmentWaveByteOffset()) {
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// Scratch wave offset passed in system SGPR.
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unsigned PrivateSegmentWaveByteOffsetReg;
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@ -1188,6 +1188,15 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(MachineInstr &MI,
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case Intrinsic::amdgcn_workitem_id_z:
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return legalizePreloadedArgIntrin(MI, MRI, B,
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AMDGPUFunctionArgInfo::WORKITEM_ID_Z);
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case Intrinsic::amdgcn_workgroup_id_x:
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return legalizePreloadedArgIntrin(MI, MRI, B,
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AMDGPUFunctionArgInfo::WORKGROUP_ID_X);
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case Intrinsic::amdgcn_workgroup_id_y:
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return legalizePreloadedArgIntrin(MI, MRI, B,
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AMDGPUFunctionArgInfo::WORKGROUP_ID_Y);
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case Intrinsic::amdgcn_workgroup_id_z:
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return legalizePreloadedArgIntrin(MI, MRI, B,
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AMDGPUFunctionArgInfo::WORKGROUP_ID_Z);
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default:
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return true;
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}
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@ -5,7 +5,122 @@
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; HSA-NEXT: - { reg: '$sgpr0_sgpr1_sgpr2_sgpr3', virtual-reg: '%0' }
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; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
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; HSA-NEXT: - { reg: '$sgpr4', virtual-reg: '%2' }
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; HSA-NEXT: - { reg: '$sgpr5', virtual-reg: '%3' }
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; HSA-NEXT: frameInfo:
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define amdgpu_kernel void @default_kernel() {
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ret void
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}
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; HSA-LABEL: name: workgroup_id_x{{$}}
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; HSA: liveins:
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; HSA-NEXT: - { reg: '$sgpr0_sgpr1_sgpr2_sgpr3', virtual-reg: '%0' }
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; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
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; HSA-NEXT: - { reg: '$sgpr4', virtual-reg: '%2' }
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; HSA-NEXT: - { reg: '$sgpr5', virtual-reg: '%3' }
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; HSA-NEXT: frameInfo:
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define amdgpu_kernel void @workgroup_id_x() {
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%id = call i32 @llvm.amdgcn.workgroup.id.x()
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store volatile i32 %id, i32 addrspace(1)* undef
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ret void
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}
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; HSA-LABEL: name: workgroup_id_y{{$}}
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; HSA: liveins:
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; HSA-NEXT: - { reg: '$sgpr0_sgpr1_sgpr2_sgpr3', virtual-reg: '%0' }
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; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
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; HSA-NEXT: - { reg: '$sgpr4', virtual-reg: '%2' }
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; HSA-NEXT: - { reg: '$sgpr5', virtual-reg: '%3' }
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; HSA-NEXT: - { reg: '$sgpr6', virtual-reg: '%4' }
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; HSA-NEXT: frameInfo:
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define amdgpu_kernel void @workgroup_id_y() {
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%id = call i32 @llvm.amdgcn.workgroup.id.y()
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store volatile i32 %id, i32 addrspace(1)* undef
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ret void
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}
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; HSA-LABEL: name: workgroup_id_z{{$}}
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; HSA: liveins:
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; HSA-NEXT: - { reg: '$sgpr0_sgpr1_sgpr2_sgpr3', virtual-reg: '%0' }
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; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
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; HSA-NEXT: - { reg: '$sgpr4', virtual-reg: '%2' }
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; HSA-NEXT: - { reg: '$sgpr5', virtual-reg: '%3' }
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; HSA-NEXT: - { reg: '$sgpr6', virtual-reg: '%4' }
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; HSA-NEXT: frameInfo:
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define amdgpu_kernel void @workgroup_id_z() {
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%id = call i32 @llvm.amdgcn.workgroup.id.z()
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store volatile i32 %id, i32 addrspace(1)* undef
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ret void
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}
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; HSA-LABEL: name: workgroup_id_xy{{$}}
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; HSA: liveins:
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; HSA-NEXT: - { reg: '$sgpr0_sgpr1_sgpr2_sgpr3', virtual-reg: '%0' }
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; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
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; HSA-NEXT: - { reg: '$sgpr4', virtual-reg: '%2' }
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; HSA-NEXT: - { reg: '$sgpr5', virtual-reg: '%3' }
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; HSA-NEXT: - { reg: '$sgpr6', virtual-reg: '%4' }
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; HSA-NEXT: frameInfo:
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define amdgpu_kernel void @workgroup_id_xy() {
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%id0 = call i32 @llvm.amdgcn.workgroup.id.x()
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store volatile i32 %id0, i32 addrspace(1)* undef
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%id1 = call i32 @llvm.amdgcn.workgroup.id.y()
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store volatile i32 %id1, i32 addrspace(1)* undef
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ret void
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}
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; HSA-LABEL: name: workgroup_id_xyz{{$}}
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; HSA: liveins:
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; HSA-NEXT: - { reg: '$sgpr0_sgpr1_sgpr2_sgpr3', virtual-reg: '%0' }
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; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
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; HSA-NEXT: - { reg: '$sgpr4', virtual-reg: '%2' }
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; HSA-NEXT: - { reg: '$sgpr5', virtual-reg: '%3' }
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; HSA-NEXT: - { reg: '$sgpr6', virtual-reg: '%4' }
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; HSA-NEXT: frameInfo:
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define amdgpu_kernel void @workgroup_id_xyz() {
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%id0 = call i32 @llvm.amdgcn.workgroup.id.x()
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store volatile i32 %id0, i32 addrspace(1)* undef
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%id1 = call i32 @llvm.amdgcn.workgroup.id.y()
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store volatile i32 %id1, i32 addrspace(1)* undef
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%id2 = call i32 @llvm.amdgcn.workgroup.id.y()
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store volatile i32 %id2, i32 addrspace(1)* undef
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ret void
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}
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; HSA-LABEL: name: workgroup_id_yz{{$}}
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; HSA: liveins:
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; HSA-NEXT: - { reg: '$sgpr0_sgpr1_sgpr2_sgpr3', virtual-reg: '%0' }
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; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
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; HSA-NEXT: - { reg: '$sgpr4', virtual-reg: '%2' }
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; HSA-NEXT: - { reg: '$sgpr5', virtual-reg: '%3' }
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; HSA-NEXT: - { reg: '$sgpr6', virtual-reg: '%4' }
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; HSA-NEXT: frameInfo:
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define amdgpu_kernel void @workgroup_id_yz() {
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%id0 = call i32 @llvm.amdgcn.workgroup.id.x()
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store volatile i32 %id0, i32 addrspace(1)* undef
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%id1 = call i32 @llvm.amdgcn.workgroup.id.y()
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store volatile i32 %id1, i32 addrspace(1)* undef
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ret void
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}
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; HSA-LABEL: name: workgroup_id_xz{{$}}
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; HSA: liveins:
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; HSA-NEXT: - { reg: '$sgpr0_sgpr1_sgpr2_sgpr3', virtual-reg: '%0' }
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; HSA-NEXT: - { reg: '$vgpr0', virtual-reg: '%1' }
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; HSA-NEXT: - { reg: '$sgpr4', virtual-reg: '%2' }
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; HSA-NEXT: - { reg: '$sgpr5', virtual-reg: '%3' }
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; HSA-NEXT: - { reg: '$sgpr6', virtual-reg: '%4' }
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; HSA-NEXT: frameInfo:
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define amdgpu_kernel void @workgroup_id_xz() {
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%id0 = call i32 @llvm.amdgcn.workgroup.id.x()
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store volatile i32 %id0, i32 addrspace(1)* undef
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%id1 = call i32 @llvm.amdgcn.workgroup.id.z()
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store volatile i32 %id1, i32 addrspace(1)* undef
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ret void
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}
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declare i32 @llvm.amdgcn.workgroup.id.x() #0
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declare i32 @llvm.amdgcn.workgroup.id.y() #0
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declare i32 @llvm.amdgcn.workgroup.id.z() #0
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attributes #0 = { nounwind readnone speculatable }
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@ -0,0 +1,106 @@
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; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=CI-HSA %s
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; RUN: llc -global-isel -mtriple=amdgcn-unknown-amdhsa -mattr=-code-object-v3 -mcpu=carrizo -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=CO-V2 -check-prefix=VI-HSA %s
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; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=SI-MESA %s
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; RUN: llc -global-isel -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=UNKNOWN-OS -check-prefix=VI-MESA %s
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; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,SI-MESA %s
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; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -mattr=-code-object-v3 -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=ALL,CO-V2,VI-MESA %s
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declare i32 @llvm.amdgcn.workgroup.id.x() #0
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declare i32 @llvm.amdgcn.workgroup.id.y() #0
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declare i32 @llvm.amdgcn.workgroup.id.z() #0
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; ALL-LABEL {{^}}test_workgroup_id_x:
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; CO-V2: .amd_kernel_code_t
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; CO-V2: user_sgpr_count = 6
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; CO-V2: enable_sgpr_workgroup_id_x = 1
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; CO-V2: enable_sgpr_workgroup_id_y = 0
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; CO-V2: enable_sgpr_workgroup_id_z = 0
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; CO-V2: enable_sgpr_workgroup_info = 0
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; CO-V2: enable_vgpr_workitem_id = 0
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; CO-V2: enable_sgpr_grid_workgroup_count_x = 0
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; CO-V2: enable_sgpr_grid_workgroup_count_y = 0
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; CO-V2: enable_sgpr_grid_workgroup_count_z = 0
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; CO-V2: .end_amd_kernel_code_t
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; UNKNOWN-OS: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s2{{$}}
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; CO-V2: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s6{{$}}
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; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
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; CO-V2: COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; ALL-NOCO-V2: COMPUTE_PGM_RSRC2:USER_SGPR: 2
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; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
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; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
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; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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define amdgpu_kernel void @test_workgroup_id_x(i32 addrspace(1)* %out) #1 {
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%id = call i32 @llvm.amdgcn.workgroup.id.x()
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store i32 %id, i32 addrspace(1)* %out
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ret void
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}
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; ALL-LABEL {{^}}test_workgroup_id_y:
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; CO-V2: user_sgpr_count = 6
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; CO-V2: enable_sgpr_workgroup_id_x = 1
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; CO-V2: enable_sgpr_workgroup_id_y = 1
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; CO-V2: enable_sgpr_workgroup_id_z = 0
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; CO-V2: enable_sgpr_workgroup_info = 0
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; CO-V2: enable_sgpr_grid_workgroup_count_x = 0
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; CO-V2: enable_sgpr_grid_workgroup_count_y = 0
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; CO-V2: enable_sgpr_grid_workgroup_count_z = 0
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; UNKNOWN-OS: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s3{{$}}
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; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}}
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; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
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; CO-V2: COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; ALL-NOCO-V2: COMPUTE_PGM_RSRC2:USER_SGPR: 2
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; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 0
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; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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define amdgpu_kernel void @test_workgroup_id_y(i32 addrspace(1)* %out) #1 {
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%id = call i32 @llvm.amdgcn.workgroup.id.y()
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store i32 %id, i32 addrspace(1)* %out
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ret void
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}
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; ALL-LABEL {{^}}test_workgroup_id_z:
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; CO-V2: user_sgpr_count = 6
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; CO-V2: enable_sgpr_workgroup_id_x = 1
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; CO-V2: enable_sgpr_workgroup_id_y = 0
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; CO-V2: enable_sgpr_workgroup_id_z = 1
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; CO-V2: enable_sgpr_workgroup_info = 0
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; CO-V2: enable_vgpr_workitem_id = 0
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; CO-V2: enable_sgpr_private_segment_buffer = 1
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; CO-V2: enable_sgpr_dispatch_ptr = 0
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; CO-V2: enable_sgpr_queue_ptr = 0
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; CO-V2: enable_sgpr_kernarg_segment_ptr = 1
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; CO-V2: enable_sgpr_dispatch_id = 0
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; CO-V2: enable_sgpr_flat_scratch_init = 0
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; CO-V2: enable_sgpr_private_segment_size = 0
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; CO-V2: enable_sgpr_grid_workgroup_count_x = 0
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; CO-V2: enable_sgpr_grid_workgroup_count_y = 0
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; CO-V2: enable_sgpr_grid_workgroup_count_z = 0
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; UNKNOWN-OS: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s3{{$}}
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; HSA: v_mov_b32_e32 [[VCOPY:v[0-9]+]], s7{{$}}
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; ALL: {{buffer|flat}}_store_dword {{.*}}[[VCOPY]]
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; CO-V2: COMPUTE_PGM_RSRC2:USER_SGPR: 6
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; ALL-NOCO-V2: COMPUTE_PGM_RSRC2:USER_SGPR: 2
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; ALL: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
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; ALL: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
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; ALL: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
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define amdgpu_kernel void @test_workgroup_id_z(i32 addrspace(1)* %out) #1 {
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%id = call i32 @llvm.amdgcn.workgroup.id.z()
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store i32 %id, i32 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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