forked from OSchip/llvm-project
[SCEV] SCEVExpander::isHighCostExpansionHelper(): cost-model add/mul
Summary: While this resolves the regression from D73722 in `llvm/test/Transforms/IndVarSimplify/exit_value_test2.ll`, this now regresses `llvm/test/Transforms/IndVarSimplify/elim-extend.ll` `@nestedIV` test, we no longer can perform that expansion within default budget of `4`, but require budget of `6`. That regression is being addressed by D73777. The basic idea here is simple. ``` Op0, Op1, Op2 ... | | | \--+--/ | | | \---+---/ ``` I.e. given N operands, we will have N-1 operations, so we have to add cost of an add (mul) for **every** Op processed, **except** the first one, plus we need to recurse into *every* Op. I'm guessing there's already canonicalization that ensures we won't have `1` operand in `scMulExpr`, and no `0` in `scAddExpr`/`scMulExpr`. Reviewers: reames, mkazantsev, wmi, sanjoy Reviewed By: mkazantsev Subscribers: hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73728
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@ -2219,6 +2219,40 @@ bool SCEVExpander::isHighCostExpansionHelper(
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TTI, Processed);
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}
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if (S->getSCEVType() == scAddExpr || S->getSCEVType() == scMulExpr) {
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const SCEVNAryExpr *NAry = dyn_cast<SCEVNAryExpr>(S);
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unsigned Opcode;
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switch (S->getSCEVType()) {
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case scAddExpr:
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Opcode = Instruction::Add;
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break;
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case scMulExpr:
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Opcode = Instruction::Mul;
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break;
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default:
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llvm_unreachable("There are no other variants here.");
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}
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Type *OpType = NAry->getType();
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int PairCost = TTI.getOperationCost(Opcode, OpType);
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// TODO: this is a very pessimistic cost modelling for Mul,
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// because of Bin Pow algorithm actually used by the expander,
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// see SCEVExpander::visitMulExpr(), ExpandOpBinPowN().
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assert(NAry->getNumOperands() > 1 &&
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"Nary expr should have more than 1 operand.");
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for (const SCEV *Op : NAry->operands()) {
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if (isHighCostExpansionHelper(Op, L, At, BudgetRemaining, TTI, Processed))
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return true;
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if (Op == *NAry->op_begin())
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continue;
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BudgetRemaining -= PairCost;
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}
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return BudgetRemaining < 0;
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}
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// HowManyLessThans uses a Max expression whenever the loop is not guarded by
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// the exit condition.
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if (isa<SCEVMinMaxExpr>(S))
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@ -135,8 +135,8 @@ define void @nestedIV(i8* %address, i32 %limit) nounwind {
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; CHECK-NEXT: store i8 0, i8* [[ADR2]]
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; CHECK-NEXT: [[ADR3:%.*]] = getelementptr i8, i8* [[ADDRESS]], i64 [[INDVARS_IV_NEXT]]
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; CHECK-NEXT: store i8 0, i8* [[ADR3]]
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], [[TMP0]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[INNERLOOP]], label [[INNEREXIT:%.*]]
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; CHECK-NEXT: [[INNERCMP:%.*]] = icmp sgt i64 [[TMP0]], [[INDVARS_IV_NEXT]]
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; CHECK-NEXT: br i1 [[INNERCMP]], label [[INNERLOOP]], label [[INNEREXIT:%.*]]
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; CHECK: innerexit:
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; CHECK-NEXT: [[INNERCOUNT_LCSSA_WIDE:%.*]] = phi i64 [ [[INDVARS_IV_NEXT]], [[INNERLOOP]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = trunc i64 [[INNERCOUNT_LCSSA_WIDE]] to i32
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@ -19,9 +19,6 @@ define i32 @_Z3fooPKcjj(i8* nocapture readonly %s, i32 %len, i32 %c) {
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; CHECK-NEXT: [[CMP8:%.*]] = icmp ugt i32 [[LEN:%.*]], 11
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; CHECK-NEXT: br i1 [[CMP8]], label [[WHILE_BODY_LR_PH:%.*]], label [[WHILE_END:%.*]]
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; CHECK: while.body.lr.ph:
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; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[LEN]], -12
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; CHECK-NEXT: [[TMP1:%.*]] = udiv i32 [[TMP0]], 12
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; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[TMP1]], 12
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; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
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; CHECK: while.body:
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; CHECK-NEXT: [[KEYLEN_010:%.*]] = phi i32 [ [[LEN]], [[WHILE_BODY_LR_PH]] ], [ [[SUB:%.*]], [[WHILE_BODY]] ]
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@ -39,10 +36,10 @@ define i32 @_Z3fooPKcjj(i8* nocapture readonly %s, i32 %len, i32 %c) {
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; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[SUB]], 11
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; CHECK-NEXT: br i1 [[CMP]], label [[WHILE_BODY]], label [[WHILE_COND_WHILE_END_CRIT_EDGE:%.*]]
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; CHECK: while.cond.while.end_crit_edge:
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; CHECK-NEXT: [[TMP3:%.*]] = sub i32 [[TMP0]], [[TMP2]]
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; CHECK-NEXT: [[SUB_LCSSA:%.*]] = phi i32 [ [[SUB]], [[WHILE_BODY]] ]
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; CHECK-NEXT: br label [[WHILE_END]]
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; CHECK: while.end:
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; CHECK-NEXT: [[KEYLEN_0_LCSSA:%.*]] = phi i32 [ [[TMP3]], [[WHILE_COND_WHILE_END_CRIT_EDGE]] ], [ [[LEN]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: [[KEYLEN_0_LCSSA:%.*]] = phi i32 [ [[SUB_LCSSA]], [[WHILE_COND_WHILE_END_CRIT_EDGE]] ], [ [[LEN]], [[ENTRY:%.*]] ]
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; CHECK-NEXT: call void @_Z3mixRjj(i32* dereferenceable(4) [[A]], i32 [[KEYLEN_0_LCSSA]])
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; CHECK-NEXT: [[T4:%.*]] = load i32, i32* [[A]], align 4
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; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* [[T]])
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