forked from OSchip/llvm-project
[ARM] Prefer BIC over BFC in ARM mode.
BIC is generally faster, and it can put the output in a different register from the input. We already do this in Thumb2 mode; not sure why the equivalent fix never got applied to ARM mode. Differential Revision: https://reviews.llvm.org/D31797 llvm-svn: 299803
This commit is contained in:
Eli Friedman
parent
eb80a51b52
commit
75631c97ba
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@ -3893,6 +3893,7 @@ def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
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let Inst{11-0} = imm;
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}
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let AddedComplexity = 1 in
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def : ARMPat<(and GPR:$src, mod_imm_not:$imm),
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(BICri GPR:$src, mod_imm_not:$imm)>;
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@ -19,7 +19,7 @@ entry:
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call void @llvm.va_start(i8* %g1)
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; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
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; CHECK: bfc [[REG]], #0, #3
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; CHECK: bic [[REG]], [[REG]], #7
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%0 = va_arg i8** %g, double
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call void @llvm.va_end(i8* %g1)
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@ -77,7 +77,7 @@ entry:
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define i32 @f7(i32 %x, i32 %y) {
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; CHECK-LABEL: f7:
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; CHECK: bfi r1, r0, #4, #1
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; CHECK: bfi r0, r2, #4, #1
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%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
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%and = and i32 %x, 4
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%or = or i32 %y2, 16
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@ -88,8 +88,8 @@ define i32 @f7(i32 %x, i32 %y) {
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define i32 @f8(i32 %x, i32 %y) {
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; CHECK-LABEL: f8:
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; CHECK: bfi r1, r0, #4, #1
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; CHECK: bfi r1, r0, #5, #1
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; CHECK: bfi r0, r2, #4, #1
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; CHECK: bfi r0, r2, #5, #1
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%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
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%and = and i32 %x, 4
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%or = or i32 %y2, 48
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@ -111,7 +111,7 @@ define i32 @f9(i32 %x, i32 %y) {
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define i32 @f10(i32 %x, i32 %y) {
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; CHECK-LABEL: f10:
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; CHECK: bfi r1, r0, #4, #2
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; CHECK: bfi r0, r2, #4, #2
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%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
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%and = and i32 %x, 4
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%or = or i32 %y2, 32
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@ -128,7 +128,7 @@ define i32 @f10(i32 %x, i32 %y) {
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define i32 @f11(i32 %x, i32 %y) {
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; CHECK-LABEL: f11:
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; CHECK: bfi r1, r0, #4, #3
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; CHECK: bfi r0, r2, #4, #3
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%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
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%and = and i32 %x, 4
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%or = or i32 %y2, 32
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@ -150,7 +150,7 @@ define i32 @f11(i32 %x, i32 %y) {
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define i32 @f12(i32 %x, i32 %y) {
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; CHECK-LABEL: f12:
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; CHECK: bfi r1, r0, #4, #1
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; CHECK: bfi r0, r2, #4, #1
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%y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
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%and = and i32 %x, 4
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%or = or i32 %y2, 16
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@ -1,17 +1,24 @@
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; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
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define i32 @f1(i32 %a, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: bic r0, r0, r1
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%tmp = xor i32 %b, 4294967295
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%tmp1 = and i32 %a, %tmp
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ret i32 %tmp1
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}
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; CHECK: bic r0, r0, r1
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define i32 @f2(i32 %a, i32 %b) {
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; CHECK-LABEL: f2:
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; CHECK: bic r0, r0, r1
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%tmp = xor i32 %b, 4294967295
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%tmp1 = and i32 %tmp, %a
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ret i32 %tmp1
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}
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; CHECK: bic r0, r0, r1
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define i32 @f3(i32 %a) {
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; CHECK-LABEL: f3:
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; CHECK: bic r0, r0, #255
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%tmp = and i32 %a, -256
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ret i32 %tmp
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}
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@ -597,7 +597,7 @@ define void @test_fma(half* %p, half* %q, half* %r) #0 {
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; CHECK-FP16: vcvtb.f16.f32
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; CHECK-LIBCALL-LABEL: test_fabs:
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; CHECK-LIBCALL: bl __aeabi_h2f
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; CHECK-LIBCALL: bfc
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; CHECK-LIBCALL: bic
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; CHECK-LIBCALL: bl __aeabi_f2h
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define void @test_fabs(half* %p) {
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%a = load half, half* %p, align 2
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@ -687,7 +687,7 @@ define void @test_maxnan(half* %p) #0 {
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; CHECK-LIBCALL: bl __aeabi_h2f
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; CHECK-LIBCALL: bl __aeabi_h2f
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; CHECK-VFP-LIBCALL: vbsl
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; CHECK-NOVFP: bfc
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; CHECK-NOVFP: bic
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; CHECK-NOVFP: and
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; CHECK-NOVFP: orr
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; CHECK-LIBCALL: bl __aeabi_f2h
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@ -35,7 +35,7 @@ entry:
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; CHECK-NOT: vldr
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; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0]
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; CHECK-NOT: b LBB
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; CHECK: bfc [[REG2]], #31, #1
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; CHECK: bic [[REG2]], [[REG2]], #-2147483648
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; CHECK: cmp [[REG1]], #0
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; CHECK: cmpeq [[REG2]], #0
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; CHECK-NOT: vcmp.f32
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@ -14,8 +14,7 @@ define double @f(double %a) {
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define float @g(float %a) {
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; CHECK-LABEL: g:
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; CHECK-THUMB: bic r0, r0, #-2147483648
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; CHECK-ARM: bfc r0, #31, #1
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; CHECK: bic r0, r0, #-2147483648
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; CHECK-NEXT: bx lr
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%x = call float @llvm.fabs.f32(float %a) readnone
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ret float %x
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@ -4,8 +4,8 @@
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; CHECK-LABEL: test1:
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; CHECK-NOT: bfc
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; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
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; CHECK: bfc [[REG]], #0, #3
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; CHECK-NOT: bfc
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; CHECK: bic {{(r[0-9]+)|(lr)}}, [[REG]], #7
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; CHECK-NOT: bic
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define i64 @test1(i32 %i, ...) nounwind optsize {
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entry:
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@ -20,8 +20,8 @@ entry:
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; CHECK-LABEL: test2:
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; CHECK-NOT: bfc
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; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
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; CHECK: bfc [[REG]], #0, #3
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; CHECK-NOT: bfc
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; CHECK: bic {{(r[0-9]+)|(lr)}}, [[REG]], #7
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; CHECK-NOT: bic
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; CHECK: bx lr
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define double @test2(i32 %a, i32* %b, ...) nounwind optsize {
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