forked from OSchip/llvm-project
AMDGPU/GlobalISel: Rewrite fadd select tests
Convert to the style most others use with one test instruction per function, and use an implicit use to ensure the result register class is constrained. Change-Id: I6109148b0e3c80aa5535796a37abca583c19a936
This commit is contained in:
Matt Arsenault
parent
01213f9070
commit
752e2e245a
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@ -1,33 +0,0 @@
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
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---
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name: fadd
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legalized: true
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regBankSelected: true
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# GCN-LABEL: name: fadd
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr3_vgpr4
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = COPY $vgpr1
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%3:vgpr(p1) = COPY $vgpr3_vgpr4
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; fadd vs
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; GCN: V_ADD_F32_e64
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%4:vgpr(s32) = G_FADD %1, %0
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; fadd sv
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; GCN: V_ADD_F32_e64
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%5:vgpr(s32) = G_FADD %0, %1
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; fadd vv
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; GCN: V_ADD_F32_e64
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%6:vgpr(s32) = G_FADD %1, %2
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G_STORE %4, %3 :: (store 4, addrspace 1)
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G_STORE %5, %3 :: (store 4, addrspace 1)
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G_STORE %6, %3 :: (store 4, addrspace 1)
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...
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@ -0,0 +1,193 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
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---
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name: fadd_s16_vvv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX8-LABEL: name: fadd_s16_vvv
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FADD %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: fadd_s16_vsv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GFX8-LABEL: name: fadd_s16_vsv
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; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FADD %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: fadd_s16_vvs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GFX8-LABEL: name: fadd_s16_vvs
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s16) = G_TRUNC %0
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%3:sgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FADD %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: fadd_s16_vvv_fabs_lhs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX8-LABEL: name: fadd_s16_vvv_fabs_lhs
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FABS %2
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%5:vgpr(s16) = G_FADD %4, %3
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S_ENDPGM 0, implicit %5
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...
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---
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name: fadd_s16_vvv_fabs_rhs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX8-LABEL: name: fadd_s16_vvv_fabs_rhs
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 2, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FABS %3
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%5:vgpr(s16) = G_FADD %2, %4
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S_ENDPGM 0, implicit %5
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...
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---
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name: fadd_s16_vvv_fneg_fabs_lhs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_lhs
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FABS %2
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%5:vgpr(s16) = G_FNEG %4
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%6:vgpr(s16) = G_FADD %5, %3
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S_ENDPGM 0, implicit %6
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...
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---
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name: fadd_s16_vvv_fneg_fabs_rhs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX8-LABEL: name: fadd_s16_vvv_fneg_fabs_rhs
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s16) = G_TRUNC %0
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FABS %3
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%5:vgpr(s16) = G_FNEG %4
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%6:vgpr(s16) = G_FADD %2, %5
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S_ENDPGM 0, implicit %6
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...
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---
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name: fadd_s16_fneg_copy_sgpr
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GFX8-LABEL: name: fadd_s16_fneg_copy_sgpr
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX8: [[V_ADD_F16_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F16_e64 0, [[COPY]], 1, [[COPY1]], 0, 0, implicit $exec
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; GFX8: S_ENDPGM 0, implicit [[V_ADD_F16_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s16) = G_TRUNC %0
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%3:sgpr(s16) = G_TRUNC %1
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%4:sgpr(s16) = G_FNEG %3
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%5:vgpr(s16) = G_FADD %2, %4
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S_ENDPGM 0, implicit %5
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...
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@ -0,0 +1,211 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
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---
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name: fadd_s32_vvv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: fadd_s32_vvv
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_FADD %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fadd_s32_vsv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GFX6-LABEL: name: fadd_s32_vsv
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; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_FADD %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fadd_s32_vvs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $sgpr0
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; GFX6-LABEL: name: fadd_s32_vvs
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = G_FADD %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fadd_s32_vvv_fabs_lhs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: fadd_s32_vvv_fabs_lhs
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_FABS %0
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%3:vgpr(s32) = G_FADD %2, %1
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S_ENDPGM 0, implicit %3
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...
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---
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|
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name: fadd_s32_vvv_fabs_rhs
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legalized: true
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regBankSelected: true
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|
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body: |
|
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: fadd_s32_vvv_fabs_rhs
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_FABS %1
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%3:vgpr(s32) = G_FADD %1, %2
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S_ENDPGM 0, implicit %3
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|
||||
...
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|
||||
---
|
||||
|
||||
name: fadd_s32_vvv_fneg_fabs_lhs
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legalized: true
|
||||
regBankSelected: true
|
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|
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body: |
|
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bb.0:
|
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_lhs
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_FABS %0
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%3:vgpr(s32) = G_FNEG %2
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%4:vgpr(s32) = G_FADD %3, %1
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S_ENDPGM 0, implicit %4
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...
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|
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---
|
||||
|
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name: fadd_s32_vvv_fneg_fabs_rhs
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legalized: true
|
||||
regBankSelected: true
|
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|
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body: |
|
||||
bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_rhs
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $exec
|
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; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s32) = G_FABS %1
|
||||
%3:vgpr(s32) = G_FNEG %2
|
||||
%4:vgpr(s32) = G_FADD %1, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
# Need to look through reg bank copy to find source modifiers
|
||||
---
|
||||
|
||||
name: fadd_s32_fneg_copy_sgpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $sgpr0
|
||||
; GFX6-LABEL: name: fadd_s32_fneg_copy_sgpr
|
||||
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
|
||||
; GFX6: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_XOR_B32_]]
|
||||
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[COPY2]], 0, 0, implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr0
|
||||
%2:sgpr(s32) = G_FNEG %1
|
||||
%3:vgpr(s32) = COPY %2
|
||||
%4:vgpr(s32) = G_FADD %0, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
# Need to look through copy in between fneg and fabs
|
||||
|
||||
---
|
||||
|
||||
name: fadd_s32_copy_fneg_copy_fabs
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $sgpr0
|
||||
; GFX6-LABEL: name: fadd_s32_copy_fneg_copy_fabs
|
||||
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
||||
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483647
|
||||
; GFX6: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[COPY1]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; GFX6: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
|
||||
; GFX6: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[S_AND_B32_]], [[S_MOV_B32_1]], implicit-def $scc
|
||||
; GFX6: [[V_ADD_F32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_F32_e64 0, [[COPY]], 0, [[S_XOR_B32_]], 0, 0, implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F32_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:sgpr(s32) = COPY $sgpr0
|
||||
%2:sgpr(s32) = G_FABS %1
|
||||
%3:sgpr(s32) = COPY %2
|
||||
%4:sgpr(s32) = G_FNEG %3
|
||||
%5:sgpr(s32) = COPY %4
|
||||
%6:vgpr(s32) = G_FADD %0, %5
|
||||
S_ENDPGM 0, implicit %6
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,184 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
|
||||
|
||||
---
|
||||
|
||||
name: fadd_s64_vvv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; GFX6-LABEL: name: fadd_s64_vvv
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vgpr(s64) = G_FADD %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: fadd_s64_vsv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
|
||||
; GFX6-LABEL: name: fadd_s64_vsv
|
||||
; GFX6: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
|
||||
%0:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%2:vgpr(s64) = G_FADD %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: fadd_s64_vvs
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
|
||||
; GFX6-LABEL: name: fadd_s64_vvs
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
%2:vgpr(s64) = G_FADD %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: fadd_s64_vvv_fabs_lhs
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; GFX6-LABEL: name: fadd_s64_vvv_fabs_lhs
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vgpr(s64) = G_FABS %0
|
||||
%3:vgpr(s64) = G_FADD %2, %1
|
||||
S_ENDPGM 0, implicit %3
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: fadd_s64_vvv_fabs_rhs
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; GFX6-LABEL: name: fadd_s64_vvv_fabs_rhs
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vgpr(s64) = G_FABS %1
|
||||
%3:vgpr(s64) = G_FADD %1, %2
|
||||
S_ENDPGM 0, implicit %3
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: fadd_s64_vvv_fneg_fabs_lhs
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; GFX6-LABEL: name: fadd_s64_vvv_fneg_fabs_lhs
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vgpr(s64) = G_FABS %0
|
||||
%3:vgpr(s64) = G_FNEG %2
|
||||
%4:vgpr(s64) = G_FADD %3, %1
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
|
||||
name: fadd_s64_vvv_fneg_fabs_rhs
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; GFX6-LABEL: name: fadd_s64_vvv_fneg_fabs_rhs
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%2:vgpr(s64) = G_FABS %1
|
||||
%3:vgpr(s64) = G_FNEG %2
|
||||
%4:vgpr(s64) = G_FADD %1, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
|
||||
# Need to look through reg bank copy to find source modifiers
|
||||
|
||||
---
|
||||
|
||||
name: fadd_s64_fneg_copy_sgpr
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $sgpr0_sgpr1
|
||||
; GFX6-LABEL: name: fadd_s64_fneg_copy_sgpr
|
||||
; GFX6: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; GFX6: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
|
||||
; GFX6: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub0
|
||||
; GFX6: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[COPY1]].sub1
|
||||
; GFX6: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 2147483648
|
||||
; GFX6: [[S_XOR_B32_:%[0-9]+]]:sreg_32 = S_XOR_B32 [[COPY3]], [[S_MOV_B32_]], implicit-def $scc
|
||||
; GFX6: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[S_XOR_B32_]], %subreg.sub1
|
||||
; GFX6: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
|
||||
; GFX6: [[V_ADD_F64_:%[0-9]+]]:vreg_64 = V_ADD_F64 0, [[COPY]], 0, [[COPY4]], 0, 0, implicit $exec
|
||||
; GFX6: S_ENDPGM 0, implicit [[V_ADD_F64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:sgpr(s64) = COPY $sgpr0_sgpr1
|
||||
%2:sgpr(s64) = G_FNEG %1
|
||||
%3:vgpr(s64) = COPY %2
|
||||
%4:vgpr(s64) = G_FADD %0, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue