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[AVX-512] Add VPMULLD/Q/W instructions to load folding tables. 

llvm-svn: 294164
This commit is contained in:
Craig Topper 2017-02-06 01:19:26 +00:00
parent 452a7770e6
commit 75218fb6b1
1 changed files with 27 additions and 0 deletions
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27
llvm/lib/Target/X86/X86InstrInfo.cpp
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@ -1891,6 +1891,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
{ X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
{ X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
{ X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
{ X86::VPMULLDZrr, X86::VPMULLDZrm, 0 },
{ X86::VPMULLQZrr, X86::VPMULLQZrm, 0 },
{ X86::VPMULLWZrr, X86::VPMULLWZrm, 0 },
{ X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
{ X86::VPORDZrr, X86::VPORDZrm, 0 },
{ X86::VPORQZrr, X86::VPORQZrm, 0 },
@ -2062,6 +2065,12 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
{ X86::VPMADDWDZ256rr, X86::VPMADDWDZ256rm, 0 },
{ X86::VPMULDQZ128rr, X86::VPMULDQZ128rm, 0 },
{ X86::VPMULDQZ256rr, X86::VPMULDQZ256rm, 0 },
{ X86::VPMULLDZ128rr, X86::VPMULLDZ128rm, 0 },
{ X86::VPMULLDZ256rr, X86::VPMULLDZ256rm, 0 },
{ X86::VPMULLQZ128rr, X86::VPMULLQZ128rm, 0 },
{ X86::VPMULLQZ256rr, X86::VPMULLQZ256rm, 0 },
{ X86::VPMULLWZ128rr, X86::VPMULLWZ128rm, 0 },
{ X86::VPMULLWZ256rr, X86::VPMULLWZ256rm, 0 },
{ X86::VPMULUDQZ128rr, X86::VPMULUDQZ128rm, 0 },
{ X86::VPMULUDQZ256rr, X86::VPMULUDQZ256rm, 0 },
{ X86::VPORDZ128rr, X86::VPORDZ128rm, 0 },
@ -2380,6 +2389,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
{ X86::VPERMWZrrkz, X86::VPERMWZrmkz, 0 },
{ X86::VPMADDUBSWZrrkz, X86::VPMADDUBSWZrmkz, 0 },
{ X86::VPMADDWDZrrkz, X86::VPMADDWDZrmkz, 0 },
{ X86::VPMULLDZrrkz, X86::VPMULLDZrmkz, 0 },
{ X86::VPMULLQZrrkz, X86::VPMULLQZrmkz, 0 },
{ X86::VPMULLWZrrkz, X86::VPMULLWZrmkz, 0 },
{ X86::VPMULDQZrrkz, X86::VPMULDQZrmkz, 0 },
{ X86::VPMULUDQZrrkz, X86::VPMULUDQZrmkz, 0 },
{ X86::VPORDZrrkz, X86::VPORDZrmkz, 0 },
@ -2465,6 +2477,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
{ X86::VPMADDUBSWZ256rrkz, X86::VPMADDUBSWZ256rmkz, 0 },
{ X86::VPMADDWDZ256rrkz, X86::VPMADDWDZ256rmkz, 0 },
{ X86::VPMULDQZ256rrkz, X86::VPMULDQZ256rmkz, 0 },
{ X86::VPMULLDZ256rrkz, X86::VPMULLDZ256rmkz, 0 },
{ X86::VPMULLQZ256rrkz, X86::VPMULLQZ256rmkz, 0 },
{ X86::VPMULLWZ256rrkz, X86::VPMULLWZ256rmkz, 0 },
{ X86::VPMULUDQZ256rrkz, X86::VPMULUDQZ256rmkz, 0 },
{ X86::VPORDZ256rrkz, X86::VPORDZ256rmkz, 0 },
{ X86::VPORQZ256rrkz, X86::VPORQZ256rmkz, 0 },
@ -2539,6 +2554,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
{ X86::VPMADDUBSWZ128rrkz, X86::VPMADDUBSWZ128rmkz, 0 },
{ X86::VPMADDWDZ128rrkz, X86::VPMADDWDZ128rmkz, 0 },
{ X86::VPMULDQZ128rrkz, X86::VPMULDQZ128rmkz, 0 },
{ X86::VPMULLDZ128rrkz, X86::VPMULLDZ128rmkz, 0 },
{ X86::VPMULLQZ128rrkz, X86::VPMULLQZ128rmkz, 0 },
{ X86::VPMULLWZ128rrkz, X86::VPMULLWZ128rmkz, 0 },
{ X86::VPMULUDQZ128rrkz, X86::VPMULUDQZ128rmkz, 0 },
{ X86::VPORDZ128rrkz, X86::VPORDZ128rmkz, 0 },
{ X86::VPORQZ128rrkz, X86::VPORQZ128rmkz, 0 },
@ -2738,6 +2756,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
{ X86::VPMADDUBSWZrrk, X86::VPMADDUBSWZrmk, 0 },
{ X86::VPMADDWDZrrk, X86::VPMADDWDZrmk, 0 },
{ X86::VPMULDQZrrk, X86::VPMULDQZrmk, 0 },
{ X86::VPMULLDZrrk, X86::VPMULLDZrmk, 0 },
{ X86::VPMULLQZrrk, X86::VPMULLQZrmk, 0 },
{ X86::VPMULLWZrrk, X86::VPMULLWZrmk, 0 },
{ X86::VPMULUDQZrrk, X86::VPMULUDQZrmk, 0 },
{ X86::VPORDZrrk, X86::VPORDZrmk, 0 },
{ X86::VPORQZrrk, X86::VPORQZrmk, 0 },
@ -2835,6 +2856,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
{ X86::VPMADDUBSWZ256rrk, X86::VPMADDUBSWZ256rmk, 0 },
{ X86::VPMADDWDZ256rrk, X86::VPMADDWDZ256rmk, 0 },
{ X86::VPMULDQZ256rrk, X86::VPMULDQZ256rmk, 0 },
{ X86::VPMULLDZ256rrk, X86::VPMULLDZ256rmk, 0 },
{ X86::VPMULLQZ256rrk, X86::VPMULLQZ256rmk, 0 },
{ X86::VPMULLWZ256rrk, X86::VPMULLWZ256rmk, 0 },
{ X86::VPMULUDQZ256rrk, X86::VPMULUDQZ256rmk, 0 },
{ X86::VPORDZ256rrk, X86::VPORDZ256rmk, 0 },
{ X86::VPORQZ256rrk, X86::VPORQZ256rmk, 0 },
@ -2923,6 +2947,9 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
{ X86::VPMADDUBSWZ128rrk, X86::VPMADDUBSWZ128rmk, 0 },
{ X86::VPMADDWDZ128rrk, X86::VPMADDWDZ128rmk, 0 },
{ X86::VPMULDQZ128rrk, X86::VPMULDQZ128rmk, 0 },
{ X86::VPMULLDZ128rrk, X86::VPMULLDZ128rmk, 0 },
{ X86::VPMULLQZ128rrk, X86::VPMULLQZ128rmk, 0 },
{ X86::VPMULLWZ128rrk, X86::VPMULLWZ128rmk, 0 },
{ X86::VPMULUDQZ128rrk, X86::VPMULUDQZ128rmk, 0 },
{ X86::VPORDZ128rrk, X86::VPORDZ128rmk, 0 },
{ X86::VPORQZ128rrk, X86::VPORQZ128rmk, 0 },