forked from OSchip/llvm-project
[RISCV] Trim RVV isel pats matchable via DAG post-process
In D122512, several masked patterns were added to support lowering of vector-predicated float-to-int and int-to-float conversions. With the introduction of these patterns, all of the old "unmasked" patterns are matchable via the DAG post-process introduced in D118810, once the relevant opcode entries are set up in the helper table. Locally this reduces the generated isel table by 4%. Reviewed By: arcbbb Differential Revision: https://reviews.llvm.org/D122637
This commit is contained in:
Fraser Cormack
parent
ea043ea183
commit
75047577d6
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@ -2102,6 +2102,7 @@ multiclass PseudoVEXT_VF2 {
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Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
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def "_" # m.MX # "_MASK" :
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VPseudoUnaryMaskTA<m.vrclass, m.f2vrclass, constraints>,
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RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
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Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
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}
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}
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@ -2118,6 +2119,7 @@ multiclass PseudoVEXT_VF4 {
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Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
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def "_" # m.MX # "_MASK" :
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VPseudoUnaryMaskTA<m.vrclass, m.f4vrclass, constraints>,
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RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
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Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
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}
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}
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@ -2134,6 +2136,7 @@ multiclass PseudoVEXT_VF8 {
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Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
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def "_" # m.MX # "_MASK" :
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VPseudoUnaryMaskTA<m.vrclass, m.f8vrclass, constraints>,
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RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
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Sched<[WriteVExtV, ReadVExtV, ReadVMask]>;
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}
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}
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@ -2669,7 +2672,8 @@ multiclass VPseudoConversion<VReg RetClass,
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def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>;
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def "_" # MInfo.MX # "_TU": VPseudoUnaryNoMaskTU<RetClass, Op1Class, Constraint>;
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def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskTA<RetClass, Op1Class,
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Constraint>;
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Constraint>,
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RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
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}
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}
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@ -549,10 +549,6 @@ multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix,
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foreach vtiTofti = fraction_list in {
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defvar vti = vtiTofti.Vti;
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defvar fti = vtiTofti.Fti;
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def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2),
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true_mask, VLOpFrag)),
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(!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX)
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fti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>;
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def : Pat<(vti.Vector (vop (fti.Vector fti.RegClass:$rs2),
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(fti.Mask V0), VLOpFrag)),
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(!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX#"_MASK")
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@ -565,11 +561,6 @@ multiclass VPatExtendSDNode_V_VL<SDNode vop, string inst_name, string suffix,
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multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
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foreach fvti = AllFloatVectors in {
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defvar ivti = GetIntVTypeInfo<fvti>.Vti;
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def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
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(fvti.Mask true_mask),
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
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fvti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>;
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def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
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(fvti.Mask V0),
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VLOpFrag)),
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@ -582,11 +573,6 @@ multiclass VPatConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
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multiclass VPatConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
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foreach fvti = AllFloatVectors in {
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defvar ivti = GetIntVTypeInfo<fvti>.Vti;
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def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
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(ivti.Mask true_mask),
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
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ivti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
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(ivti.Mask V0),
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VLOpFrag)),
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@ -600,11 +586,6 @@ multiclass VPatWConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
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foreach fvtiToFWti = AllWidenableFloatVectors in {
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defvar fvti = fvtiToFWti.Vti;
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defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
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def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
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(fvti.Mask true_mask),
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
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fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
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def : Pat<(iwti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
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(fvti.Mask V0),
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VLOpFrag)),
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@ -618,11 +599,6 @@ multiclass VPatWConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
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foreach vtiToWti = AllWidenableIntToFloatVectors in {
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defvar ivti = vtiToWti.Vti;
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defvar fwti = vtiToWti.Wti;
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def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
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(ivti.Mask true_mask),
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX)
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ivti.RegClass:$rs1, GPR:$vl, ivti.Log2SEW)>;
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def : Pat<(fwti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
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(ivti.Mask V0),
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VLOpFrag)),
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@ -636,11 +612,6 @@ multiclass VPatNConvertFP2ISDNode_V_VL<SDNode vop, string instruction_name> {
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foreach vtiToWti = AllWidenableIntToFloatVectors in {
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defvar vti = vtiToWti.Vti;
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defvar fwti = vtiToWti.Wti;
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def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1),
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(fwti.Mask true_mask),
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#vti.LMul.MX)
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fwti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>;
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def : Pat<(vti.Vector (vop (fwti.Vector fwti.RegClass:$rs1),
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(fwti.Mask V0),
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VLOpFrag)),
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@ -654,11 +625,6 @@ multiclass VPatNConvertI2FPSDNode_V_VL<SDNode vop, string instruction_name> {
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foreach fvtiToFWti = AllWidenableFloatVectors in {
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defvar fvti = fvtiToFWti.Vti;
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defvar iwti = GetIntVTypeInfo<fvtiToFWti.Wti>.Vti;
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def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1),
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(iwti.Mask true_mask),
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VLOpFrag)),
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(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX)
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iwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (vop (iwti.Vector iwti.RegClass:$rs1),
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(iwti.Mask V0),
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VLOpFrag)),
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@ -1547,11 +1513,6 @@ foreach fvti = AllFloatVectors in {
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foreach fvtiToFWti = AllWidenableFloatVectors in {
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defvar fvti = fvtiToFWti.Vti;
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defvar fwti = fvtiToFWti.Wti;
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def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1),
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(fvti.Mask true_mask),
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VLOpFrag)),
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(!cast<Instruction>("PseudoVFWCVT_F_F_V_"#fvti.LMul.MX)
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fvti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
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def : Pat<(fwti.Vector (riscv_fpextend_vl (fvti.Vector fvti.RegClass:$rs1),
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(fvti.Mask V0),
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VLOpFrag)),
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@ -1568,11 +1529,6 @@ foreach fvti = AllFloatVectors in {
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foreach fvtiToFWti = AllWidenableFloatVectors in {
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defvar fvti = fvtiToFWti.Vti;
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defvar fwti = fvtiToFWti.Wti;
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def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1),
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(fwti.Mask true_mask),
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VLOpFrag)),
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(!cast<Instruction>("PseudoVFNCVT_F_F_W_"#fvti.LMul.MX)
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fwti.RegClass:$rs1, GPR:$vl, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (riscv_fpround_vl (fwti.Vector fwti.RegClass:$rs1),
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(fwti.Mask V0),
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VLOpFrag)),
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