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[ARM] Generate test checks for umulo-32.ll; NFC 

The second test case is going to be changed by D59041, so generate
full baseline checks.

llvm-svn: 355775
This commit is contained in:
Nikita Popov 2019-03-09 13:21:15 +00:00
parent 377d9dc872
commit 74dde7e5a1
1 changed files with 45 additions and 9 deletions
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54
llvm/test/CodeGen/ARM/umulo-32.ll
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@ -1,10 +1,24 @@
; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=thumbv6-unknown-linux-gnu | FileCheck %s
%umul.ty = type { i32, i1 }
define i32 @test1(i32 %a, i1 %x) nounwind {
; CHECK: test1:
; CHECK: muldi3
; CHECK-LABEL: test1:
; CHECK: @ %bb.0:
; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: mov r5, r1
; CHECK-NEXT: movs r2, #37
; CHECK-NEXT: movs r4, #0
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r3, r4
; CHECK-NEXT: bl __muldi3
; CHECK-NEXT: lsls r1, r5, #31
; CHECK-NEXT: beq .LBB0_2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: mvns r0, r4
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: pop {r4, r5, r7, pc}
%tmp0 = tail call %umul.ty @llvm.umul.with.overflow.i32(i32 %a, i32 37)
%tmp1 = extractvalue %umul.ty %tmp0, 0
%tmp2 = select i1 %x, i32 -1, i32 %tmp1
@ -14,12 +28,34 @@ define i32 @test1(i32 %a, i1 %x) nounwind {
declare %umul.ty @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
define i32 @test2(i32 %argc, i8** %argv) ssp {
; CHECK: test2:
; CHECK: str r0
; CHECK: movs r2
; CHECK: mov r1
; CHECK: mov r3
; CHECK: muldi3
; CHECK-LABEL: test2:
; CHECK: @ %bb.0:
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: sub sp, #16
; CHECK-NEXT: str r0, [sp, #8]
; CHECK-NEXT: movs r4, #0
; CHECK-NEXT: str r4, [sp, #12]
; CHECK-NEXT: str r1, [sp, #4]
; CHECK-NEXT: movs r0, #10
; CHECK-NEXT: str r0, [sp]
; CHECK-NEXT: movs r2, #8
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: mov r3, r4
; CHECK-NEXT: bl __muldi3
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: beq .LBB1_2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: movs r1, #1
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: beq .LBB1_4
; CHECK-NEXT: @ %bb.3:
; CHECK-NEXT: mvns r0, r4
; CHECK-NEXT: .LBB1_4:
; CHECK-NEXT: bl _Znam
; CHECK-NEXT: mov r0, r4
; CHECK-NEXT: add sp, #16
; CHECK-NEXT: pop {r4, pc}
%1 = alloca i32, align 4
%2 = alloca i32, align 4
%3 = alloca i8**, align 4