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[RISCV] Use PatFrags for variable shift patterns 

This follows SystemZ and I think is cleaner vs the multiclass.

llvm-svn: 345262
This commit is contained in:
Alex Bradbury 2018-10-25 12:45:20 +00:00
parent 0573b8d8b6
commit 74d4931da2
1 changed files with 8 additions and 9 deletions
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17
llvm/lib/Target/RISCV/RISCVInstrInfo.td
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@ -206,7 +206,7 @@ def ixlenimm : Operand<XLenVT> {
def simm32 : ImmLeaf<XLenVT, [{return isInt<32>(Imm);}]>;
def simm32hi20 : ImmLeaf<XLenVT, [{return isShiftedInt<20, 12>(Imm);}]>;
// A mask value that won't affect significant shift bits.
def immshiftxlen : ImmLeaf<XLenVT, [{
def immbottomxlenset : ImmLeaf<XLenVT, [{
if (Subtarget->is64Bit())
return countTrailingOnes<uint64_t>(Imm) >= 6;
return countTrailingOnes<uint64_t>(Imm) >= 5;
@ -660,15 +660,14 @@ def : PatGprUimmLog2XLen<sra, SRAI>;
// typically introduced when the legalizer promotes the shift amount and
// zero-extends it). For RISC-V, the mask is unnecessary as shifts in the base
// ISA only read the least significant 5 bits (RV32I) or 6 bits (RV64I).
multiclass VarShiftXLenPat<PatFrag ShiftOp, RVInst Inst> {
def : Pat<(ShiftOp GPR:$rs1, GPR:$rs2), (Inst GPR:$rs1, GPR:$rs2)>;
def : Pat<(ShiftOp GPR:$rs1, (and GPR:$rs2, immshiftxlen)),
(Inst GPR:$rs1, GPR:$rs2)>;
}
class shiftop<SDPatternOperator operator>
: PatFrags<(ops node:$val, node:$count),
[(operator node:$val, node:$count),
(operator node:$val, (and node:$count, immbottomxlenset))]>;
defm : VarShiftXLenPat<shl, SLL>;
defm : VarShiftXLenPat<srl, SRL>;
defm : VarShiftXLenPat<sra, SRA>;
def : PatGprGpr<shiftop<shl>, SLL>;
def : PatGprGpr<shiftop<srl>, SRL>;
def : PatGprGpr<shiftop<sra>, SRA>;
/// FrameIndex calculations