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[RISCV] Lower calls through PLT 

This patch adds support for generating calls through the procedure
linkage table where required for a given ExternalSymbol or GlobalAddress
callee.

Differential Revision: https://reviews.llvm.org/D55304

llvm-svn: 363686
This commit is contained in:
Lewis Revill 2019-06-18 14:29:45 +00:00
parent 2fef12ccb1
commit 74c8364954
4 changed files with 142 additions and 4 deletions
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18
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -1921,11 +1921,21 @@ SDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
// TargetGlobalAddress/TargetExternalSymbol node so that legalize won't
// split it and then direct call can be matched by PseudoCALL.
if (GlobalAddressSDNode *S = dyn_cast<GlobalAddressSDNode>(Callee)) {
Callee = DAG.getTargetGlobalAddress(S->getGlobal(), DL, PtrVT, 0,
RISCVII::MO_CALL);
const GlobalValue *GV = S->getGlobal();
unsigned OpFlags = RISCVII::MO_CALL;
if (!getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV))
OpFlags = RISCVII::MO_PLT;
Callee = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, OpFlags);
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
Callee =
DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, RISCVII::MO_CALL);
unsigned OpFlags = RISCVII::MO_CALL;
if (!getTargetMachine().shouldAssumeDSOLocal(*MF.getFunction().getParent(),
nullptr))
OpFlags = RISCVII::MO_PLT;
Callee = DAG.getTargetExternalSymbol(S->getSymbol(), PtrVT, OpFlags);
}
// The first call operand is the chain and the second is the target address.

3
llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
View File

@ -39,6 +39,9 @@ static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
case RISCVII::MO_CALL:
Kind = RISCVMCExpr::VK_RISCV_CALL;
break;
case RISCVII::MO_PLT:
Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
break;
case RISCVII::MO_LO:
Kind = RISCVMCExpr::VK_RISCV_LO;
break;

1
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
View File

@ -49,6 +49,7 @@ enum {
enum {
MO_None,
MO_CALL,
MO_PLT,
MO_LO,
MO_HI,
MO_PCREL_LO,

124
llvm/test/CodeGen/RISCV/calls.ll
View File

@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -relocation-model=pic -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I-PIC %s
declare i32 @external_function(i32)
@ -13,15 +15,53 @@ define i32 @test_call_external(i32 %a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-PIC-LABEL: test_call_external:
; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp)
; RV32I-PIC-NEXT: call external_function@plt
; RV32I-PIC-NEXT: lw ra, 12(sp)
; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret
%1 = call i32 @external_function(i32 %a)
ret i32 %1
}
declare dso_local i32 @dso_local_function(i32)
define i32 @test_call_dso_local(i32 %a) nounwind {
; RV32I-LABEL: test_call_dso_local:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: call dso_local_function
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-PIC-LABEL: test_call_dso_local:
; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp)
; RV32I-PIC-NEXT: call dso_local_function
; RV32I-PIC-NEXT: lw ra, 12(sp)
; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret
%1 = call i32 @dso_local_function(i32 %a)
ret i32 %1
}
define i32 @defined_function(i32 %a) nounwind {
; RV32I-LABEL: defined_function:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: ret
;
; RV32I-PIC-LABEL: defined_function:
; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi a0, a0, 1
; RV32I-PIC-NEXT: ret
%1 = add i32 %a, 1
ret i32 %1
}
@ -35,6 +75,15 @@ define i32 @test_call_defined(i32 %a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-PIC-LABEL: test_call_defined:
; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp)
; RV32I-PIC-NEXT: call defined_function@plt
; RV32I-PIC-NEXT: lw ra, 12(sp)
; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret
%1 = call i32 @defined_function(i32 %a)
ret i32 %1
}
@ -50,6 +99,17 @@ define i32 @test_call_indirect(i32 (i32)* %a, i32 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-PIC-LABEL: test_call_indirect:
; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp)
; RV32I-PIC-NEXT: mv a2, a0
; RV32I-PIC-NEXT: mv a0, a1
; RV32I-PIC-NEXT: jalr a2
; RV32I-PIC-NEXT: lw ra, 12(sp)
; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret
%1 = call i32 %a(i32 %b)
ret i32 %1
}
@ -62,6 +122,11 @@ define fastcc i32 @fastcc_function(i32 %a, i32 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
;
; RV32I-PIC-LABEL: fastcc_function:
; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: add a0, a0, a1
; RV32I-PIC-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@ -79,6 +144,19 @@ define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-PIC-LABEL: test_call_fastcc:
; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp)
; RV32I-PIC-NEXT: sw s0, 8(sp)
; RV32I-PIC-NEXT: mv s0, a0
; RV32I-PIC-NEXT: call fastcc_function@plt
; RV32I-PIC-NEXT: mv a0, s0
; RV32I-PIC-NEXT: lw s0, 8(sp)
; RV32I-PIC-NEXT: lw ra, 12(sp)
; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret
%1 = call fastcc i32 @fastcc_function(i32 %a, i32 %b)
ret i32 %a
}
@ -107,6 +185,28 @@ define i32 @test_call_external_many_args(i32 %a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-PIC-LABEL: test_call_external_many_args:
; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp)
; RV32I-PIC-NEXT: sw s0, 8(sp)
; RV32I-PIC-NEXT: mv s0, a0
; RV32I-PIC-NEXT: sw a0, 4(sp)
; RV32I-PIC-NEXT: sw a0, 0(sp)
; RV32I-PIC-NEXT: mv a1, a0
; RV32I-PIC-NEXT: mv a2, a0
; RV32I-PIC-NEXT: mv a3, a0
; RV32I-PIC-NEXT: mv a4, a0
; RV32I-PIC-NEXT: mv a5, a0
; RV32I-PIC-NEXT: mv a6, a0
; RV32I-PIC-NEXT: mv a7, a0
; RV32I-PIC-NEXT: call external_many_args@plt
; RV32I-PIC-NEXT: mv a0, s0
; RV32I-PIC-NEXT: lw s0, 8(sp)
; RV32I-PIC-NEXT: lw ra, 12(sp)
; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret
%1 = call i32 @external_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
ret i32 %a
@ -118,6 +218,12 @@ define i32 @defined_many_args(i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 %
; RV32I-NEXT: lw a0, 4(sp)
; RV32I-NEXT: addi a0, a0, 1
; RV32I-NEXT: ret
;
; RV32I-PIC-LABEL: defined_many_args:
; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: lw a0, 4(sp)
; RV32I-PIC-NEXT: addi a0, a0, 1
; RV32I-PIC-NEXT: ret
%added = add i32 %j, 1
ret i32 %added
}
@ -140,6 +246,24 @@ define i32 @test_call_defined_many_args(i32 %a) nounwind {
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32I-PIC-LABEL: test_call_defined_many_args:
; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp)
; RV32I-PIC-NEXT: sw a0, 4(sp)
; RV32I-PIC-NEXT: sw a0, 0(sp)
; RV32I-PIC-NEXT: mv a1, a0
; RV32I-PIC-NEXT: mv a2, a0
; RV32I-PIC-NEXT: mv a3, a0
; RV32I-PIC-NEXT: mv a4, a0
; RV32I-PIC-NEXT: mv a5, a0
; RV32I-PIC-NEXT: mv a6, a0
; RV32I-PIC-NEXT: mv a7, a0
; RV32I-PIC-NEXT: call defined_many_args@plt
; RV32I-PIC-NEXT: lw ra, 12(sp)
; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret
%1 = call i32 @defined_many_args(i32 %a, i32 %a, i32 %a, i32 %a, i32 %a,
i32 %a, i32 %a, i32 %a, i32 %a, i32 %a)
ret i32 %1