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[AMDGPU] Fix adjustWritemask subreg handling 

If we happen to extract a non-dword subreg that breaks the
logic of the function and it may shrink the dmask because
it does not recognize the use of a lane(s).

This bug is next to impossible to trigger with the current
lowering in the BE, but it breaks in one of my future patches.

Differential Revision: https://reviews.llvm.org/D93782
This commit is contained in:
Stanislav Mekhanoshin 2020-12-23 14:15:23 -08:00
parent be89d7460b
commit 747f67e034
1 changed files with 3 additions and 1 deletions
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4
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
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@ -10862,7 +10862,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
/// Helper function for adjustWritemask /// Helper function for adjustWritemask
static unsigned SubIdx2Lane(unsigned Idx) { static unsigned SubIdx2Lane(unsigned Idx) {
switch (Idx) { switch (Idx) {
default: return 0; default: return ~0u;
case AMDGPU::sub0: return 0; case AMDGPU::sub0: return 0;
case AMDGPU::sub1: return 1; case AMDGPU::sub1: return 1;
case AMDGPU::sub2: return 2; case AMDGPU::sub2: return 2;
@ -10922,6 +10922,8 @@ SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,
// in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
// set, etc. // set, etc.
Lane = SubIdx2Lane(I->getConstantOperandVal(1)); Lane = SubIdx2Lane(I->getConstantOperandVal(1));
if (Lane == ~0u)
return Node;
// Check if the use is for the TFE/LWE generated result at VGPRn+1. // Check if the use is for the TFE/LWE generated result at VGPRn+1.
if (UsesTFC && Lane == TFCLane) { if (UsesTFC && Lane == TFCLane) {