forked from OSchip/llvm-project
[AMDGPU] Fix adjustWritemask subreg handling
If we happen to extract a non-dword subreg that breaks the logic of the function and it may shrink the dmask because it does not recognize the use of a lane(s). This bug is next to impossible to trigger with the current lowering in the BE, but it breaks in one of my future patches. Differential Revision: https://reviews.llvm.org/D93782
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@ -10862,7 +10862,7 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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/// Helper function for adjustWritemask
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static unsigned SubIdx2Lane(unsigned Idx) {
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switch (Idx) {
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default: return 0;
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default: return ~0u;
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case AMDGPU::sub0: return 0;
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case AMDGPU::sub1: return 1;
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case AMDGPU::sub2: return 2;
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@ -10922,6 +10922,8 @@ SDNode *SITargetLowering::adjustWritemask(MachineSDNode *&Node,
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// in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
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// set, etc.
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Lane = SubIdx2Lane(I->getConstantOperandVal(1));
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if (Lane == ~0u)
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return Node;
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// Check if the use is for the TFE/LWE generated result at VGPRn+1.
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if (UsesTFC && Lane == TFCLane) {
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