forked from OSchip/llvm-project
[TargetLowering] add tests to show effect of setcc sub->shift; NFC
There's effectively no difference for the cases with variables. We just trade a sub for an add on those. But the case with a subtract from constant would require an extra move instruction on x86, so this looks like a reasonable generic combine. llvm-svn: 353619
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llvm
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@ -3075,7 +3075,6 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
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DAG.getConstant(0, dl, N0.getValueType()),
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Cond);
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// The shift is not valid if this is a bool (i1).
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// TODO: This transform needs evidence to justify its existence.
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if (N0.getNode()->hasOneUse() && OpVT.getScalarSizeInBits() != 1) {
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assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
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auto &DL = DAG.getDataLayout();
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@ -297,3 +297,41 @@ define i64 @sub_to_shift_to_add(i32 %x, i32 %y, i64 %s1, i64 %s2) {
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ret i64 %r
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}
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define <4 x float> @sub_to_shift_to_add_vec(<4 x i32> %x, <4 x i32> %y, <4 x float> %s1, <4 x float> %s2) {
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; SSE2-LABEL: sub_to_shift_to_add_vec:
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; SSE2: # %bb.0:
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; SSE2-NEXT: paddd %xmm1, %xmm1
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; SSE2-NEXT: pcmpeqd %xmm0, %xmm1
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; SSE2-NEXT: pand %xmm1, %xmm2
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; SSE2-NEXT: pandn %xmm3, %xmm1
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; SSE2-NEXT: por %xmm2, %xmm1
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; SSE2-NEXT: movdqa %xmm1, %xmm0
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; SSE2-NEXT: retq
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;
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; SSE41-LABEL: sub_to_shift_to_add_vec:
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; SSE41: # %bb.0:
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; SSE41-NEXT: paddd %xmm1, %xmm1
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; SSE41-NEXT: pcmpeqd %xmm1, %xmm0
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; SSE41-NEXT: blendvps %xmm0, %xmm2, %xmm3
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; SSE41-NEXT: movaps %xmm3, %xmm0
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; SSE41-NEXT: retq
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%sub = sub <4 x i32> %x, %y
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%cmp = icmp eq <4 x i32> %sub, %y
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%r = select <4 x i1> %cmp, <4 x float> %s1, <4 x float> %s2
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ret <4 x float> %r
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}
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define i64 @sub_constant_to_shift_to_add(i32 %x, i64 %s1, i64 %s2) {
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; CHECK-LABEL: sub_constant_to_shift_to_add:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq %rsi, %rax
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; CHECK-NEXT: addl %edi, %edi
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; CHECK-NEXT: cmpl $42, %edi
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; CHECK-NEXT: cmovneq %rdx, %rax
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; CHECK-NEXT: retq
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%sub = sub i32 42, %x
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%cmp = icmp eq i32 %sub, %x
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%r = select i1 %cmp, i64 %s1, i64 %s2
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ret i64 %r
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}
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