forked from OSchip/llvm-project
Remove more vector_shuffle patterns for unpack. These should be target specific nodes when they get to isel.
llvm-svn: 150363
This commit is contained in:
Craig Topper
parent
6d471c9e49
commit
74650add0e
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@ -2265,11 +2265,6 @@ let Predicates = [HasAVX] in {
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(VSHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
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def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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(VSHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
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// vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
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// fall back to this for SSE1)
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def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
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(VSHUFPSrri VR128:$src2, VR128:$src1,
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(SHUFFLE_get_shuf_imm VR128:$src3))>;
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def : Pat<(v2i64 (X86Shufp VR128:$src1,
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(memopv2i64 addr:$src2), (i8 imm:$imm))),
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@ -2297,11 +2292,6 @@ let Predicates = [HasSSE1] in {
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(SHUFPSrmi VR128:$src1, addr:$src2, imm:$imm)>;
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def : Pat<(v4i32 (X86Shufp VR128:$src1, VR128:$src2, (i8 imm:$imm))),
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(SHUFPSrri VR128:$src1, VR128:$src2, imm:$imm)>;
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// vector_shuffle v1, v2 <4, 5, 2, 3> using SHUFPSrri (we prefer movsd, but
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// fall back to this for SSE1)
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def : Pat<(v4f32 (movlp:$src3 VR128:$src1, (v4f32 VR128:$src2))),
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(SHUFPSrri VR128:$src2, VR128:$src1,
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(SHUFFLE_get_shuf_imm VR128:$src3))>;
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}
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let Predicates = [HasSSE2] in {
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@ -2318,7 +2308,7 @@ let Predicates = [HasSSE2] in {
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//===----------------------------------------------------------------------===//
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/// sse12_unpack_interleave - sse 1 & 2 unpack and interleave
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multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
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multiclass sse12_unpack_interleave<bits<8> opc, SDNode OpNode, ValueType vt,
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PatFrag mem_frag, RegisterClass RC,
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X86MemOperand x86memop, string asm,
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Domain d> {
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@ -2335,86 +2325,48 @@ multiclass sse12_unpack_interleave<bits<8> opc, PatFrag OpNode, ValueType vt,
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IIC_DEFAULT, d>;
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}
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let AddedComplexity = 10 in {
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defm VUNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
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defm VUNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
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VR128, f128mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, TB, VEX_4V;
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defm VUNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
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defm VUNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
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VR128, f128mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, TB, OpSize, VEX_4V;
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defm VUNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
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defm VUNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
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VR128, f128mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, TB, VEX_4V;
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defm VUNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
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defm VUNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
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VR128, f128mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, TB, OpSize, VEX_4V;
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defm VUNPCKHPSY: sse12_unpack_interleave<0x15, unpckh, v8f32, memopv8f32,
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defm VUNPCKHPSY: sse12_unpack_interleave<0x15, X86Unpckh, v8f32, memopv8f32,
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VR256, f256mem, "unpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, TB, VEX_4V;
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defm VUNPCKHPDY: sse12_unpack_interleave<0x15, unpckh, v4f64, memopv4f64,
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defm VUNPCKHPDY: sse12_unpack_interleave<0x15, X86Unpckh, v4f64, memopv4f64,
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VR256, f256mem, "unpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, TB, OpSize, VEX_4V;
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defm VUNPCKLPSY: sse12_unpack_interleave<0x14, unpckl, v8f32, memopv8f32,
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defm VUNPCKLPSY: sse12_unpack_interleave<0x14, X86Unpckl, v8f32, memopv8f32,
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VR256, f256mem, "unpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedSingle>, TB, VEX_4V;
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defm VUNPCKLPDY: sse12_unpack_interleave<0x14, unpckl, v4f64, memopv4f64,
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defm VUNPCKLPDY: sse12_unpack_interleave<0x14, X86Unpckl, v4f64, memopv4f64,
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VR256, f256mem, "unpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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SSEPackedDouble>, TB, OpSize, VEX_4V;
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let Constraints = "$src1 = $dst" in {
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defm UNPCKHPS: sse12_unpack_interleave<0x15, unpckh, v4f32, memopv4f32,
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defm UNPCKHPS: sse12_unpack_interleave<0x15, X86Unpckh, v4f32, memopv4f32,
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VR128, f128mem, "unpckhps\t{$src2, $dst|$dst, $src2}",
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SSEPackedSingle>, TB;
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defm UNPCKHPD: sse12_unpack_interleave<0x15, unpckh, v2f64, memopv2f64,
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defm UNPCKHPD: sse12_unpack_interleave<0x15, X86Unpckh, v2f64, memopv2f64,
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VR128, f128mem, "unpckhpd\t{$src2, $dst|$dst, $src2}",
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SSEPackedDouble>, TB, OpSize;
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defm UNPCKLPS: sse12_unpack_interleave<0x14, unpckl, v4f32, memopv4f32,
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defm UNPCKLPS: sse12_unpack_interleave<0x14, X86Unpckl, v4f32, memopv4f32,
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VR128, f128mem, "unpcklps\t{$src2, $dst|$dst, $src2}",
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SSEPackedSingle>, TB;
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defm UNPCKLPD: sse12_unpack_interleave<0x14, unpckl, v2f64, memopv2f64,
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defm UNPCKLPD: sse12_unpack_interleave<0x14, X86Unpckl, v2f64, memopv2f64,
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VR128, f128mem, "unpcklpd\t{$src2, $dst|$dst, $src2}",
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SSEPackedDouble>, TB, OpSize;
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} // Constraints = "$src1 = $dst"
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} // AddedComplexity
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let Predicates = [HasAVX], AddedComplexity = 1 in {
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def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))),
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(VUNPCKLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)),
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(VUNPCKLPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))),
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(VUNPCKHPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)),
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(VUNPCKHPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v8f32 (X86Unpckl VR256:$src1, (memopv8f32 addr:$src2))),
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(VUNPCKLPSYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8f32 (X86Unpckl VR256:$src1, VR256:$src2)),
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(VUNPCKLPSYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v8f32 (X86Unpckh VR256:$src1, (memopv8f32 addr:$src2))),
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(VUNPCKHPSYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v8f32 (X86Unpckh VR256:$src1, VR256:$src2)),
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(VUNPCKHPSYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))),
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(VUNPCKLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)),
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(VUNPCKLPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))),
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(VUNPCKHPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)),
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(VUNPCKHPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4f64 (X86Unpckl VR256:$src1, (memopv4f64 addr:$src2))),
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(VUNPCKLPDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4f64 (X86Unpckl VR256:$src1, VR256:$src2)),
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(VUNPCKLPDYrr VR256:$src1, VR256:$src2)>;
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def : Pat<(v4f64 (X86Unpckh VR256:$src1, (memopv4f64 addr:$src2))),
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(VUNPCKHPDYrm VR256:$src1, addr:$src2)>;
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def : Pat<(v4f64 (X86Unpckh VR256:$src1, VR256:$src2)),
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(VUNPCKHPDYrr VR256:$src1, VR256:$src2)>;
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// FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
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// problem is during lowering, where it's not possible to recognize the load
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// fold cause it has two uses through a bitcast. One use disappears at isel
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@ -2423,27 +2375,7 @@ let Predicates = [HasAVX], AddedComplexity = 1 in {
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(VUNPCKLPDrr VR128:$src, VR128:$src)>;
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}
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let Predicates = [HasSSE1] in {
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def : Pat<(v4f32 (X86Unpckl VR128:$src1, (memopv4f32 addr:$src2))),
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(UNPCKLPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpckl VR128:$src1, VR128:$src2)),
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(UNPCKLPSrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v4f32 (X86Unpckh VR128:$src1, (memopv4f32 addr:$src2))),
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(UNPCKHPSrm VR128:$src1, addr:$src2)>;
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def : Pat<(v4f32 (X86Unpckh VR128:$src1, VR128:$src2)),
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(UNPCKHPSrr VR128:$src1, VR128:$src2)>;
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}
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let Predicates = [HasSSE2] in {
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def : Pat<(v2f64 (X86Unpckl VR128:$src1, (memopv2f64 addr:$src2))),
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(UNPCKLPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Unpckl VR128:$src1, VR128:$src2)),
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(UNPCKLPDrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2f64 (X86Unpckh VR128:$src1, (memopv2f64 addr:$src2))),
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(UNPCKHPDrm VR128:$src1, addr:$src2)>;
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def : Pat<(v2f64 (X86Unpckh VR128:$src1, VR128:$src2)),
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(UNPCKHPDrr VR128:$src1, VR128:$src2)>;
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// FIXME: Instead of X86Movddup, there should be a X86Unpckl here, the
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// problem is during lowering, where it's not possible to recognize the load
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// fold cause it has two uses through a bitcast. One use disappears at isel
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