[RISCV] Add '32bit' feature to rv32 only builtins.

The backend now has a 32bit feature as part of the recent mtune
patch. We can now use that make our rv32-only builtin error checking
work the same way as rv64-only errors.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D132192
This commit is contained in:
Craig Topper 2022-09-06 14:45:17 -07:00
parent f3502afe85
commit 7440e2274f
5 changed files with 30 additions and 40 deletions
clang
include/clang/Basic
lib
Basic/Targets
Sema
test
CodeGen/RISCV/rvb-intrinsics
Driver

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@ -77,12 +77,12 @@ TARGET_BUILTIN(__builtin_riscv_fsr_64, "WiWiWiWi", "nc", "experimental-zbt,64bit
// Zbkb extension
TARGET_BUILTIN(__builtin_riscv_brev8, "LiLi", "nc", "zbkb")
TARGET_BUILTIN(__builtin_riscv_zip_32, "ZiZi", "nc", "zbkb")
TARGET_BUILTIN(__builtin_riscv_unzip_32, "ZiZi", "nc", "zbkb")
TARGET_BUILTIN(__builtin_riscv_zip_32, "ZiZi", "nc", "zbkb,32bit")
TARGET_BUILTIN(__builtin_riscv_unzip_32, "ZiZi", "nc", "zbkb,32bit")
// Zknd extension
TARGET_BUILTIN(__builtin_riscv_aes32dsi_32, "ZiZiZiIUc", "nc", "zknd")
TARGET_BUILTIN(__builtin_riscv_aes32dsmi_32, "ZiZiZiIUc", "nc", "zknd")
TARGET_BUILTIN(__builtin_riscv_aes32dsi_32, "ZiZiZiIUc", "nc", "zknd,32bit")
TARGET_BUILTIN(__builtin_riscv_aes32dsmi_32, "ZiZiZiIUc", "nc", "zknd,32bit")
TARGET_BUILTIN(__builtin_riscv_aes64ds_64, "WiWiWi", "nc", "zknd,64bit")
TARGET_BUILTIN(__builtin_riscv_aes64dsm_64, "WiWiWi", "nc", "zknd,64bit")
TARGET_BUILTIN(__builtin_riscv_aes64im_64, "WiWi", "nc", "zknd,64bit")
@ -92,8 +92,8 @@ TARGET_BUILTIN(__builtin_riscv_aes64ks1i_64, "WiWiIUi", "nc", "zknd|zkne,64bit")
TARGET_BUILTIN(__builtin_riscv_aes64ks2_64, "WiWiWi", "nc", "zknd|zkne,64bit")
// Zkne extension
TARGET_BUILTIN(__builtin_riscv_aes32esi_32, "ZiZiZiIUc", "nc", "zkne")
TARGET_BUILTIN(__builtin_riscv_aes32esmi_32, "ZiZiZiIUc", "nc", "zkne")
TARGET_BUILTIN(__builtin_riscv_aes32esi_32, "ZiZiZiIUc", "nc", "zkne,32bit")
TARGET_BUILTIN(__builtin_riscv_aes32esmi_32, "ZiZiZiIUc", "nc", "zkne,32bit")
TARGET_BUILTIN(__builtin_riscv_aes64es_64, "WiWiWi", "nc", "zkne,64bit")
TARGET_BUILTIN(__builtin_riscv_aes64esm_64, "WiWiWi", "nc", "zkne,64bit")
@ -103,12 +103,12 @@ TARGET_BUILTIN(__builtin_riscv_sha256sig1, "LiLi", "nc", "zknh")
TARGET_BUILTIN(__builtin_riscv_sha256sum0, "LiLi", "nc", "zknh")
TARGET_BUILTIN(__builtin_riscv_sha256sum1, "LiLi", "nc", "zknh")
TARGET_BUILTIN(__builtin_riscv_sha512sig0h_32, "ZiZiZi", "nc", "zknh")
TARGET_BUILTIN(__builtin_riscv_sha512sig0l_32, "ZiZiZi", "nc", "zknh")
TARGET_BUILTIN(__builtin_riscv_sha512sig1h_32, "ZiZiZi", "nc", "zknh")
TARGET_BUILTIN(__builtin_riscv_sha512sig1l_32, "ZiZiZi", "nc", "zknh")
TARGET_BUILTIN(__builtin_riscv_sha512sum0r_32, "ZiZiZi", "nc", "zknh")
TARGET_BUILTIN(__builtin_riscv_sha512sum1r_32, "ZiZiZi", "nc", "zknh")
TARGET_BUILTIN(__builtin_riscv_sha512sig0h_32, "ZiZiZi", "nc", "zknh,32bit")
TARGET_BUILTIN(__builtin_riscv_sha512sig0l_32, "ZiZiZi", "nc", "zknh,32bit")
TARGET_BUILTIN(__builtin_riscv_sha512sig1h_32, "ZiZiZi", "nc", "zknh,32bit")
TARGET_BUILTIN(__builtin_riscv_sha512sig1l_32, "ZiZiZi", "nc", "zknh,32bit")
TARGET_BUILTIN(__builtin_riscv_sha512sum0r_32, "ZiZiZi", "nc", "zknh,32bit")
TARGET_BUILTIN(__builtin_riscv_sha512sum1r_32, "ZiZiZi", "nc", "zknh,32bit")
TARGET_BUILTIN(__builtin_riscv_sha512sig0_64, "WiWi", "nc", "zknh,64bit")
TARGET_BUILTIN(__builtin_riscv_sha512sig1_64, "WiWi", "nc", "zknh,64bit")
TARGET_BUILTIN(__builtin_riscv_sha512sum0_64, "WiWi", "nc", "zknh,64bit")

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@ -221,6 +221,8 @@ bool RISCVTargetInfo::initFeatureMap(
if (getTriple().getArch() == llvm::Triple::riscv64) {
Features["64bit"] = true;
XLen = 64;
} else {
Features["32bit"] = true;
}
auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeaturesVec);
@ -251,6 +253,7 @@ bool RISCVTargetInfo::hasFeature(StringRef Feature) const {
.Case("riscv", true)
.Case("riscv32", !Is64Bit)
.Case("riscv64", Is64Bit)
.Case("32bit", !Is64Bit)
.Case("64bit", Is64Bit)
.Default(None);
if (Result)

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@ -4324,27 +4324,6 @@ bool Sema::CheckRISCVLMUL(CallExpr *TheCall, unsigned ArgNum) {
<< Arg->getSourceRange();
}
static bool isRISCV32Builtin(unsigned BuiltinID) {
// These builtins only work on riscv32 targets.
switch (BuiltinID) {
case RISCV::BI__builtin_riscv_zip_32:
case RISCV::BI__builtin_riscv_unzip_32:
case RISCV::BI__builtin_riscv_aes32dsi_32:
case RISCV::BI__builtin_riscv_aes32dsmi_32:
case RISCV::BI__builtin_riscv_aes32esi_32:
case RISCV::BI__builtin_riscv_aes32esmi_32:
case RISCV::BI__builtin_riscv_sha512sig0h_32:
case RISCV::BI__builtin_riscv_sha512sig0l_32:
case RISCV::BI__builtin_riscv_sha512sig1h_32:
case RISCV::BI__builtin_riscv_sha512sig1l_32:
case RISCV::BI__builtin_riscv_sha512sum0r_32:
case RISCV::BI__builtin_riscv_sha512sum1r_32:
return true;
}
return false;
}
bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
unsigned BuiltinID,
CallExpr *TheCall) {
@ -4355,12 +4334,6 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
StringRef Features = Context.BuiltinInfo.getRequiredFeatures(BuiltinID);
Features.split(ReqFeatures, ',');
// Check for 32-bit only builtins on a 64-bit target.
const llvm::Triple &TT = TI.getTriple();
if (TT.getArch() != llvm::Triple::riscv32 && isRISCV32Builtin(BuiltinID))
return Diag(TheCall->getCallee()->getBeginLoc(),
diag::err_32_bit_builtin_64_bit_tgt);
// Check if each required feature is included
for (StringRef F : ReqFeatures) {
SmallVector<StringRef> ReqOpFeatures;
@ -4380,6 +4353,8 @@ bool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
// the diagnostic.
if (OF == "64bit")
OF = "RV64";
if (OF == "32bit")
OF = "RV32";
// Convert features like "zbr" and "experimental-zbr" to "Zbr".
OF.consume_front("experimental-");

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@ -0,0 +1,12 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple riscv64 -target-feature +zbkb -verify %s -o -
int zip(int rs1)
{
return __builtin_riscv_zip_32(rs1); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'RV32'}}
}
int unzip(int rs1)
{
return __builtin_riscv_unzip_32(rs1); // expected-error {{builtin requires at least one of the following extensions support to be enabled : 'RV32'}}
}

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@ -1,7 +1,7 @@
// RUN: %clang --target=riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
// RUN: %clang --target=riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64
// RV32: "target-features"="+a,+c,+m,+relax,-save-restore"
// RV32: "target-features"="+32bit,+a,+c,+m,+relax,-save-restore"
// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
// Dummy function