forked from OSchip/llvm-project
[SelectionDAG] https://reviews.llvm.org/D48278
D48278 Allow to reduce redundant shift masks. For example: x1 = x & 0xAB00 x2 = (x >> 8) & 0xAB can be reduced to: x1 = x & 0xAB00 x2 = x1 >> 8 It only allows folding when the masks and shift values are constants. llvm-svn: 336426
This commit is contained in:
Diogo N. Sampaio
parent
b370615451
commit
742bf1a255
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@ -447,6 +447,7 @@ namespace {
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SDNode *MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL);
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SDValue MatchLoadCombine(SDNode *N);
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SDValue ReduceLoadWidth(SDNode *N);
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SDValue foldRedundantShiftedMasks(SDNode *N);
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SDValue ReduceLoadOpStoreWidth(SDNode *N);
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SDValue splitMergedValStore(StoreSDNode *ST);
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SDValue TransformFPLoadStorePair(SDNode *N);
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@ -4378,6 +4379,9 @@ SDValue DAGCombiner::visitAND(SDNode *N) {
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}
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}
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if (SDValue R = foldRedundantShiftedMasks(N))
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return R;
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if (Level >= AfterLegalizeTypes) {
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// Attempt to propagate the AND back up to the leaves which, if they're
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// loads, can be combined to narrow loads and the AND node can be removed.
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@ -5944,6 +5948,108 @@ SDValue DAGCombiner::visitRotate(SDNode *N) {
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return SDValue();
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}
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// fold expressions x1 and x2 alike:
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// x1 = ( and, x, 0x00FF )
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// x2 = (( shl x, 8 ) and 0xFF00 )
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// into
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// x2 = shl x1, 8 ; reuse the computation of x1
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SDValue DAGCombiner::foldRedundantShiftedMasks(SDNode *AND) {
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if (!AND)
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return SDValue();
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const SDValue &SHIFT = AND->getOperand(0);
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if ((SHIFT.getNumOperands() != 2) || (!SHIFT.hasOneUse()))
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return SDValue();
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const ConstantSDNode *ShiftAmount =
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dyn_cast<ConstantSDNode>(SHIFT.getOperand(1));
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if (!ShiftAmount)
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return SDValue();
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const ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(AND->getOperand(1));
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if (!Mask)
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return SDValue();
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SDValue MASKED = SHIFT.getOperand(0);
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const auto &MaskedValue = dyn_cast<SDNode>(MASKED);
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unsigned N0Opcode = SHIFT.getOpcode();
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for (SDNode *OtherUser : MaskedValue->uses()) {
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if ((&(*OtherUser) == ShiftAmount) || (OtherUser->getOpcode() != ISD::AND))
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continue;
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ConstantSDNode *OtherMask =
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dyn_cast<ConstantSDNode>(OtherUser->getOperand(1));
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if (!OtherMask)
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continue;
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bool CanReduce = false;
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const APInt &MaskValue = Mask->getAPIntValue();
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const APInt &ShiftValue = ShiftAmount->getAPIntValue();
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const APInt &OtherMaskValue = OtherMask->getAPIntValue();
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KnownBits MaskedValueBits;
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DAG.computeKnownBits(MASKED, MaskedValueBits);
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KnownBits ShiftedValueBits;
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DAG.computeKnownBits(SHIFT, ShiftedValueBits);
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const APInt EffectiveOtherMask = OtherMaskValue & ~MaskedValueBits.Zero;
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const APInt EffectiveMask = MaskValue & ~ShiftedValueBits.Zero;
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LLVM_DEBUG(
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dbgs() << "\tValue being masked and shift-masked: "; MASKED.dump();
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dbgs() << "\t\tValue zero bits: 0x"
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<< MaskedValueBits.Zero.toString(16, false)
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<< "\n\n\t\tApplied mask: 0x"
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<< OtherMaskValue.toString(16, false) << " : ";
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OtherUser->dump();
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dbgs() << "\t\tEffective mask: 0x"
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<< EffectiveOtherMask.toString(16, false)
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<< "\n\n\tShifted by: " << ShiftValue.getZExtValue() << " : ";
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SHIFT.dump(); dbgs() << "\t\tAnd masked by: 0x"
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<< MaskValue.toString(16, false) << " : ";
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AND->dump(); dbgs() << "\t\tEffective mask to shifted value: 0x"
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<< EffectiveMask.toString(16, false) << '\n';);
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switch (N0Opcode) {
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case ISD::SHL:
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CanReduce = (EffectiveOtherMask.shl(EffectiveMask) == EffectiveMask) ||
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(EffectiveMask.lshr(ShiftValue) == EffectiveOtherMask);
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break;
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case ISD::SRA:
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if (!MaskedValueBits.Zero.isSignBitSet()) {
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CanReduce = (EffectiveOtherMask.ashr(ShiftValue) == EffectiveMask);
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break;
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} else // Same as SRL
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N0Opcode = ISD::SRL;
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LLVM_FALLTHROUGH
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/* fall-through */
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case ISD::SRL:
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CanReduce = (EffectiveOtherMask.lshr(ShiftValue) == EffectiveMask) ||
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(EffectiveMask.shl(ShiftValue) == EffectiveOtherMask);
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break;
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case ISD::ROTR:
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CanReduce = (EffectiveOtherMask.rotr(ShiftValue) == EffectiveMask);
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break;
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default:
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return SDValue();
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}
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if (CanReduce) {
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LLVM_DEBUG(dbgs() << "\tCan just shift the masked value\n");
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SDValue ShiftTheAND(OtherUser, 0);
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const SDLoc DL(SHIFT);
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EVT VT = AND->getValueType(0);
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SDValue NewShift =
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DAG.getNode(N0Opcode, DL, VT, ShiftTheAND, SHIFT.getOperand(1));
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AddToWorklist(OtherUser);
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return NewShift;
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}
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}
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return SDValue();
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}
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SDValue DAGCombiner::visitSHL(SDNode *N) {
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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@ -0,0 +1,95 @@
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; RUN: llc -march=aarch64 < %s | FileCheck %s -check-prefix=A64
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define i32 @ror(i32 %a) {
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entry:
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%m2 = and i32 %a, 3855
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%shl = shl i32 %a, 24
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%shr = lshr i32 %a, 8
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%or = or i32 %shl, %shr
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%m1 = and i32 %or, 251658255
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%or2 = or i32 %m1, %m2
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ret i32 %or2
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}
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; A64-LABEL: ror
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; A64: mov [[R1:w[0-9]]], #3855
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; A64-NEXT: and [[R2:w[0-9]]], w0, [[R1]]
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; A64-NEXT: orr [[R3:w[0-9]]], [[R1]], [[R1]], ror #8
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define i32 @shl(i16 %a) {
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entry:
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%0 = sext i16 %a to i32
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%1 = and i32 %0, 172
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%2 = shl i32 %0, 8
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%3 = and i32 %2, 44032
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%4 = or i32 %1, %3
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ret i32 %4
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}
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; A64-LABEL:shl:
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; A64: mov w8, #172
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; A64-NEXT: and w8, w0, w8
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; A64-NEXT: orr w0, w8, w8, lsl #8
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define i32 @lshr(i16 %a) {
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entry:
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%0 = sext i16 %a to i32
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%1 = and i32 %0, 44032
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%2 = lshr i32 %0, 8
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%3 = and i32 %2, 172
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%4 = or i32 %1, %3
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ret i32 %4
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}
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; A64-LABEL:lshr:
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; A64: mov w8, #44032
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; A64-NEXT: and w8, w0, w8
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; A64-NEXT: orr w0, w8, w8, lsr #8
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define i32 @ashr(i16 %a) {
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entry:
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%0 = sext i16 %a to i32
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%1 = and i32 %0, 44032
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%2 = ashr i32 %0, 8
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%3 = and i32 %2, 172
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%4 = or i32 %1, %3
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ret i32 %4
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}
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; A64-LABEL:ashr:
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; A64: mov w8, #44032
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; A64-NEXT: and w8, w0, w8
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; A64-NEXT: orr w0, w8, w8, lsr #8
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define i32 @shl_nogood(i16 %a) {
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entry:
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%0 = sext i16 %a to i32
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%1 = and i32 %0, 172
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%2 = shl i32 %0, %1
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%3 = and i32 %2, 44032
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%4 = or i32 %1, %3
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ret i32 %4
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}
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define i32 @shl_nogood2(i16 %a) {
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entry:
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%0 = sext i16 %a to i32
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%1 = and i32 %0, 172
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%2 = shl i32 %0, 8
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%3 = and i32 %2, %0
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%4 = or i32 %1, %3
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ret i32 %4
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}
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; A64-LABEL:shl_nogood: // @shl_nogood
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; A64: sxth w8, w0
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; A64-NEXT: mov w9, #172
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; A64-NEXT: and w9, w8, w9
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; A64-NEXT: lsl w8, w8, w9
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; A64-NEXT: mov w10, #44032
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; A64-NEXT: and w8, w8, w10
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; A64-NEXT: orr w0, w9, w8
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; A64-NEXT: ret
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; A64-LABEL:shl_nogood2: // @shl_nogood2
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; A64: sxth w8, w0
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; A64-NEXT: mov w9, #172
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; A64-NEXT: and w9, w8, w9
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; A64-NEXT: and w8, w8, w8, lsl #8
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; A64-NEXT: orr w0, w9, w8
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; A64-NEXT: ret
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@ -0,0 +1,98 @@
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "armv4t-arm-none-eabi"
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; RUN: llc -march=arm < %s | FileCheck %s -check-prefix=ARM
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define i32 @ror(i32 %a) {
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entry:
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%m2 = and i32 %a, 3855
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%shl = shl i32 %a, 24
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%shr = lshr i32 %a, 8
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%or = or i32 %shl, %shr
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%m1 = and i32 %or, 251658255
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%or2 = or i32 %m1, %m2
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ret i32 %or2
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}
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; ARM-LABEL: ror
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; ARM: mov [[R1:r[0-9]]], #15
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; ARM-NEXT: orr [[R2:r[0-9]]], [[R1]], #3840
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; ARM-NEXT: and [[R3:r[0-9]]], r0, [[R1]]
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; ARM-NEXT: orr [[R4:r[0-9]]], [[R3]], [[R3]], ror #8
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; ARM-NEXT: mov pc, lr
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define i32 @shl(i16 %a) {
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entry:
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%0 = sext i16 %a to i32
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%1 = and i32 %0, 172
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%2 = shl i32 %0, 8
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%3 = and i32 %2, 44032
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%4 = or i32 %1, %3
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ret i32 %4
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}
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; ARM-LABEL: shl:
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; ARM: and r0, r0, #172
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; ARM-NEXT: orr r0, r0, r0, lsl #8
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define i32 @lshr(i16 %a) {
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entry:
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%0 = sext i16 %a to i32
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%1 = and i32 %0, 44032
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%2 = lshr i32 %0, 8
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%3 = and i32 %2, 172
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%4 = or i32 %1, %3
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ret i32 %4
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}
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; ARM-LABEL: lshr:
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; ARM: and r0, r0, #44032
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; ARM-NEXT: orr r0, r0, r0, lsr #8
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define i32 @ashr(i16 %a) {
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entry:
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%0 = sext i16 %a to i32
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%1 = and i32 %0, 44032
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%2 = ashr i32 %0, 8
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%3 = and i32 %2, 172
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%4 = or i32 %1, %3
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ret i32 %4
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}
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; ARM-LABEL: ashr:
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; ARM: and r0, r0, #44032
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; ARM-NEXT: orr r0, r0, r0, lsr #8
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define i32 @shl_nogood(i16 %a) {
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entry:
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%0 = sext i16 %a to i32
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%1 = and i32 %0, 172
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%2 = shl i32 %0, %1
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%3 = and i32 %2, 44032
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%4 = or i32 %1, %3
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ret i32 %4
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}
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define i32 @shl_nogood2(i16 %a) {
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entry:
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%0 = sext i16 %a to i32
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%1 = and i32 %0, 172
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%2 = shl i32 %0, 8
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%3 = and i32 %2, %0
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%4 = or i32 %1, %3
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ret i32 %4
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}
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; ARM-LABEL:shl_nogood:
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; ARM: lsl r0, r0, #16
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; ARM-NEXT: mov r1, #172
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; ARM-NEXT: and r1, r1, r0, asr #16
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; ARM-NEXT: asr r0, r0, #16
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; ARM-NEXT: mov r2, #44032
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; ARM-NEXT: and r0, r2, r0, lsl r1
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; ARM-NEXT: orr r0, r1, r0
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; ARM-NEXT: mov pc, lr
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; ARM-LABEL:shl_nogood2:
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; ARM: lsl r0, r0, #16
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; ARM-NEXT: mov r1, #172
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; ARM-NEXT: asr r2, r0, #16
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; ARM-NEXT: and r1, r1, r0, asr #16
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; ARM-NEXT: lsl r2, r2, #8
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; ARM-NEXT: and r0, r2, r0, asr #16
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; ARM-NEXT: orr r0, r1, r0
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; ARM-NEXT: mov pc, lr
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@ -29,18 +29,18 @@ define void @foo() local_unnamed_addr {
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; X86-NEXT: .cfi_offset %edi, -16
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; X86-NEXT: .cfi_offset %ebx, -12
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; X86-NEXT: .cfi_offset %ebp, -8
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; X86-NEXT: movl obj, %edx
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; X86-NEXT: movsbl var_27, %eax
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; X86-NEXT: movzwl var_2, %esi
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; X86-NEXT: movl var_310, %ecx
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; X86-NEXT: imull %eax, %ecx
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; X86-NEXT: addl var_24, %ecx
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; X86-NEXT: andl $4194303, %edx # imm = 0x3FFFFF
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; X86-NEXT: leal (%edx,%edx), %ebx
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; X86-NEXT: subl %eax, %ebx
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; X86-NEXT: movl %ebx, %edi
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; X86-NEXT: subl %esi, %edi
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; X86-NEXT: imull %edi, %ecx
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; X86-NEXT: movl $4194303, %edi # imm = 0x3FFFFF
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; X86-NEXT: andl obj, %edi
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; X86-NEXT: leal (%edi,%edi), %edx
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; X86-NEXT: subl %eax, %edx
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; X86-NEXT: movl %edx, %ebx
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; X86-NEXT: subl %esi, %ebx
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; X86-NEXT: imull %ebx, %ecx
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; X86-NEXT: addl $-1437483407, %ecx # imm = 0xAA51BE71
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; X86-NEXT: movl $9, %esi
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; X86-NEXT: xorl %ebp, %ebp
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@ -50,12 +50,12 @@ define void @foo() local_unnamed_addr {
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; X86-NEXT: cmovnel %esi, %ebp
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; X86-NEXT: movl $0, %ecx
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; X86-NEXT: cmovnel %ecx, %esi
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; X86-NEXT: cmpl %edx, %edi
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; X86-NEXT: cmpl %edi, %ebx
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; X86-NEXT: movl %ebp, var_50+4
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; X86-NEXT: movl %esi, var_50
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; X86-NEXT: setge var_205
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; X86-NEXT: imull %eax, %ebx
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; X86-NEXT: movb %bl, var_218
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; X86-NEXT: imull %eax, %edx
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; X86-NEXT: movb %dl, var_218
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; X86-NEXT: popl %esi
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; X86-NEXT: .cfi_def_cfa_offset 16
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; X86-NEXT: popl %edi
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@ -68,24 +68,24 @@ define void @foo() local_unnamed_addr {
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;
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; X64-LABEL: foo:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movl {{.*}}(%rip), %eax
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; X64-NEXT: movsbl {{.*}}(%rip), %r9d
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; X64-NEXT: movzwl {{.*}}(%rip), %r8d
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; X64-NEXT: movl {{.*}}(%rip), %ecx
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; X64-NEXT: imull %r9d, %ecx
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; X64-NEXT: addl {{.*}}(%rip), %ecx
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; X64-NEXT: andl $4194303, %eax # imm = 0x3FFFFF
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; X64-NEXT: leal (%rax,%rax), %edi
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; X64-NEXT: movl $4194303, %esi
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; X64-NEXT: andl obj(%rip), %esi
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; X64-NEXT: leal (%rsi,%rsi), %edi
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; X64-NEXT: subl %r9d, %edi
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; X64-NEXT: movl %edi, %esi
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; X64-NEXT: subl %r8d, %esi
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; X64-NEXT: imull %esi, %ecx
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; X64-NEXT: movl %edi, %edx
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; X64-NEXT: subl %r8d, %edx
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; X64-NEXT: imull %edx, %ecx
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; X64-NEXT: addl $-1437483407, %ecx # imm = 0xAA51BE71
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; X64-NEXT: movl $9, %edx
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; X64-NEXT: movl $9, %eax
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; X64-NEXT: # kill: def $cl killed $cl killed $ecx
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; X64-NEXT: shlq %cl, %rdx
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; X64-NEXT: movq %rdx, {{.*}}(%rip)
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; X64-NEXT: cmpl %eax, %esi
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; X64-NEXT: shlq %cl, %rax
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; X64-NEXT: movq %rax, {{.*}}(%rip)
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; X64-NEXT: cmpl %esi, %edx
|
||||
; X64-NEXT: setge {{.*}}(%rip)
|
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; X64-NEXT: imull %r9d, %edi
|
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; X64-NEXT: movb %dil, {{.*}}(%rip)
|
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|
|
|
|||
Loading…
Reference in New Issue