forked from OSchip/llvm-project
Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 multiply instructions.
llvm-svn: 142737
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52340ac5f8
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@ -86,7 +86,7 @@ let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
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"mul{l}\t$src",
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[]>; // EAX,EDX = EAX*[mem32]
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
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"mul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
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}
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@ -101,7 +101,7 @@ def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", []>,
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", []>;
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// EAX,EDX = EAX*GR32
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", []>;
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// RAX,RDX = RAX*GR64
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@ -115,7 +115,7 @@ def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
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"imul{l}\t$src", []>; // EAX,EDX = EAX*[mem32]
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src),
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"imul{q}\t$src", []>; // RAX,RDX = RAX*[mem64]
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}
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@ -285,8 +285,8 @@ def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
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def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
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"idiv{q}\t$src", []>;
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let mayLoad = 1, mayLoad = 1 in {
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let mayLoad = 1 in {
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let Defs = [AL,EFLAGS,AX], Uses = [AX] in
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def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
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"idiv{b}\t$src", []>;
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