forked from OSchip/llvm-project
[mips][microMIPS] Implement CodeGen support for ADDIUS5 instruction.
Differential Revision: http://reviews.llvm.org/D5799 llvm-svn: 222351
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@ -31,6 +31,8 @@ def uimm4_andi : Operand<i32> {
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let EncoderMethod = "getUImm4AndValue";
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}
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def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>;
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def immZExtAndi16 : ImmLeaf<i32,
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[{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 ||
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Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 ||
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@ -161,7 +163,6 @@ class AddImmUS5<string opstr, RegisterOperand RO> :
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MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
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!strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
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let Constraints = "$rd = $dst";
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let isCommutable = 1;
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}
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class AddImmUR1SP<string opstr, RegisterOperand RO> :
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@ -527,6 +528,11 @@ let Predicates = [InMicroMips] in {
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// MicroMips arbitrary patterns that map to one or more instructions
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//===----------------------------------------------------------------------===//
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def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm),
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(ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>;
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def : MipsPat<(add GPR32:$src, immSExt16:$imm),
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(ADDiu_MM GPR32:$src, immSExt16:$imm)>;
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def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm),
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(ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>;
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def : MipsPat<(and GPR32:$src, immZExt16:$imm),
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@ -1096,9 +1096,10 @@ def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
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//===----------------------------------------------------------------------===//
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/// Arithmetic Instructions (ALU Immediate)
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let AdditionalPredicates = [NotInMicroMips] in {
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def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
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add>,
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ADDI_FM<0x9>, IsAsCheapAsAMove;
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add>, ADDI_FM<0x9>, IsAsCheapAsAMove;
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}
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def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
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ISA_MIPS1_NOT_32R6_64R6;
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def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
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@ -0,0 +1,25 @@
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; RUN: llc -march=mipsel -mcpu=mips32r2 -mattr=+micromips \
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; RUN: -relocation-model=pic -O3 < %s | FileCheck %s
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@x = global i32 65504, align 4
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@y = global i32 60929, align 4
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@.str = private unnamed_addr constant [7 x i8] c"%08x \0A\00", align 1
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define i32 @main() nounwind {
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entry:
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%0 = load i32* @x, align 4
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%addiu1 = add i32 %0, -7
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%call1 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
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([7 x i8]* @.str, i32 0, i32 0), i32 %addiu1)
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%1 = load i32* @y, align 4
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%addiu2 = add i32 %1, 55
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%call2 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds
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([7 x i8]* @.str, i32 0, i32 0), i32 %addiu2)
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ret i32 0
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}
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declare i32 @printf(i8*, ...)
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; CHECK: addius5 ${{[0-9]+}}, -7
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; CHECK: addiu ${{[0-9]+}}, ${{[0-9]+}}, 55
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