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[ARM] Small refactor of Thumb2 SMLA insts 

Follow up to r276624. Changes bits 22-20 to be parameters to
instruction class.

Differential Revision: https://reviews.llvm.org/D22562

llvm-svn: 276626
This commit is contained in:
Sam Parker 2016-07-25 09:29:24 +00:00
parent 1224c809f1
commit 73f5c785c1
1 changed files with 8 additions and 12 deletions
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20
llvm/lib/Target/ARM/ARMInstrThumb2.td
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@ -2638,36 +2638,32 @@ def t2SMULTT : T2ThreeRegSMUL<0b001, 0b11, "smultt",
def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb", []>; def t2SMULWB : T2ThreeRegSMUL<0b011, 0b00, "smulwb", []>;
def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt", []>; def t2SMULWT : T2ThreeRegSMUL<0b011, 0b01, "smulwt", []>;
class T2FourRegSMLA<bits<2> op5_4, string opc, list<dag> pattern> class T2FourRegSMLA<bits<3> op22_20, bits<2> op5_4, string opc, list<dag> pattern>
: T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16, : T2FourReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMUL16,
opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>, opc, "\t$Rd, $Rn, $Rm, $Ra", pattern>,
Requires<[IsThumb2, HasDSP, UseMulOps]> { Requires<[IsThumb2, HasDSP, UseMulOps]> {
let Inst{31-27} = 0b11111; let Inst{31-27} = 0b11111;
let Inst{26-23} = 0b0110; let Inst{26-23} = 0b0110;
let Inst{22-20} = 0b001; let Inst{22-20} = op22_20;
let Inst{7-6} = 0b00; let Inst{7-6} = 0b00;
let Inst{5-4} = op5_4; let Inst{5-4} = op5_4;
} }
def t2SMLABB : T2FourRegSMLA<0b00, "smlabb", def t2SMLABB : T2FourRegSMLA<0b001, 0b00, "smlabb",
[(set rGPR:$Rd, (add rGPR:$Ra, [(set rGPR:$Rd, (add rGPR:$Ra,
(mul (sext_inreg rGPR:$Rn, i16), (mul (sext_inreg rGPR:$Rn, i16),
(sext_inreg rGPR:$Rm, i16))))]>; (sext_inreg rGPR:$Rm, i16))))]>;
def t2SMLABT : T2FourRegSMLA<0b01, "smlabt", def t2SMLABT : T2FourRegSMLA<0b001, 0b01, "smlabt",
[(set rGPR:$Rd, (add rGPR:$Ra, (mul (sext_inreg rGPR:$Rn, i16), [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sext_inreg rGPR:$Rn, i16),
(sra rGPR:$Rm, (i32 16)))))]>; (sra rGPR:$Rm, (i32 16)))))]>;
def t2SMLATB : T2FourRegSMLA<0b10, "smlatb", def t2SMLATB : T2FourRegSMLA<0b001, 0b10, "smlatb",
[(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)), [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
(sext_inreg rGPR:$Rm, i16))))]>; (sext_inreg rGPR:$Rm, i16))))]>;
def t2SMLATT : T2FourRegSMLA<0b11, "smlatt", def t2SMLATT : T2FourRegSMLA<0b001, 0b11, "smlatt",
[(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)), [(set rGPR:$Rd, (add rGPR:$Ra, (mul (sra rGPR:$Rn, (i32 16)),
(sra rGPR:$Rm, (i32 16)))))]>; (sra rGPR:$Rm, (i32 16)))))]>;
def t2SMLAWB : T2FourRegSMLA<0b00, "smlawb", []> { def t2SMLAWB : T2FourRegSMLA<0b011, 0b00, "smlawb", []>;
let Inst{22-20} = 0b011; def t2SMLAWT : T2FourRegSMLA<0b011, 0b01, "smlawt", []>;
}
def t2SMLAWT : T2FourRegSMLA<0b01, "smlawt", []> {
let Inst{22-20} = 0b011;
}
class T2SMLAL<bits<3> op22_20, bits<4> op7_4, string opc, list<dag> pattern> class T2SMLAL<bits<3> op22_20, bits<4> op7_4, string opc, list<dag> pattern>
: T2FourReg_mac<1, op22_20, op7_4, : T2FourReg_mac<1, op22_20, op7_4,