forked from OSchip/llvm-project
[PowerPC][NFC] Update test assertions using update_llc_test_checks.py
Summary: This patch is made due to https://reviews.llvm.org/rL371289 where typo fixes failed. Differential Revision: https://reviews.llvm.org/D67317 llvm-svn: 371483
This commit is contained in:
Kai Luo
parent
daa79c5338
commit
73da43aeb3
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@ -15,7 +15,7 @@ define void @store_i32_by_i8(i32 signext %m, i8* %p) {
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;
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; CHECK-PPC64-LABEL: store_i32_by_i8:
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; CHECK-PPC64: # %bb.0: # %entry
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; CHECK-PPC64-NEXT: stwbrx 3, 0, 4
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; CHECK-PPC64-NEXT: stwbrx 3, 0, 4
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; CHECK-PPC64-NEXT: blr
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entry:
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%conv = trunc i32 %m to i8
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@ -187,18 +187,18 @@ entry:
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define void @store_i64_by_i8_bswap_uses(i32 signext %t, i8* %p) {
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; CHECK-PPC64LE-LABEL: store_i64_by_i8_bswap_uses:
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; CHECK-PPC64LE: # %bb.0: # %entry
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; CHECK-PPC64LE-NEXT: slwi [[REG:[0-9]+]], 3, 3
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; CHECK-PPC64LE-NEXT: subf [[REG1:[0-9]+]], 3, [[REG]]
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; CHECK-PPC64LE-NEXT: extsw [[REG2:[0-9]+]], [[REG1]]
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; CHECK-PPC64LE-NEXT: stdbrx [[REG2]], 0, 4
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; CHECK-PPC64LE-NEXT: slwi 5, 3, 3
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; CHECK-PPC64LE-NEXT: subf 3, 3, 5
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; CHECK-PPC64LE-NEXT: extsw 3, 3
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; CHECK-PPC64LE-NEXT: stdbrx 3, 0, 4
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; CHECK-PPC64LE-NEXT: blr
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;
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; CHECK-PPC64-LABEL: store_i64_by_i8_bswap_uses:
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; CHECK-PPC64: # %bb.0: # %entry
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; CHECK-PPC64-NEXT: slwi [[REG:[0-9]+]], 3, 3
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; CHECK-PPC64-NEXT: subf [[REG1:[0-9]+]], 3, [[REG]]
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; CHECK-PPC64-NEXT: extsw [[REG2:[0-9]+]], [[REG1]]
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; CHECK-PPC64-NEXT: stdx [[REG2]], 0, 4
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; CHECK-PPC64-NEXT: slwi 5, 3, 3
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; CHECK-PPC64-NEXT: subf 3, 3, 5
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; CHECK-PPC64-NEXT: extsw 3, 3
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; CHECK-PPC64-NEXT: stdx 3, 0, 4
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; CHECK-PPC64-NEXT: blr
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entry:
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%mul = mul nsw i32 %t, 7
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@ -234,8 +234,6 @@ entry:
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%conv28 = trunc i64 %shr26 to i8
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store i8 %conv28, i8* %p, align 1
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ret void
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; CEHCK-PPC64LE: stdbrx [[REG2]], 0, 4
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; CEHCK-PPC64: stdx [[REG2]], 0, 4
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}
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; One of the stores is volatile
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@ -248,11 +246,22 @@ entry:
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define void @store_i32_by_i8_bswap_volatile(i32 signext %m, i8* %p) {
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; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_volatile:
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; CHECK-PPC64LE: # %bb.0: # %entry
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; CHECK-PPC64LE-NOT: stwbrx
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; CHECK-PPC64LE-NEXT: li 5, 2
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; CHECK-PPC64LE-NEXT: sthbrx 3, 4, 5
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; CHECK-PPC64LE-NEXT: srwi 5, 3, 16
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; CHECK-PPC64LE-NEXT: srwi 3, 3, 24
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; CHECK-PPC64LE-NEXT: stb 5, 1(4)
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; CHECK-PPC64LE-NEXT: stb 3, 0(4)
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; CHECK-PPC64LE-NEXT: blr
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;
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; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_volatile:
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; CHECK-PPC64: # %bb.0: # %entry
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; CHECK-PPC64-NOT: stw
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; CHECK-PPC64-NEXT: sth 3, 2(4)
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; CHECK-PPC64-NEXT: srwi 5, 3, 16
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; CHECK-PPC64-NEXT: srwi 3, 3, 24
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; CHECK-PPC64-NEXT: stb 5, 1(4)
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; CHECK-PPC64-NEXT: stb 3, 0(4)
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; CHECK-PPC64-NEXT: blr
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entry:
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%conv = trunc i32 %m to i8
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%arrayidx = getelementptr inbounds i8, i8* %p, i64 3
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@ -281,11 +290,26 @@ entry:
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define void @store_i32_by_i8_bswap_store_in_between(i32 signext %m, i8* %p, i8* %q) {
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; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_store_in_between:
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; CHECK-PPC64LE: # %bb.0: # %entry
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; CHECK-PPC64LE-NOT: stwbrx
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; CHECK-PPC64LE-NEXT: li 6, 2
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; CHECK-PPC64LE-NEXT: sthbrx 3, 4, 6
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; CHECK-PPC64LE-NEXT: li 6, 3
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; CHECK-PPC64LE-NEXT: stb 6, 0(5)
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; CHECK-PPC64LE-NEXT: srwi 5, 3, 16
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; CHECK-PPC64LE-NEXT: srwi 3, 3, 24
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; CHECK-PPC64LE-NEXT: stb 5, 1(4)
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; CHECK-PPC64LE-NEXT: stb 3, 0(4)
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; CHECK-PPC64LE-NEXT: blr
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;
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; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_store_in_between:
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; CHECK-PPC64: # %bb.0: # %entry
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; CHECK-PPC64-NOT: stw
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; CHECK-PPC64-NEXT: li 6, 3
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; CHECK-PPC64-NEXT: sth 3, 2(4)
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; CHECK-PPC64-NEXT: stb 6, 0(5)
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; CHECK-PPC64-NEXT: srwi 5, 3, 16
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; CHECK-PPC64-NEXT: srwi 3, 3, 24
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; CHECK-PPC64-NEXT: stb 5, 1(4)
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; CHECK-PPC64-NEXT: stb 3, 0(4)
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; CHECK-PPC64-NEXT: blr
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entry:
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%conv = trunc i32 %m to i8
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%arrayidx = getelementptr inbounds i8, i8* %p, i64 3
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@ -308,11 +332,25 @@ entry:
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define void @store_i32_by_i8_bswap_unrelated_store(i32 signext %m, i8* %p, i8* %q) {
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; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_unrelated_store:
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; CHECK-PPC64LE: # %bb.0: # %entry
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; CHECK-PPC64LE-NOT: stwbrx
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; CHECK-PPC64LE-NEXT: srwi 6, 3, 8
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; CHECK-PPC64LE-NEXT: stb 3, 3(4)
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; CHECK-PPC64LE-NEXT: stb 6, 2(5)
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; CHECK-PPC64LE-NEXT: srwi 5, 3, 16
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; CHECK-PPC64LE-NEXT: srwi 3, 3, 24
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; CHECK-PPC64LE-NEXT: stb 5, 1(4)
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; CHECK-PPC64LE-NEXT: stb 3, 0(4)
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; CHECK-PPC64LE-NEXT: blr
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;
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; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_unrelated_store:
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; CHECK-PPC64: # %bb.0: # %entry
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; CHECK-PPC64-NOT: stw
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; CHECK-PPC64-NEXT: srwi 6, 3, 8
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; CHECK-PPC64-NEXT: stb 3, 3(4)
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; CHECK-PPC64-NEXT: stb 6, 2(5)
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; CHECK-PPC64-NEXT: srwi 5, 3, 16
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; CHECK-PPC64-NEXT: srwi 3, 3, 24
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; CHECK-PPC64-NEXT: stb 5, 1(4)
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; CHECK-PPC64-NEXT: stb 3, 0(4)
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; CHECK-PPC64-NEXT: blr
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entry:
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%conv = trunc i32 %m to i8
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%arrayidx = getelementptr inbounds i8, i8* %p, i64 3
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@ -339,8 +377,8 @@ entry:
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define void @store_i32_by_i8_bswap_nonzero_offset(i32 signext %m, i8* %p) {
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; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_nonzero_offset:
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; CHECK-PPC64LE: # %bb.0: # %entry
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; CHECK-PPC64LE-NEXT: addi [[REG1:[0-9]+]], 4, 1
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; CHECK-PPC64LE-NEXT: stwbrx 3, 0, [[REG1]]
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; CHECK-PPC64LE-NEXT: addi 4, 4, 1
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; CHECK-PPC64LE-NEXT: stwbrx 3, 0, 4
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; CHECK-PPC64LE-NEXT: blr
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;
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; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_nonzero_offset:
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@ -379,8 +417,8 @@ define void @store_i32_by_i8_neg_offset(i32 signext %m, i8* %p) {
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;
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; CHECK-PPC64-LABEL: store_i32_by_i8_neg_offset:
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; CHECK-PPC64: # %bb.0: # %entry
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; CHECK-PPC64-NEXT: addi [[REG1:[0-9]+]], 4, -4
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; CHECK-PPC64-NEXT: stwbrx 3, 0, [[REG1]]
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; CHECK-PPC64-NEXT: addi 4, 4, -4
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; CHECK-PPC64-NEXT: stwbrx 3, 0, 4
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; CHECK-PPC64-NEXT: blr
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entry:
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%0 = lshr i32 %m, 8
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@ -409,8 +447,8 @@ entry:
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define void @store_i32_by_i8_bswap_neg_offset(i32 signext %m, i8* %p) {
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; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_neg_offset:
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; CHECK-PPC64LE: # %bb.0: # %entry
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; CHECK-PPC64LE-NEXT: addi [[REG1:[0-9]+]], 4, -4
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; CHECK-PPC64LE-NEXT: stwbrx 3, 0, [[REG1]]
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; CHECK-PPC64LE-NEXT: addi 4, 4, -4
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; CHECK-PPC64LE-NEXT: stwbrx 3, 0, 4
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; CHECK-PPC64LE-NEXT: blr
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;
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; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_neg_offset:
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@ -444,17 +482,17 @@ entry:
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define void @store_i32_by_i8_bswap_base_index_offset(i32 %m, i32 %i, i8* %p) {
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; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_base_index_offset:
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; CHECK-PPC64LE: # %bb.0: # %entry
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; CHECK-PPC64LE-NEXT: extsw [[REG1:[0-9]+]], 4
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; CHECK-PPC64LE-NEXT: add [[REG2:[0-9]+]], 5, [[REG1]]
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; CHECK-PPC64LE-NEXT: addi [[REG3:[0-9]+]], [[REG2]], -4
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; CHECK-PPC64LE-NEXT: stwbrx 3, 0, [[REG3]]
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; CHECK-PPC64LE-NEXT: extsw 4, 4
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; CHECK-PPC64LE-NEXT: add 4, 5, 4
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; CHECK-PPC64LE-NEXT: addi 4, 4, -4
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; CHECK-PPC64LE-NEXT: stwbrx 3, 0, 4
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; CHECK-PPC64LE-NEXT: blr
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;
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; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_base_index_offset:
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; CHECK-PPC64: # %bb.0: # %entry
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; CHECK-PPC64-NEXT: extsw [[REG1:[0-9]+]], 4
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; CHECK-PPC64-NEXT: add [[REG2:[0-9]+]], 5, [[REG1]]
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; CHECK-PPC64-NEXT: stw 3, -4([[REG2]])
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; CHECK-PPC64-NEXT: extsw 4, 4
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; CHECK-PPC64-NEXT: add 4, 5, 4
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; CHECK-PPC64-NEXT: stw 3, -4(4)
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; CHECK-PPC64-NEXT: blr
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entry:
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%0 = lshr i32 %m, 16
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@ -496,17 +534,17 @@ entry:
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define void @store_i32_by_i8_bswap_complicated(i32 %m, i32 %i, i8* %p) {
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; CHECK-PPC64LE-LABEL: store_i32_by_i8_bswap_complicated:
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; CHECK-PPC64LE: # %bb.0: # %entry
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; CHECK-PPC64LE-NEXT: extsw [[REG1:[0-9]+]], 4
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; CHECK-PPC64LE-NEXT: add [[REG2:[0-9]+]], 5, [[REG1]]
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; CHECK-PPC64LE-NEXT: addi [[REG3:[0-9]+]], [[REG2]], 3
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; CHECK-PPC64LE-NEXT: stwbrx 3, 0, [[REG3]]
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; CHECK-PPC64LE-NEXT: extsw 4, 4
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; CHECK-PPC64LE-NEXT: add 4, 5, 4
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; CHECK-PPC64LE-NEXT: addi 4, 4, 3
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; CHECK-PPC64LE-NEXT: stwbrx 3, 0, 4
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; CHECK-PPC64LE-NEXT: blr
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;
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; CHECK-PPC64-LABEL: store_i32_by_i8_bswap_complicated:
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; CHECK-PPC64: # %bb.0: # %entry
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; CHECK-PPC64-NEXT: extsw [[REG1:[0-9]+]], 4
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; CHECK-PPC64-NEXT: add [[REG2:[0-9]+]], 5, [[REG1]]
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; CHECK-PPC64-NEXT: stw 3, 3([[REG2]])
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; CHECK-PPC64-NEXT: extsw 4, 4
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; CHECK-PPC64-NEXT: add 4, 5, 4
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; CHECK-PPC64-NEXT: stw 3, 3(4)
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; CHECK-PPC64-NEXT: blr
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entry:
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%idx.ext = sext i32 %i to i64
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@ -579,15 +617,17 @@ entry:
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; p[0] = v;
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; p[1] = v;
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define void @store_same_value_to_consecutive_mem(i8* %p, i8 zeroext %v) {
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; CHECK-PPC64LE-LABEL: store_same_value_to_consecutive_mem
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; CHECK-PPC64LE: # %bb.0: # %entry
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; CHECK-PPC64LE-NEXT: stb 4, 0(3)
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; CHECK-PPC64LE-NEXT: stb 4, 1(3)
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; CHECK-PPC64LE-LABEL: store_same_value_to_consecutive_mem:
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; CHECK-PPC64LE: # %bb.0: # %entry
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; CHECK-PPC64LE-NEXT: stb 4, 0(3)
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; CHECK-PPC64LE-NEXT: stb 4, 1(3)
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; CHECK-PPC64LE-NEXT: blr
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;
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; CHECK-PPC64-LABEL: store_same_value_to_consecutive_mem
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; CHECK-PPC64-LABEL: store_same_value_to_consecutive_mem:
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; CHECK-PPC64: # %bb.0: # %entry
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; CHECK-PPC64-NEXT: stb 4, 0(3)
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; CHECK-PPC64-NEXT: stb 4, 1(3)
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; CHECK-PPC64-NEXT: blr
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entry:
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store i8 %v, i8* %p, align 1
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%arrayidx1 = getelementptr inbounds i8, i8* %p, i64 1
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