forked from OSchip/llvm-project
[WebAssembly] Basic TargetTransformInfo support for SIMD128.
llvm-svn: 270508
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parent
478c1a25fd
commit
73d7a555b9
llvm/lib/Target/WebAssembly
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@ -25,3 +25,59 @@ WebAssemblyTTIImpl::getPopcntSupport(unsigned TyWidth) const {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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return TargetTransformInfo::PSK_FastHardware;
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return TargetTransformInfo::PSK_FastHardware;
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}
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}
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unsigned WebAssemblyTTIImpl::getNumberOfRegisters(bool Vector) {
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unsigned Result = BaseT::getNumberOfRegisters(Vector);
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// For SIMD, use at least 16 registers, as a rough guess.
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if (Vector)
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Result = std::max(Result, 16u);
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return Result;
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}
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unsigned WebAssemblyTTIImpl::getRegisterBitWidth(bool Vector) {
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if (Vector && getST()->hasSIMD128())
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return 128;
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return 64;
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}
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unsigned WebAssemblyTTIImpl::getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::OperandValueKind Opd1Info,
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TTI::OperandValueKind Opd2Info, TTI::OperandValueProperties Opd1PropInfo,
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TTI::OperandValueProperties Opd2PropInfo) {
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unsigned Cost = BasicTTIImplBase<WebAssemblyTTIImpl>::getArithmeticInstrCost(
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Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo);
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if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
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switch (Opcode) {
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case Instruction::LShr:
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case Instruction::AShr:
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case Instruction::Shl:
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// SIMD128's shifts currently only accept a scalar shift count. For each
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// element, we'll need to extract, op, insert. The following is a rough
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// approxmation.
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if (Opd2Info != TTI::OK_UniformValue &&
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Opd2Info != TTI::OK_UniformConstantValue)
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Cost = VTy->getNumElements() *
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(TargetTransformInfo::TCC_Basic +
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getArithmeticInstrCost(Opcode, VTy->getElementType()) +
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TargetTransformInfo::TCC_Basic);
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break;
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}
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}
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return Cost;
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}
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unsigned WebAssemblyTTIImpl::getVectorInstrCost(unsigned Opcode, Type *Val,
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unsigned Index) {
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unsigned Cost = BasicTTIImplBase::getVectorInstrCost(Opcode, Val, Index);
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// SIMD128's insert/extract currently only take constant indices.
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if (Index == -1u)
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return Cost + 25 * TargetTransformInfo::TCC_Expensive;
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return Cost;
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}
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@ -61,7 +61,15 @@ public:
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/// \name Vector TTI Implementations
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/// \name Vector TTI Implementations
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/// @{
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/// @{
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// TODO: Implement Vector TTI for WebAssembly
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unsigned getNumberOfRegisters(bool Vector);
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unsigned getRegisterBitWidth(bool Vector);
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unsigned getArithmeticInstrCost(
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unsigned Opcode, Type *Ty,
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TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue,
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TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue,
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TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None,
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TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None);
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unsigned getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index);
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/// @}
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/// @}
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};
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};
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