forked from OSchip/llvm-project
[Hexagon] Using MustExtend flag on expression instead of passing around bools.
llvm-svn: 262238
This commit is contained in:
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2ce5cf0393
commit
73cd686ce1
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@ -108,7 +108,7 @@ class HexagonAsmParser : public MCTargetAsmParser {
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void canonicalizeImmediates(MCInst &MCI);
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bool matchOneInstruction(MCInst &MCB, SMLoc IDLoc,
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OperandVector &InstOperands, uint64_t &ErrorInfo,
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bool MatchingInlineAsm, bool &MustExtend);
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bool MatchingInlineAsm);
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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OperandVector &Operands, MCStreamer &Out,
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@ -117,7 +117,7 @@ class HexagonAsmParser : public MCTargetAsmParser {
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unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override;
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void OutOfRange(SMLoc IDLoc, long long Val, long long Max);
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int processInstruction(MCInst &Inst, OperandVector const &Operands,
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SMLoc IDLoc, bool &MustExtend);
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SMLoc IDLoc);
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// Check if we have an assembler and, if so, set the ELF e_header flags.
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void chksetELFHeaderEFlags(unsigned flags) {
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@ -186,7 +186,6 @@ struct HexagonOperand : public MCParsedAsmOperand {
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struct ImmTy {
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const MCExpr *Val;
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bool MustExtend;
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};
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struct InstTy {
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@ -244,7 +243,7 @@ public:
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bool isRelocatable, bool Extendable) const {
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if (Kind == Immediate) {
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const MCExpr *myMCExpr = &HexagonMCInstrInfo::getExpr(*getImm());
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if (Imm.MustExtend && !Extendable)
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if (HexagonMCInstrInfo::mustExtend(*Imm.Val) && !Extendable)
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return false;
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int64_t Res;
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if (myMCExpr->evaluateAsAbsolute(Res)) {
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@ -348,7 +347,7 @@ public:
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bool isu6_1Ext() const { return CheckImmRange(6 + 26, 1, false, true, true); }
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bool isu6_2Ext() const { return CheckImmRange(6 + 26, 2, false, true, true); }
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bool isu6_3Ext() const { return CheckImmRange(6 + 26, 3, false, true, true); }
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bool isu32MustExt() const { return isImm() && Imm.MustExtend; }
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bool isu32MustExt() const { return isImm(); }
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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@ -598,7 +597,6 @@ public:
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SMLoc E) {
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HexagonOperand *Op = new HexagonOperand(Immediate);
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Op->Imm.Val = Val;
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Op->Imm.MustExtend = false;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return std::unique_ptr<HexagonOperand>(Op);
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@ -782,16 +780,14 @@ void HexagonAsmParser::canonicalizeImmediates(MCInst &MCI) {
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bool HexagonAsmParser::matchOneInstruction(MCInst &MCI, SMLoc IDLoc,
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OperandVector &InstOperands,
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uint64_t &ErrorInfo,
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bool MatchingInlineAsm,
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bool &MustExtend) {
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bool MatchingInlineAsm) {
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// Perform matching with tablegen asmmatcher generated function
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int result =
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MatchInstructionImpl(InstOperands, MCI, ErrorInfo, MatchingInlineAsm);
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if (result == Match_Success) {
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MCI.setLoc(IDLoc);
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MustExtend = mustExtend(InstOperands);
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canonicalizeImmediates(MCI);
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result = processInstruction(MCI, InstOperands, IDLoc, MustExtend);
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result = processInstruction(MCI, InstOperands, IDLoc);
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DEBUG(dbgs() << "Insn:");
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DEBUG(MCI.dump_pretty(dbgs()));
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@ -833,7 +829,8 @@ bool HexagonAsmParser::mustExtend(OperandVector &Operands) {
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unsigned Count = 0;
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for (std::unique_ptr<MCParsedAsmOperand> &i : Operands)
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if (i->isImm())
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if (static_cast<HexagonOperand *>(i.get())->Imm.MustExtend)
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if (HexagonMCInstrInfo::mustExtend(
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*static_cast<HexagonOperand *>(i.get())->Imm.Val))
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++Count;
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// Multiple extenders should have been filtered by iss9Ext et. al.
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assert(Count < 2 && "Multiple extenders");
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@ -871,13 +868,11 @@ bool HexagonAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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return finishBundle(IDLoc, Out);
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}
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MCInst *SubInst = new (getParser().getContext()) MCInst;
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bool MustExtend = false;
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if (matchOneInstruction(*SubInst, IDLoc, Operands, ErrorInfo,
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MatchingInlineAsm, MustExtend))
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MatchingInlineAsm))
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return true;
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HexagonMCInstrInfo::extendIfNeeded(
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getParser().getContext(), MCII, MCB, *SubInst,
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HexagonMCInstrInfo::isExtended(MCII, *SubInst) || MustExtend);
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getParser().getContext(), MCII, MCB, *SubInst);
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MCB.addOperand(MCOperand::createInst(SubInst));
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if (!InBrackets)
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return finishBundle(IDLoc, Out);
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@ -1446,9 +1441,9 @@ bool HexagonAsmParser::parseInstruction(OperandVector &Operands) {
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}
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Expr = HexagonMCExpr::create(Expr, Context);
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HexagonMCInstrInfo::setMustNotExtend(*Expr, MustNotExtend);
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HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
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std::unique_ptr<HexagonOperand> Operand =
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HexagonOperand::CreateImm(Expr, ExprLoc, ExprLoc);
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Operand->Imm.MustExtend = MustExtend;
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Operands.push_back(std::move(Operand));
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continue;
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}
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@ -1535,7 +1530,7 @@ void HexagonAsmParser::OutOfRange(SMLoc IDLoc, long long Val, long long Max) {
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int HexagonAsmParser::processInstruction(MCInst &Inst,
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OperandVector const &Operands,
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SMLoc IDLoc, bool &MustExtend) {
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SMLoc IDLoc) {
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MCContext &Context = getParser().getContext();
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const MCRegisterInfo *RI = getContext().getRegisterInfo();
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std::string r = "r";
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@ -1789,9 +1784,11 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
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OutOfRange(IDLoc, s8, -128);
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MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
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MCConstantExpr::create(s8, Context), Context))); // upper 32
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MCOperand imm2(MCOperand::createExpr(HexagonMCExpr::create(
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MCConstantExpr::create(u64 & 0xFFFFFFFF, Context),
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Context))); // lower 32
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auto Expr = HexagonMCExpr::create(
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MCConstantExpr::create(u64 & 0xFFFFFFFF, Context),
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Context);
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HexagonMCInstrInfo::setMustExtend(*Expr, HexagonMCInstrInfo::mustExtend(*MO.getExpr()));
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MCOperand imm2(MCOperand::createExpr(Expr)); // lower 32
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Inst = makeCombineInst(Hexagon::A4_combineii, Rdd, imm, imm2);
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} else {
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MCOperand imm(MCOperand::createExpr(HexagonMCExpr::create(
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@ -1903,10 +1900,11 @@ int HexagonAsmParser::processInstruction(MCInst &Inst,
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MCOperand &Rs = Inst.getOperand(1);
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MCOperand &Imm = Inst.getOperand(2);
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int64_t Value;
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bool Absolute = Imm.getExpr()->evaluateAsAbsolute(Value);
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MCExpr const &Expr = *Imm.getExpr();
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bool Absolute = Expr.evaluateAsAbsolute(Value);
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assert(Absolute);
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(void)Absolute;
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if (!MustExtend) {
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if (!HexagonMCInstrInfo::mustExtend(Expr)) {
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if (Value < 0 && Value > -256) {
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Imm.setExpr(HexagonMCExpr::create(
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MCConstantExpr::create(Value * -1, Context), Context));
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@ -32,7 +32,7 @@ namespace llvm {
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}
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static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
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HexagonAsmPrinter &Printer) {
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HexagonAsmPrinter &Printer, bool MustExtend) {
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MCContext &MC = Printer.OutContext;
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const MCExpr *ME;
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@ -81,7 +81,9 @@ static MCOperand GetSymbolRef(const MachineOperand &MO, const MCSymbol *Symbol,
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ME = MCBinaryExpr::createAdd(ME, MCConstantExpr::create(MO.getOffset(), MC),
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MC);
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return MCOperand::createExpr(HexagonMCExpr::create(ME, MC));
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ME = HexagonMCExpr::create(ME, MC);
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HexagonMCInstrInfo::setMustExtend(*ME, MustExtend);
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return MCOperand::createExpr(ME);
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}
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// Create an MCInst from a MachineInstr
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@ -99,13 +101,11 @@ void llvm::HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
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MCI->setOpcode(MI->getOpcode());
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assert(MCI->getOpcode() == static_cast<unsigned>(MI->getOpcode()) &&
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"MCI opcode should have been set on construction");
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bool MustExtend = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i < e; i++) {
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const MachineOperand &MO = MI->getOperand(i);
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MCOperand MCO;
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if (MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended)
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MustExtend = true;
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bool MustExtend = MO.getTargetFlags() & HexagonII::HMOTF_ConstExtended;
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switch (MO.getType()) {
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default:
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@ -120,42 +120,51 @@ void llvm::HexagonLowerToMC(const MCInstrInfo &MCII, const MachineInstr *MI,
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APFloat Val = MO.getFPImm()->getValueAPF();
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// FP immediates are used only when setting GPRs, so they may be dealt
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// with like regular immediates from this point on.
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MCO = MCOperand::createExpr(
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HexagonMCExpr::create(MCConstantExpr::create(*Val.bitcastToAPInt().getRawData(),
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AP.OutContext), AP.OutContext));
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auto Expr = HexagonMCExpr::create(
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MCConstantExpr::create(*Val.bitcastToAPInt().getRawData(),
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AP.OutContext),
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AP.OutContext);
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HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
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MCO = MCOperand::createExpr(Expr);
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break;
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}
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case MachineOperand::MO_Immediate:
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MCO = MCOperand::createExpr(
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HexagonMCExpr::create(MCConstantExpr::create(MO.getImm(), AP.OutContext), AP.OutContext));
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case MachineOperand::MO_Immediate: {
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auto Expr = HexagonMCExpr::create(
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MCConstantExpr::create(MO.getImm(), AP.OutContext), AP.OutContext);
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HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
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MCO = MCOperand::createExpr(Expr);
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCO = MCOperand::createExpr
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(HexagonMCExpr::create(MCSymbolRefExpr::create(MO.getMBB()->getSymbol(),
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AP.OutContext), AP.OutContext));
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}
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case MachineOperand::MO_MachineBasicBlock: {
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MCExpr const *Expr = MCSymbolRefExpr::create(MO.getMBB()->getSymbol(),
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AP.OutContext);
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Expr = HexagonMCExpr::create(Expr, AP.OutContext);
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HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
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MCO = MCOperand::createExpr(Expr);
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break;
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}
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case MachineOperand::MO_GlobalAddress:
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MCO = GetSymbolRef(MO, AP.getSymbol(MO.getGlobal()), AP);
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MCO = GetSymbolRef(MO, AP.getSymbol(MO.getGlobal()), AP, MustExtend);
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break;
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case MachineOperand::MO_ExternalSymbol:
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MCO = GetSymbolRef(MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()),
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AP);
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AP, MustExtend);
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break;
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case MachineOperand::MO_JumpTableIndex:
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MCO = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP);
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MCO = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP, MustExtend);
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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MCO = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP);
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MCO = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP, MustExtend);
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break;
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case MachineOperand::MO_BlockAddress:
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MCO = GetSymbolRef(MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()),AP);
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MCO = GetSymbolRef(MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP,
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MustExtend);
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break;
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}
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MCI->addOperand(MCO);
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}
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AP.HexagonProcessInstruction(*MCI, *MI);
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HexagonMCInstrInfo::extendIfNeeded(AP.OutContext, MCII, MCB, *MCI,
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MustExtend);
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HexagonMCInstrInfo::extendIfNeeded(AP.OutContext, MCII, MCB, *MCI);
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MCB.addOperand(MCOperand::createInst(MCI));
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}
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@ -160,8 +160,8 @@ MCInst const *HexagonMCInstrInfo::extenderForIndex(MCInst const &MCB,
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void HexagonMCInstrInfo::extendIfNeeded(MCContext &Context,
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MCInstrInfo const &MCII, MCInst &MCB,
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MCInst const &MCI, bool MustExtend) {
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if (isConstExtended(MCII, MCI) || MustExtend)
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MCInst const &MCI) {
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if (isConstExtended(MCII, MCI))
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addConstExtender(Context, MCII, MCB, MCI);
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}
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@ -408,6 +408,12 @@ bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII,
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MCInst const &MCI) {
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if (HexagonMCInstrInfo::isExtended(MCII, MCI))
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return true;
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if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
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return false;
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MCOperand const &MO = HexagonMCInstrInfo::getExtendableOperand(MCII, MCI);
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if (isa<HexagonMCExpr>(MO.getExpr()) &&
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HexagonMCInstrInfo::mustExtend(*MO.getExpr()))
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return true;
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// Branch insns are handled as necessary by relaxation.
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if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
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(HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCOMPOUND &&
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@ -419,10 +425,6 @@ bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII,
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else if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCR) &&
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(MCI.getOpcode() != Hexagon::C4_addipc))
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return false;
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else if (!HexagonMCInstrInfo::isExtendable(MCII, MCI))
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return false;
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MCOperand const &MO = HexagonMCInstrInfo::getExtendableOperand(MCII, MCI);
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// We could be using an instruction with an extendable immediate and shoehorn
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// a global address into it. If it is a global address it will be constant
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@ -585,8 +587,8 @@ int64_t HexagonMCInstrInfo::minConstant(MCInst const &MCI, size_t Index) {
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return Value;
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}
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void HexagonMCInstrInfo::setMustExtend(MCExpr &Expr, bool Val) {
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HexagonMCExpr &HExpr = cast<HexagonMCExpr>(Expr);
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void HexagonMCInstrInfo::setMustExtend(MCExpr const &Expr, bool Val) {
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HexagonMCExpr &HExpr = const_cast<HexagonMCExpr &>(cast<HexagonMCExpr>(Expr));
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HExpr.setMustExtend(Val);
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}
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@ -75,7 +75,7 @@ MCInst createBundle();
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// Return the extender for instruction at Index or nullptr if none
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MCInst const *extenderForIndex(MCInst const &MCB, size_t Index);
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void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
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MCInst const &MCI, bool MustExtend);
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MCInst const &MCI);
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// Create a duplex instruction given the two subinsts
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MCInst *deriveDuplex(MCContext &Context, unsigned iClass, MCInst const &inst0,
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@ -279,7 +279,7 @@ bool s23_2_reloc(MCExpr const &Expr);
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void setInnerLoop(MCInst &MCI);
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void setMemReorderDisabled(MCInst &MCI);
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void setMemStoreReorderEnabled(MCInst &MCI);
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void setMustExtend(MCExpr &Expr, bool Val = true);
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void setMustExtend(MCExpr const &Expr, bool Val = true);
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void setMustNotExtend(MCExpr const &Expr, bool Val = true);
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void setS23_2_reloc(MCExpr const &Expr, bool Val = true);
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