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Revert "Reapply Revert "RegAllocFast: Rewrite and improve"" 

This reverts commit 55f9f87da2.

Breaks following buildbots:
http://lab.llvm.org:8011/builders/lldb-arm-ubuntu/builds/4306
http://lab.llvm.org:8011/builders/lldb-aarch64-ubuntu/builds/9154
This commit is contained in:
Muhammad Omair Javaid 2020-09-22 14:20:10 +05:00
parent 66bcb14312
commit 73a6a164b8
186 changed files with 10897 additions and 11280 deletions
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8
lldb/test/Shell/SymbolFile/NativePDB/disassembly.cpp
View File

@ -28,9 +28,11 @@ int main(int argc, char **argv) {
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+17>: mov dword ptr [rsp + 0x24], ecx
// CHECK: ** 15 foo();
// CHECK: disassembly.cpp.tmp.exe[{{.*}}] <+21>: call {{.*}} ; foo at disassembly.cpp:12
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+26>: xor eax, eax
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+26>: xor ecx, ecx
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+28>: mov dword ptr [rsp + 0x20], eax
// CHECK: ** 16 return 0;
// CHECK-NEXT: 17 }
// CHECK-NEXT: 18
// CHECK: disassembly.cpp.tmp.exe[{{.*}}] <+28>: add rsp, 0x38
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+32>: ret
// CHECK: disassembly.cpp.tmp.exe[{{.*}}] <+32>: mov eax, ecx
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+34>: add rsp, 0x38
// CHECK-NEXT: disassembly.cpp.tmp.exe[{{.*}}] <+38>: ret

1308
llvm/lib/CodeGen/RegAllocFast.cpp
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File diff suppressed because it is too large Load Diff

5
llvm/test/CodeGen/AArch64/GlobalISel/darwin-tls-call-clobber.ll
View File

@ -31,8 +31,9 @@ target triple = "arm64-apple-ios13.0.0"
; This test checks that we don't re-use the register for the variable descriptor
; for the second ldr.
; CHECK: adrp x[[PTR1:[0-9]+]], _t_val@TLVPPAGE
; CHECK: ldr x0, [x[[PTR1]], _t_val@TLVPPAGEOFF]
; CHECK: ldr x[[FPTR:[0-9]+]], [x0]
; CHECK: ldr x[[PTR1]], [x[[PTR1]], _t_val@TLVPPAGEOFF]
; CHECK: ldr x[[FPTR:[0-9]+]], [x[[PTR1]]]
; CHECK: mov x0, x[[PTR1]]
; CHECK: blr x[[FPTR]]
define void @_Z4funcPKc(i8* %id) {

2
llvm/test/CodeGen/AArch64/arm64-fast-isel-br.ll
View File

@ -94,7 +94,7 @@ entry:
store i32 %c, i32* %c.addr, align 4
store i64 %d, i64* %d.addr, align 8
%0 = load i16, i16* %b.addr, align 2
; CHECK: tbz {{w[0-9]+}}, #0, LBB4_2
; CHECK: tbz w8, #0, LBB4_2
%conv = trunc i16 %0 to i1
br i1 %conv, label %if.then, label %if.end

3
llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
View File

@ -79,7 +79,8 @@ declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8
define i32 @t2() {
entry:
; CHECK-LABEL: t2
; CHECK: mov x0, xzr
; CHECK: mov [[REG1:x[0-9]+]], xzr
; CHECK: mov x0, [[REG1]]
; CHECK: mov w1, #-8
; CHECK: mov [[REG2:w[0-9]+]], #1023
; CHECK: uxth w2, [[REG2]]

34
llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion-fallback.ll
View File

@ -4,8 +4,9 @@
define i32 @fptosi_wh(half %a) nounwind ssp {
entry:
; CHECK-LABEL: fptosi_wh
; CHECK: fcvt [[REG:s[0-9]+]], h0
; CHECK: fcvtzs w0, [[REG]]
; CHECK: fcvt s0, h0
; CHECK: fcvtzs [[REG:w[0-9]+]], s0
; CHECK: mov w0, [[REG]]
%conv = fptosi half %a to i32
ret i32 %conv
}
@ -14,8 +15,9 @@ entry:
define i32 @fptoui_swh(half %a) nounwind ssp {
entry:
; CHECK-LABEL: fptoui_swh
; CHECK: fcvt [[REG:s[0-9]+]], h0
; CHECK: fcvtzu w0, [[REG]]
; CHECK: fcvt s0, h0
; CHECK: fcvtzu [[REG:w[0-9]+]], s0
; CHECK: mov w0, [[REG]]
%conv = fptoui half %a to i32
ret i32 %conv
}
@ -24,8 +26,8 @@ entry:
define half @sitofp_hw_i1(i1 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_hw_i1
; CHECK: sbfx [[REG:w[0-9]+]], w0, #0, #1
; CHECK: scvtf s0, [[REG]]
; CHECK: sbfx w8, w0, #0, #1
; CHECK: scvtf s0, w8
; CHECK: fcvt h0, s0
%conv = sitofp i1 %a to half
ret half %conv
@ -35,8 +37,8 @@ entry:
define half @sitofp_hw_i8(i8 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_hw_i8
; CHECK: sxtb [[REG:w[0-9]+]], w0
; CHECK: scvtf s0, [[REG]]
; CHECK: sxtb w8, w0
; CHECK: scvtf s0, w8
; CHECK: fcvt h0, s0
%conv = sitofp i8 %a to half
ret half %conv
@ -46,8 +48,8 @@ entry:
define half @sitofp_hw_i16(i16 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_hw_i16
; CHECK: sxth [[REG:w[0-9]+]], w0
; CHECK: scvtf s0, [[REG]]
; CHECK: sxth w8, w0
; CHECK: scvtf s0, w8
; CHECK: fcvt h0, s0
%conv = sitofp i16 %a to half
ret half %conv
@ -77,8 +79,8 @@ entry:
define half @uitofp_hw_i1(i1 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_hw_i1
; CHECK: and [[REG:w[0-9]+]], w0, #0x1
; CHECK: ucvtf s0, [[REG]]
; CHECK: and w8, w0, #0x1
; CHECK: ucvtf s0, w8
; CHECK: fcvt h0, s0
%conv = uitofp i1 %a to half
ret half %conv
@ -88,8 +90,8 @@ entry:
define half @uitofp_hw_i8(i8 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_hw_i8
; CHECK: and [[REG:w[0-9]+]], w0, #0xff
; CHECK: ucvtf s0, [[REG]]
; CHECK: and w8, w0, #0xff
; CHECK: ucvtf s0, w8
; CHECK: fcvt h0, s0
%conv = uitofp i8 %a to half
ret half %conv
@ -99,8 +101,8 @@ entry:
define half @uitofp_hw_i16(i16 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_hw_i16
; CHECK: and [[REG:w[0-9]+]], w0, #0xffff
; CHECK: ucvtf s0, [[REG]]
; CHECK: and w8, w0, #0xffff
; CHECK: ucvtf s0, w8
; CHECK: fcvt h0, s0
%conv = uitofp i16 %a to half
ret half %conv

56
llvm/test/CodeGen/AArch64/arm64-fast-isel-conversion.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck -enable-var-scope %s
; RUN: llc -O0 -fast-isel -fast-isel-abort=1 -verify-machineinstrs -mtriple=arm64-apple-darwin -mcpu=cyclone < %s | FileCheck %s
;; Test various conversions.
define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
@ -49,12 +49,13 @@ entry:
; CHECK: strh w1, [sp, #12]
; CHECK: str w2, [sp, #8]
; CHECK: str x3, [sp]
; CHECK: ldrb [[REG0:w[0-9]+]], [sp, #15]
; CHECK: strh [[REG0]], [sp, #12]
; CHECK: ldrh [[REG1:w[0-9]+]], [sp, #12]
; CHECK: str [[REG1]], [sp, #8]
; CHECK: ldr w[[REG2:[0-9]+]], [sp, #8]
; CHECK: str x[[REG2]], [sp]
; CHECK: ldrb w8, [sp, #15]
; CHECK: strh w8, [sp, #12]
; CHECK: ldrh w8, [sp, #12]
; CHECK: str w8, [sp, #8]
; CHECK: ldr w8, [sp, #8]
; CHECK: ; kill: def $x8 killed $w8
; CHECK: str x8, [sp]
; CHECK: ldr x0, [sp]
; CHECK: ret
%a.addr = alloca i8, align 1
@ -104,12 +105,12 @@ entry:
; CHECK: strh w1, [sp, #12]
; CHECK: str w2, [sp, #8]
; CHECK: str x3, [sp]
; CHECK: ldrsb [[REG0:w[0-9]+]], [sp, #15]
; CHECK: strh [[REG0]], [sp, #12]
; CHECK: ldrsh [[REG1:w[0-9]+]], [sp, #12]
; CHECK: str [[REG1]], [sp, #8]
; CHECK: ldrsw [[REG2:x[0-9]+]], [sp, #8]
; CHECK: str [[REG2]], [sp]
; CHECK: ldrsb w8, [sp, #15]
; CHECK: strh w8, [sp, #12]
; CHECK: ldrsh w8, [sp, #12]
; CHECK: str w8, [sp, #8]
; CHECK: ldrsw x8, [sp, #8]
; CHECK: str x8, [sp]
; CHECK: ldr x0, [sp]
; CHECK: ret
%a.addr = alloca i8, align 1
@ -165,8 +166,8 @@ entry:
define signext i16 @sext_i1_i16(i1 %a) nounwind ssp {
entry:
; CHECK-LABEL: sext_i1_i16
; CHECK: sbfx [[REG:w[0-9]+]], w0, #0, #1
; CHECK: sxth w0, [[REG]]
; CHECK: sbfx w8, w0, #0, #1
; CHECK-NEXT: sxth w0, w8
%conv = sext i1 %a to i16
ret i16 %conv
}
@ -175,8 +176,8 @@ entry:
define signext i8 @sext_i1_i8(i1 %a) nounwind ssp {
entry:
; CHECK-LABEL: sext_i1_i8
; CHECK: sbfx [[REG:w[0-9]+]], w0, #0, #1
; CHECK: sxtb w0, [[REG]]
; CHECK: sbfx w8, w0, #0, #1
; CHECK-NEXT: sxtb w0, w8
%conv = sext i1 %a to i8
ret i8 %conv
}
@ -239,8 +240,8 @@ entry:
define float @sitofp_sw_i1(i1 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_sw_i1
; CHECK: sbfx [[REG:w[0-9]+]], w0, #0, #1
; CHECK: scvtf s0, [[REG]]
; CHECK: sbfx w8, w0, #0, #1
; CHECK: scvtf s0, w8
%conv = sitofp i1 %a to float
ret float %conv
}
@ -249,8 +250,8 @@ entry:
define float @sitofp_sw_i8(i8 %a) nounwind ssp {
entry:
; CHECK-LABEL: sitofp_sw_i8
; CHECK: sxtb [[REG:w[0-9]+]], w0
; CHECK: scvtf s0, [[REG]]
; CHECK: sxtb w8, w0
; CHECK: scvtf s0, w8
%conv = sitofp i8 %a to float
ret float %conv
}
@ -303,8 +304,8 @@ entry:
define float @uitofp_sw_i1(i1 %a) nounwind ssp {
entry:
; CHECK-LABEL: uitofp_sw_i1
; CHECK: and [[REG:w[0-9]+]], w0, #0x1
; CHECK: ucvtf s0, [[REG]]
; CHECK: and w8, w0, #0x1
; CHECK: ucvtf s0, w8
%conv = uitofp i1 %a to float
ret float %conv
}
@ -373,8 +374,7 @@ entry:
define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: i64_trunc_i16
; CHECK: mov x[[TMP:[0-9]+]], x0
; CHECK: and [[REG2:w[0-9]+]], w[[TMP]], #0xffff{{$}}
; CHECK: and [[REG2:w[0-9]+]], w0, #0xffff
; CHECK: uxth w0, [[REG2]]
%conv = trunc i64 %a to i16
ret i16 %conv
@ -383,8 +383,7 @@ entry:
define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: i64_trunc_i8
; CHECK: mov x[[TMP:[0-9]+]], x0
; CHECK: and [[REG2:w[0-9]+]], w[[TMP]], #0xff{{$}}
; CHECK: and [[REG2:w[0-9]+]], w0, #0xff
; CHECK: uxtb w0, [[REG2]]
%conv = trunc i64 %a to i8
ret i8 %conv
@ -393,8 +392,7 @@ entry:
define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {
entry:
; CHECK-LABEL: i64_trunc_i1
; CHECK: mov x[[TMP:[0-9]+]], x0
; CHECK: and [[REG2:w[0-9]+]], w[[TMP]], #0x1{{$}}
; CHECK: and [[REG2:w[0-9]+]], w0, #0x1
; CHECK: and w0, [[REG2]], #0x1
%conv = trunc i64 %a to i1
ret i1 %conv

23
llvm/test/CodeGen/AArch64/arm64-vcvt_f.ll
View File

@ -210,10 +210,10 @@ define <4 x float> @test_vcvt_high_f32_f64(<2 x float> %x, <2 x double> %v) noun
;
; FAST-LABEL: test_vcvt_high_f32_f64:
; FAST: // %bb.0:
; FAST-NEXT: // implicit-def: $q2
; FAST-NEXT: mov.16b v2, v0
; FAST-NEXT: // implicit-def: $q0
; FAST-NEXT: fcvtn2 v2.4s, v1.2d
; FAST-NEXT: mov.16b v0, v2
; FAST-NEXT: fcvtn2 v0.4s, v1.2d
; FAST-NEXT: ret
;
; GISEL-LABEL: test_vcvt_high_f32_f64:
@ -249,10 +249,10 @@ define <4 x float> @test_vcvtx_high_f32_f64(<2 x float> %x, <2 x double> %v) nou
;
; FAST-LABEL: test_vcvtx_high_f32_f64:
; FAST: // %bb.0:
; FAST-NEXT: // implicit-def: $q2
; FAST-NEXT: mov.16b v2, v0
; FAST-NEXT: // implicit-def: $q0
; FAST-NEXT: fcvtxn2 v2.4s, v1.2d
; FAST-NEXT: mov.16b v0, v2
; FAST-NEXT: fcvtxn2 v0.4s, v1.2d
; FAST-NEXT: ret
;
; GISEL-LABEL: test_vcvtx_high_f32_f64:
@ -283,12 +283,17 @@ define i16 @to_half(float %in) {
;
; FAST-LABEL: to_half:
; FAST: // %bb.0:
; FAST-NEXT: fcvt h1, s0
; FAST-NEXT: sub sp, sp, #16 // =16
; FAST-NEXT: .cfi_def_cfa_offset 16
; FAST-NEXT: fcvt h0, s0
; FAST-NEXT: // implicit-def: $w0
; FAST-NEXT: fmov s0, w0
; FAST-NEXT: mov.16b v0, v1
; FAST-NEXT: fmov w0, s0
; FAST-NEXT: // kill: def $w1 killed $w0
; FAST-NEXT: fmov s1, w0
; FAST-NEXT: mov.16b v1, v0
; FAST-NEXT: fmov w8, s1
; FAST-NEXT: mov w0, w8
; FAST-NEXT: str w0, [sp, #12] // 4-byte Folded Spill
; FAST-NEXT: mov w0, w8
; FAST-NEXT: add sp, sp, #16 // =16
; FAST-NEXT: ret
;
; GISEL-LABEL: to_half:

5
llvm/test/CodeGen/AArch64/arm64_32-fastisel.ll
View File

@ -17,9 +17,8 @@ declare [2 x i32] @callee()
define void @test_struct_return(i32* %addr) {
; CHECK-LABEL: test_struct_return:
; CHECK: bl _callee
; CHECK: x[[COPYX0:[0-9]+]], x0
; CHECK-DAG: lsr [[HI:x[0-9]+]], x[[COPYX0]], #32
; CHECK-DAG: str w[[COPYX0]]
; CHECK-DAG: lsr [[HI:x[0-9]+]], x0, #32
; CHECK-DAG: str w0
%res = call [2 x i32] @callee()
%res.0 = extractvalue [2 x i32] %res, 0
store i32 %res.0, i32* %addr

7
llvm/test/CodeGen/AArch64/arm64_32-null.ll
View File

@ -13,12 +13,11 @@ define void @test_store(i8** %p) {
define void @test_phi(i8** %p) {
; CHECK-LABEL: test_phi:
; CHECK: mov [[R1:x[0-9]+]], xzr
; CHECK: str [[R1]], [sp, #8]
; CHECK: str [[R1]], [sp]
; CHECK: b [[BB:LBB[0-9_]+]]
; CHECK: [[BB]]:
; CHECK: ldr x0, [sp, #8]
; CHECK: mov w8, w0
; CHECK: str w8, [x{{.*}}]
; CHECK: ldr x0, [sp]
; CHECK: str w0, [x{{.*}}]
bb0:
br label %bb1

2
llvm/test/CodeGen/AArch64/br-cond-not-merge.ll
View File

@ -64,9 +64,9 @@ bb3:
; OPT: b.gt [[L:\.LBB[0-9_]+]]
; OPT: tbz w1, #0, [[L]]
;
; NOOPT: str w1, [sp, #[[SLOT2:[0-9]+]]]
; NOOPT: subs w{{[0-9]+}}, w{{[0-9]+}}, #0
; NOOPT: cset [[R1:w[0-9]+]], gt
; NOOPT: str w1, [sp, #[[SLOT2:[0-9]+]]]
; NOOPT: str [[R1]], [sp, #[[SLOT1:[0-9]+]]]
; NOOPT: b .LBB
; NOOPT: ldr [[R2:w[0-9]+]], [sp, #[[SLOT1]]]

38
llvm/test/CodeGen/AArch64/cmpxchg-O0.ll
View File

@ -1,16 +1,16 @@
; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -O0 -fast-isel=0 -global-isel=false %s -o - | FileCheck -enable-var-scope %s
; RUN: llc -verify-machineinstrs -mtriple=aarch64-linux-gnu -O0 -fast-isel=0 -global-isel=false %s -o - | FileCheck %s
define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_8:
; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxrb [[OLD:w[0-9]+]], {{\[}}[[ADDR]]{{\]}}
; CHECK: mov [[STATUS:w[3-9]+]], #0
; CHECK: ldaxrb [[OLD:w[0-9]+]], [x0]
; CHECK: cmp [[OLD]], w1, uxtb
; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: stlxrb [[STATUS:w[0-9]+]], w2, {{\[}}[[ADDR]]{{\]}}
; CHECK: stlxrb [[STATUS]], w2, [x0]
; CHECK: cbnz [[STATUS]], [[RETRY]]
; CHECK: [[DONE]]:
; CHECK: subs {{w[0-9]+}}, [[OLD]], w1, uxtb
; CHECK: subs {{w[0-9]+}}, [[OLD]], w1
; CHECK: cset {{w[0-9]+}}, eq
%res = cmpxchg i8* %addr, i8 %desired, i8 %new seq_cst monotonic
ret { i8, i1 } %res
@ -18,12 +18,12 @@ define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind {
define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_16:
; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxrh [[OLD:w[0-9]+]], {{\[}}[[ADDR]]{{\]}}
; CHECK: mov [[STATUS:w[3-9]+]], #0
; CHECK: ldaxrh [[OLD:w[0-9]+]], [x0]
; CHECK: cmp [[OLD]], w1, uxth
; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: stlxrh [[STATUS:w[3-9]]], w2, {{\[}}[[ADDR]]{{\]}}
; CHECK: stlxrh [[STATUS:w[3-9]]], w2, [x0]
; CHECK: cbnz [[STATUS]], [[RETRY]]
; CHECK: [[DONE]]:
; CHECK: subs {{w[0-9]+}}, [[OLD]], w1
@ -34,12 +34,12 @@ define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind
define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_32:
; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxr [[OLD:w[0-9]+]], {{\[}}[[ADDR]]{{\]}}
; CHECK: mov [[STATUS:w[3-9]+]], #0
; CHECK: ldaxr [[OLD:w[0-9]+]], [x0]
; CHECK: cmp [[OLD]], w1
; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: stlxr [[STATUS:w[0-9]+]], w2, {{\[}}[[ADDR]]{{\]}}
; CHECK: stlxr [[STATUS]], w2, [x0]
; CHECK: cbnz [[STATUS]], [[RETRY]]
; CHECK: [[DONE]]:
; CHECK: subs {{w[0-9]+}}, [[OLD]], w1
@ -50,12 +50,12 @@ define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind
define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_64:
; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxr [[OLD:x[0-9]+]], {{\[}}[[ADDR]]{{\]}}
; CHECK: mov [[STATUS:w[3-9]+]], #0
; CHECK: ldaxr [[OLD:x[0-9]+]], [x0]
; CHECK: cmp [[OLD]], x1
; CHECK: b.ne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: stlxr [[STATUS:w[0-9]+]], x2, {{\[}}[[ADDR]]{{\]}}
; CHECK: stlxr [[STATUS]], x2, [x0]
; CHECK: cbnz [[STATUS]], [[RETRY]]
; CHECK: [[DONE]]:
; CHECK: subs {{x[0-9]+}}, [[OLD]], x1
@ -66,15 +66,14 @@ define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind
define { i128, i1 } @test_cmpxchg_128(i128* %addr, i128 %desired, i128 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_128:
; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], {{\[}}[[ADDR]]{{\]}}
; CHECK: ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], [x0]
; CHECK: cmp [[OLD_LO]], x2
; CHECK: cset [[CMP_TMP:w[0-9]+]], ne
; CHECK: cmp [[OLD_HI]], x3
; CHECK: cinc [[CMP:w[0-9]+]], [[CMP_TMP]], ne
; CHECK: cbnz [[CMP]], [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: stlxp [[STATUS:w[0-9]+]], x4, x5, {{\[}}[[ADDR]]{{\]}}
; CHECK: stlxp [[STATUS:w[0-9]+]], x4, x5, [x0]
; CHECK: cbnz [[STATUS]], [[RETRY]]
; CHECK: [[DONE]]:
%res = cmpxchg i128* %addr, i128 %desired, i128 %new seq_cst monotonic
@ -87,18 +86,17 @@ define { i128, i1 } @test_cmpxchg_128(i128* %addr, i128 %desired, i128 %new) nou
@var128 = global i128 0
define {i128, i1} @test_cmpxchg_128_unsplit(i128* %addr) {
; CHECK-LABEL: test_cmpxchg_128_unsplit:
; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: add x[[VAR128:[0-9]+]], {{x[0-9]+}}, :lo12:var128
; CHECK: ldp [[DESIRED_LO:x[0-9]+]], [[DESIRED_HI:x[0-9]+]], [x[[VAR128]]]
; CHECK: ldp [[NEW_LO:x[0-9]+]], [[NEW_HI:x[0-9]+]], [x[[VAR128]]]
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], {{\[}}[[ADDR]]{{\]}}
; CHECK: ldaxp [[OLD_LO:x[0-9]+]], [[OLD_HI:x[0-9]+]], [x0]
; CHECK: cmp [[OLD_LO]], [[DESIRED_LO]]
; CHECK: cset [[CMP_TMP:w[0-9]+]], ne
; CHECK: cmp [[OLD_HI]], [[DESIRED_HI]]
; CHECK: cinc [[CMP:w[0-9]+]], [[CMP_TMP]], ne
; CHECK: cbnz [[CMP]], [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: stlxp [[STATUS:w[0-9]+]], [[NEW_LO]], [[NEW_HI]], {{\[}}[[ADDR]]{{\]}}
; CHECK: stlxp [[STATUS:w[0-9]+]], [[NEW_LO]], [[NEW_HI]], [x0]
; CHECK: cbnz [[STATUS]], [[RETRY]]
; CHECK: [[DONE]]:

8
llvm/test/CodeGen/AArch64/combine-loads.ll
View File

@ -6,10 +6,10 @@ define <2 x i64> @z(i64* nocapture nonnull readonly %p) {
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI0_0
; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI0_0]
; CHECK-NEXT: ldr x9, [x0]
; CHECK-NEXT: ldr x8, [x0, #8]
; CHECK-NEXT: mov v0.d[0], x9
; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: ldr x9, [x0, #8]
; CHECK-NEXT: mov v0.d[0], x8
; CHECK-NEXT: mov v0.d[1], x9
; CHECK-NEXT: ret
%b = load i64, i64* %p
%p2 = getelementptr i64, i64* %p, i64 1

39
llvm/test/CodeGen/AArch64/fast-isel-cmpxchg.ll
View File

@ -1,19 +1,20 @@
; RUN: llc -mtriple=aarch64-- -O0 -fast-isel -fast-isel-abort=4 -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: cmpxchg_monotonic_32:
; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9_]+]]:
; CHECK-NEXT: ldaxr w0, {{\[}}[[ADDR]]{{\]}}
; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: mov [[STATUS:w[0-9]+]], #0
; CHECK-NEXT: ldaxr [[OLD:w[0-9]+]], [x0]
; CHECK-NEXT: cmp [[OLD]], w1
; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]]
; CHECK-NEXT: // %bb.2:
; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], w2, {{\[}}[[ADDR]]{{\]}}
; CHECK-NEXT: stlxr [[STATUS]], w2, [x0]
; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]]
; CHECK-NEXT: [[DONE]]:
; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: cset [[STATUS]], eq
; CHECK-NEXT: cmp [[OLD]], w1
; CHECK-NEXT: cset [[STATUS:w[0-9]+]], eq
; CHECK-NEXT: and [[STATUS32:w[0-9]+]], [[STATUS]], #0x1
; CHECK-NEXT: str [[STATUS32]], [x3]
; CHECK-NEXT: mov w0, [[OLD]]
define i32 @cmpxchg_monotonic_32(i32* %p, i32 %cmp, i32 %new, i32* %ps) #0 {
%tmp0 = cmpxchg i32* %p, i32 %cmp, i32 %new monotonic monotonic
%tmp1 = extractvalue { i32, i1 } %tmp0, 0
@ -25,20 +26,21 @@ define i32 @cmpxchg_monotonic_32(i32* %p, i32 %cmp, i32 %new, i32* %ps) #0 {
; CHECK-LABEL: cmpxchg_acq_rel_32_load:
; CHECK: // %bb.0:
; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: ldr [[NEW:w[0-9]+]], [x2]
; CHECK: ldr [[NEW:w[0-9]+]], [x2]
; CHECK-NEXT: [[RETRY:.LBB[0-9_]+]]:
; CHECK-NEXT: ldaxr w0, {{\[}}[[ADDR]]{{\]}}
; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: mov [[STATUS:w[0-9]+]], #0
; CHECK-NEXT: ldaxr [[OLD:w[0-9]+]], [x0]
; CHECK-NEXT: cmp [[OLD]], w1
; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]]
; CHECK-NEXT: // %bb.2:
; CHECK-NEXT: stlxr [[STATUS:w[0-9]+]], [[NEW]], {{\[}}[[ADDR]]{{\]}}
; CHECK-NEXT: stlxr [[STATUS]], [[NEW]], [x0]
; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]]
; CHECK-NEXT: [[DONE]]:
; CHECK-NEXT: cmp w0, w1
; CHECK-NEXT: cset [[STATUS]], eq
; CHECK-NEXT: cmp [[OLD]], w1
; CHECK-NEXT: cset [[STATUS:w[0-9]+]], eq
; CHECK-NEXT: and [[STATUS32:w[0-9]+]], [[STATUS]], #0x1
; CHECK-NEXT: str [[STATUS32]], [x3]
; CHECK-NEXT: mov w0, [[OLD]]
define i32 @cmpxchg_acq_rel_32_load(i32* %p, i32 %cmp, i32* %pnew, i32* %ps) #0 {
%new = load i32, i32* %pnew
%tmp0 = cmpxchg i32* %p, i32 %cmp, i32 %new acq_rel acquire
@ -50,19 +52,20 @@ define i32 @cmpxchg_acq_rel_32_load(i32* %p, i32 %cmp, i32* %pnew, i32* %ps) #0
}
; CHECK-LABEL: cmpxchg_seq_cst_64:
; CHECK: mov [[ADDR:x[0-9]+]], x0
; CHECK: [[RETRY:.LBB[0-9_]+]]:
; CHECK-NEXT: ldaxr x0, {{\[}}[[ADDR]]{{\]}}
; CHECK-NEXT: cmp x0, x1
; CHECK-NEXT: mov [[STATUS:w[0-9]+]], #0
; CHECK-NEXT: ldaxr [[OLD:x[0-9]+]], [x0]
; CHECK-NEXT: cmp [[OLD]], x1
; CHECK-NEXT: b.ne [[DONE:.LBB[0-9_]+]]
; CHECK-NEXT: // %bb.2:
; CHECK-NEXT: stlxr [[STATUS]], x2, {{\[}}[[ADDR]]{{\]}}
; CHECK-NEXT: stlxr [[STATUS]], x2, [x0]
; CHECK-NEXT: cbnz [[STATUS]], [[RETRY]]
; CHECK-NEXT: [[DONE]]:
; CHECK-NEXT: cmp x0, x1
; CHECK-NEXT: cmp [[OLD]], x1
; CHECK-NEXT: cset [[STATUS:w[0-9]+]], eq
; CHECK-NEXT: and [[STATUS32:w[0-9]+]], [[STATUS]], #0x1
; CHECK-NEXT: str [[STATUS32]], [x3]
; CHECK-NEXT: mov x0, [[OLD]]
define i64 @cmpxchg_seq_cst_64(i64* %p, i64 %cmp, i64 %new, i32* %ps) #0 {
%tmp0 = cmpxchg i64* %p, i64 %cmp, i64 %new seq_cst seq_cst
%tmp1 = extractvalue { i64, i1 } %tmp0, 0

62
llvm/test/CodeGen/AArch64/popcount.ll
View File

@ -6,15 +6,15 @@ define i8 @popcount128(i128* nocapture nonnull readonly %0) {
; CHECK-LABEL: popcount128:
; CHECK: // %bb.0: // %Entry
; CHECK-NEXT: ldr x8, [x0, #8]
; CHECK-NEXT: ldr d1, [x0]
; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: uaddlv h1, v0.16b
; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: // implicit-def: $q1
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov v1.d[1], x8
; CHECK-NEXT: cnt v0.16b, v1.16b
; CHECK-NEXT: uaddlv h0, v0.16b
; CHECK-NEXT: // implicit-def: $q1
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: ret
Entry:
%1 = load i128, i128* %0, align 16
@ -32,24 +32,24 @@ define i16 @popcount256(i256* nocapture nonnull readonly %0) {
; CHECK: // %bb.0: // %Entry
; CHECK-NEXT: ldr x8, [x0, #8]
; CHECK-NEXT: ldr x9, [x0, #24]
; CHECK-NEXT: ldr d1, [x0, #16]
; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: mov v0.d[1], x9
; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: uaddlv h1, v0.16b
; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: ldr d1, [x0]
; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: uaddlv h1, v0.16b
; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: ldr d0, [x0, #16]
; CHECK-NEXT: // implicit-def: $q1
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov v1.d[1], x9
; CHECK-NEXT: cnt v0.16b, v1.16b
; CHECK-NEXT: uaddlv h0, v0.16b
; CHECK-NEXT: // implicit-def: $q1
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: fmov w9, s1
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: // implicit-def: $q1
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: mov v1.d[1], x8
; CHECK-NEXT: cnt v0.16b, v1.16b
; CHECK-NEXT: uaddlv h0, v0.16b
; CHECK-NEXT: // implicit-def: $q1
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: fmov w8, s1
; CHECK-NEXT: add w0, w8, w9
; CHECK-NEXT: ret
Entry:
@ -69,10 +69,10 @@ define <1 x i128> @popcount1x128(<1 x i128> %0) {
; CHECK-NEXT: fmov d0, x0
; CHECK-NEXT: mov v0.d[1], x1
; CHECK-NEXT: cnt v0.16b, v0.16b
; CHECK-NEXT: uaddlv h1, v0.16b
; CHECK-NEXT: // implicit-def: $q0
; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: fmov w0, s0
; CHECK-NEXT: uaddlv h0, v0.16b
; CHECK-NEXT: // implicit-def: $q1
; CHECK-NEXT: mov v1.16b, v0.16b
; CHECK-NEXT: fmov w0, s1
; CHECK-NEXT: // kill: def $x0 killed $w0
; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: mov x1, v0.d[1]

16
llvm/test/CodeGen/AArch64/swift-return.ll
View File

@ -203,10 +203,10 @@ declare swiftcc { double, double, double, double, i32, i32, i32, i32 } @gen6()
; CHECK-DAG: mov w3, w0
; CHECK: ret
; CHECK-O0-LABEL: _gen7
; CHECK-O0: mov w3, w0
; CHECK-O0: mov w0, w3
; CHECK-O0: mov w1, w3
; CHECK-O0: mov w2, w3
; CHECK-O0: str w0, [sp, #12]
; CHECK-O0: ldr w1, [sp, #12]
; CHECK-O0: ldr w2, [sp, #12]
; CHECK-O0: ldr w3, [sp, #12]
define swiftcc { i32, i32, i32, i32 } @gen7(i32 %key) {
%v0 = insertvalue { i32, i32, i32, i32 } undef, i32 %key, 0
%v1 = insertvalue { i32, i32, i32, i32 } %v0, i32 %key, 1
@ -221,10 +221,10 @@ define swiftcc { i32, i32, i32, i32 } @gen7(i32 %key) {
; CHECK: mov w3, w0
; CHECK: ret
; CHECK-O0-LABEL: _gen9
; CHECK-O0: mov w3, w0
; CHECK-O0: mov w0, w3
; CHECK-O0: mov w1, w3
; CHECK-O0: mov w2, w3
; CHECK-O0: str w0, [sp, #12]
; CHECK-O0: ldr w1, [sp, #12]
; CHECK-O0: ldr w2, [sp, #12]
; CHECK-O0: ldr w3, [sp, #12]
define swiftcc { i8, i8, i8, i8 } @gen9(i8 %key) {
%v0 = insertvalue { i8, i8, i8, i8 } undef, i8 %key, 0
%v1 = insertvalue { i8, i8, i8, i8 } %v0, i8 %key, 1

45
llvm/test/CodeGen/AArch64/swifterror.ll
View File

@ -21,10 +21,11 @@ define float @foo(%swift_error** swifterror %error_ptr_ref) {
; CHECK-O0-LABEL: foo:
; CHECK-O0: mov w{{.*}}, #16
; CHECK-O0: malloc
; CHECK-O0: mov x21, x0
; CHECK-O0-NOT: x21
; CHECK-O0: mov x1, x0
; CHECK-O0-NOT: x1
; CHECK-O0: mov [[ID:w[0-9]+]], #1
; CHECK-O0: strb [[ID]], [x0, #8]
; CHECK-O0: mov x21, x1
entry:
%call = call i8* @malloc(i64 16)
%call.0 = bitcast i8* %call to %swift_error*
@ -137,12 +138,14 @@ define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) {
; CHECK-O0: cbz w0
; CHECK-O0: mov w{{.*}}, #16
; CHECK-O0: malloc
; CHECK-O0: mov x21, x0
; CHECK-O0: mov [[ID:x[0-9]+]], x0
; CHECK-O0: mov [[ID2:w[0-9]+]], #1
; CHECK-O0: strb [[ID2]], [x0, #8]
; CHECK-O0: mov x21, [[ID]]
; CHECK-O0: ret
; reload from stack
; CHECK-O0: ldr x21, [sp, [[SLOT]]]
; CHECK-O0: ldr [[ID3:x[0-9]+]], [sp, [[SLOT]]]
; CHECK-O0: mov x21, [[ID3]]
; CHECK-O0: ret
entry:
%cond = icmp ne i32 %cc, 0
@ -176,10 +179,10 @@ define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float
; CHECK-O0-AARCH64-LABEL: foo_loop:
; spill x21
; CHECK-O0-AARCH64: stur x21, [x29, [[SLOT:#-[0-9]+]]]
; CHECK-O0-AARCH64: str x21, [sp, [[SLOT:#[0-9]+]]]
; CHECK-O0-AARCH64: b [[BB1:[A-Za-z0-9_]*]]
; CHECK-O0-AARCH64: [[BB1]]:
; CHECK-O0-AARCH64: ldur x0, [x29, [[SLOT]]]
; CHECK-O0-AARCH64: ldr x0, [sp, [[SLOT]]]
; CHECK-O0-AARCH64: str x0, [sp, [[SLOT2:#[0-9]+]]]
; CHECK-O0-AARCH64: cbz {{.*}}, [[BB2:[A-Za-z0-9_]*]]
; CHECK-O0-AARCH64: mov w{{.*}}, #16
@ -191,10 +194,11 @@ define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float
; CHECK-O0-AARCH64:[[BB2]]:
; CHECK-O0-AARCH64: ldr x0, [sp, [[SLOT2]]]
; CHECK-O0-AARCH64: fcmp
; CHECK-O0-AARCH64: stur x0, [x29, [[SLOT]]]
; CHECK-O0-AARCH64: str x0, [sp]
; CHECK-O0-AARCH64: b.le [[BB1]]
; reload from stack
; CHECK-O0-AARCH64: ldr x21, [sp]
; CHECK-O0-AARCH64: ldr [[ID3:x[0-9]+]], [sp]
; CHECK-O0-AARCH64: mov x21, [[ID3]]
; CHECK-O0-AARCH64: ret
; CHECK-O0-ARM64_32-LABEL: foo_loop:
@ -211,12 +215,14 @@ define float @foo_loop(%swift_error** swifterror %error_ptr_ref, i32 %cc, float
; CHECK-O0-ARM64_32: strb w{{.*}},
; CHECK-O0-ARM64_32:[[BB2]]:
; CHECK-O0-ARM64_32: ldr x0, [sp, [[SLOT2]]]
; CHECK-O0-ARM64_32: str x0, [sp[[OFFSET:.*]]]
; CHECK-O0-ARM64_32: fcmp
; CHECK-O0-ARM64_32: str x0, [sp[[OFFSET:.*]]]
; CHECK-O0-ARM64_32: b.le [[BB1]]
; reload from stack
; CHECK-O0-ARM64_32: ldr x21, [sp[[OFFSET]]]
; CHECK-O0-ARM64_32: ldr [[ID3:x[0-9]+]], [sp[[OFFSET]]]
; CHECK-O0-ARM64_32: mov x21, [[ID3]]
; CHECK-O0-ARM64_32: ret
entry:
br label %bb_loop
@ -255,16 +261,16 @@ define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swi
; CHECK-APPLE-NOT: x21
; CHECK-O0-LABEL: foo_sret:
; CHECK-O0: mov w{{.*}}, #16
; spill x8
; CHECK-O0-DAG: str x8
; CHECK-O0: mov w{{.*}}, #16
; CHECK-O0: malloc
; CHECK-O0: mov x10, x0
; CHECK-O0: mov x21, x10
; CHECK-O0: mov [[ID:w[0-9]+]], #1
; CHECK-O0: strb [[ID]], [x10, #8]
; CHECK-O0: strb [[ID]], [x0, #8]
; reload from stack
; CHECK-O0: str w{{.*}}, [x8, #4]
; CHECK-O0: ldr [[SRET:x[0-9]+]]
; CHECK-O0: str w{{.*}}, [{{.*}}[[SRET]], #4]
; CHECK-O0: mov x21
; CHECK-O0-NOT: x21
entry:
%call = call i8* @malloc(i64 16)
@ -293,7 +299,7 @@ define float @caller3(i8* %error_ref) {
; CHECK-O0-LABEL: caller3:
; spill x0
; CHECK-O0: str x0, [sp, [[OFFSET:#[0-9]+]]]
; CHECK-O0: str x0
; CHECK-O0: mov x21
; CHECK-O0: bl {{.*}}foo_sret
; CHECK-O0: mov [[ID2:x[0-9]+]], x21
@ -301,8 +307,8 @@ define float @caller3(i8* %error_ref) {
; CHECK-O0-ARM64_32: cmp x21, #0
; Access part of the error object and save it to error_ref
; reload from stack
; CHECK-O0: ldr [[ID:x[0-9]+]], [sp, [[OFFSET]]]
; CHECK-O0: ldrb [[CODE:w[0-9]+]]
; CHECK-O0: ldr [[ID:x[0-9]+]]
; CHECK-O0: strb [[CODE]], [{{.*}}[[ID]]]
; CHECK-O0: bl {{.*}}free
entry:
@ -624,10 +630,11 @@ declare swiftcc void @foo2(%swift_error** swifterror)
; Make sure we properly assign registers during fast-isel.
; CHECK-O0-LABEL: testAssign
; CHECK-O0: mov x21, xzr
; CHECK-O0: mov [[TMP:x.*]], xzr
; CHECK-O0: mov x21, [[TMP]]
; CHECK-O0: bl _foo2
; CHECK-O0: str x21, [s[[STK:.*]]]
; CHECK-O0: ldr x{{[0-9]+}}, [s[[STK]]]
; CHECK-O0: ldr x0, [s[[STK]]]
; CHECK-APPLE-LABEL: testAssign
; CHECK-APPLE: mov x21, xzr

10
llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
View File

@ -81,14 +81,14 @@ body: |
; CHECK: frame-setup CFI_INSTRUCTION offset $b21, -240
; CHECK: frame-setup CFI_INSTRUCTION offset $b22, -256
; CHECK: frame-setup CFI_INSTRUCTION offset $b23, -272
; CHECK: STRQui $q0, $sp, 0 :: (store 16 into %stack.1)
; CHECK: EH_LABEL <mcsymbol .Ltmp0>
; CHECK: BL @may_throw_neon, csr_aarch64_aavpcs, implicit-def dead $lr, implicit $sp, implicit killed $q0, implicit-def $q0
; CHECK: STRQui killed $q0, $sp, 1 :: (store 16 into %stack.0)
; CHECK: STRQui $q0, $sp, 1 :: (store 16 into %stack.0)
; CHECK: BL @may_throw_neon, csr_aarch64_aavpcs, implicit-def $lr, implicit $sp, implicit killed $q0, implicit-def $q0
; CHECK: EH_LABEL <mcsymbol .Ltmp1>
; CHECK: STRQui killed $q0, $sp, 0 :: (store 16 into %stack.1)
; CHECK: B %bb.1
; CHECK: bb.1..Lcontinue:
; CHECK: $q0 = LDRQui $sp, 1 :: (load 16 from %stack.0)
; CHECK: $q0 = LDRQui $sp, 0 :: (load 16 from %stack.1)
; CHECK: $fp, $lr = frame-destroy LDPXi $sp, 36 :: (load 8 from %stack.3), (load 8 from %stack.2)
; CHECK: $q9, $q8 = frame-destroy LDPQi $sp, 16 :: (load 16 from %stack.5), (load 16 from %stack.4)
; CHECK: $q11, $q10 = frame-destroy LDPQi $sp, 14 :: (load 16 from %stack.7), (load 16 from %stack.6)
@ -103,7 +103,7 @@ body: |
; CHECK: bb.2..Lunwind (landing-pad):
; CHECK: liveins: $x0, $x1
; CHECK: EH_LABEL <mcsymbol .Ltmp2>
; CHECK: $q0 = LDRQui $sp, 0 :: (load 16 from %stack.1)
; CHECK: $q0 = LDRQui $sp, 1 :: (load 16 from %stack.0)
; CHECK: $fp, $lr = frame-destroy LDPXi $sp, 36 :: (load 8 from %stack.3), (load 8 from %stack.2)
; CHECK: $q9, $q8 = frame-destroy LDPQi $sp, 16 :: (load 16 from %stack.5), (load 16 from %stack.4)
; CHECK: $q11, $q10 = frame-destroy LDPQi $sp, 14 :: (load 16 from %stack.7), (load 16 from %stack.6)

32
llvm/test/CodeGen/AArch64/unwind-preserved.ll
View File

@ -50,14 +50,14 @@ define <vscale x 4 x i32> @invoke_callee_may_throw_sve(<vscale x 4 x i32> %v) pe
; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x40, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d15 @ cfa - 16 - 64 * VG
; CHECK-NEXT: .cfi_offset w30, -8
; CHECK-NEXT: .cfi_offset w29, -16
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: str z0, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: bl may_throw_sve
; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: str z0, [sp, #1, mul vl] // 16-byte Folded Spill
; CHECK-NEXT: str z0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: b .LBB0_1
; CHECK-NEXT: .LBB0_1: // %.Lcontinue
; CHECK-NEXT: ldr z0, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
@ -92,7 +92,7 @@ define <vscale x 4 x i32> @invoke_callee_may_throw_sve(<vscale x 4 x i32> %v) pe
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2: // %.Lunwind
; CHECK-NEXT: .Ltmp2:
; CHECK-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr z0, [sp, #1, mul vl] // 16-byte Folded Reload
; CHECK-NEXT: addvl sp, sp, #2
; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
@ -172,14 +172,14 @@ define <vscale x 4 x i32> @invoke_callee_may_throw_sve(<vscale x 4 x i32> %v) pe
; GISEL-NEXT: .cfi_escape 0x10, 0x4f, 0x0a, 0x11, 0x70, 0x22, 0x11, 0x40, 0x92, 0x2e, 0x00, 0x1e, 0x22 // $d15 @ cfa - 16 - 64 * VG
; GISEL-NEXT: .cfi_offset w30, -8
; GISEL-NEXT: .cfi_offset w29, -16
; GISEL-NEXT: str z0, [sp] // 16-byte Folded Spill
; GISEL-NEXT: .Ltmp0:
; GISEL-NEXT: str z0, [sp, #1, mul vl] // 16-byte Folded Spill
; GISEL-NEXT: bl may_throw_sve
; GISEL-NEXT: .Ltmp1:
; GISEL-NEXT: str z0, [sp, #1, mul vl] // 16-byte Folded Spill
; GISEL-NEXT: str z0, [sp] // 16-byte Folded Spill
; GISEL-NEXT: b .LBB0_1
; GISEL-NEXT: .LBB0_1: // %.Lcontinue
; GISEL-NEXT: ldr z0, [sp, #1, mul vl] // 16-byte Folded Reload
; GISEL-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; GISEL-NEXT: addvl sp, sp, #2
; GISEL-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; GISEL-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
@ -214,7 +214,7 @@ define <vscale x 4 x i32> @invoke_callee_may_throw_sve(<vscale x 4 x i32> %v) pe
; GISEL-NEXT: ret
; GISEL-NEXT: .LBB0_2: // %.Lunwind
; GISEL-NEXT: .Ltmp2:
; GISEL-NEXT: ldr z0, [sp] // 16-byte Folded Reload
; GISEL-NEXT: ldr z0, [sp, #1, mul vl] // 16-byte Folded Reload
; GISEL-NEXT: addvl sp, sp, #2
; GISEL-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Folded Reload
; GISEL-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Folded Reload
@ -293,14 +293,14 @@ define aarch64_vector_pcs <4 x i32> @invoke_callee_may_throw_neon(<4 x i32> %v)
; CHECK-NEXT: .cfi_offset b21, -240
; CHECK-NEXT: .cfi_offset b22, -256
; CHECK-NEXT: .cfi_offset b23, -272
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: .Ltmp3:
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: bl may_throw_neon
; CHECK-NEXT: .Ltmp4:
; CHECK-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
; CHECK-NEXT: b .LBB1_1
; CHECK-NEXT: .LBB1_1: // %.Lcontinue
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldp x29, x30, [sp, #288] // 16-byte Folded Reload
; CHECK-NEXT: ldp q9, q8, [sp, #256] // 32-byte Folded Reload
; CHECK-NEXT: ldp q11, q10, [sp, #224] // 32-byte Folded Reload
@ -314,7 +314,7 @@ define aarch64_vector_pcs <4 x i32> @invoke_callee_may_throw_neon(<4 x i32> %v)
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2: // %.Lunwind
; CHECK-NEXT: .Ltmp5:
; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; CHECK-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; CHECK-NEXT: ldp x29, x30, [sp, #288] // 16-byte Folded Reload
; CHECK-NEXT: ldp q9, q8, [sp, #256] // 32-byte Folded Reload
; CHECK-NEXT: ldp q11, q10, [sp, #224] // 32-byte Folded Reload
@ -360,13 +360,13 @@ define aarch64_vector_pcs <4 x i32> @invoke_callee_may_throw_neon(<4 x i32> %v)
; GISEL-NEXT: .cfi_offset b21, -240
; GISEL-NEXT: .cfi_offset b22, -256
; GISEL-NEXT: .cfi_offset b23, -272
; GISEL-NEXT: str q0, [sp] // 16-byte Folded Spill
; GISEL-NEXT: .Ltmp3:
; GISEL-NEXT: bl may_throw_neon
; GISEL-NEXT: str q0, [sp, #16] // 16-byte Folded Spill
; GISEL-NEXT: bl may_throw_neon
; GISEL-NEXT: .Ltmp4:
; GISEL-NEXT: str q0, [sp] // 16-byte Folded Spill
; GISEL-NEXT: // %bb.1: // %.Lcontinue
; GISEL-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; GISEL-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; GISEL-NEXT: ldp x29, x30, [sp, #288] // 16-byte Folded Reload
; GISEL-NEXT: ldp q9, q8, [sp, #256] // 32-byte Folded Reload
; GISEL-NEXT: ldp q11, q10, [sp, #224] // 32-byte Folded Reload
@ -380,7 +380,7 @@ define aarch64_vector_pcs <4 x i32> @invoke_callee_may_throw_neon(<4 x i32> %v)
; GISEL-NEXT: ret
; GISEL-NEXT: .LBB1_2: // %.Lunwind
; GISEL-NEXT: .Ltmp5:
; GISEL-NEXT: ldr q0, [sp] // 16-byte Folded Reload
; GISEL-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload
; GISEL-NEXT: ldp x29, x30, [sp, #288] // 16-byte Folded Reload
; GISEL-NEXT: ldp q9, q8, [sp, #256] // 32-byte Folded Reload
; GISEL-NEXT: ldp q11, q10, [sp, #224] // 32-byte Folded Reload

8
llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm.ll
View File

@ -28,15 +28,15 @@ define i32 @test_sgpr_matching_constraint() nounwind {
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: s_mov_b32 s5, 7
; CHECK-NEXT: s_mov_b32 s4, 7
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: s_mov_b32 s4, 8
; CHECK-NEXT: s_mov_b32 s5, 8
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: s_add_u32 s4, s5, s4
; CHECK-NEXT: s_add_u32 s5, s4, s5
; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: v_mov_b32_e32 v0, s4
; CHECK-NEXT: v_mov_b32_e32 v0, s5
; CHECK-NEXT: s_setpc_b64 s[30:31]
entry:
%asm0 = tail call i32 asm "s_mov_b32 $0, 7", "=s"() nounwind

54
llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
View File

@ -17,28 +17,29 @@
; GCN: s_mov_b32 m0, -1
; GCN: ds_read_b32 [[LOAD0:v[0-9]+]]
; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], s{{[0-9]+}}, v0
; GCN: s_mov_b64 s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, exec
; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]{{\]}}, [[CMP0]]
; Spill load
; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], s{{[0-9]+}}, v0
; Spill saved exec
; GCN: s_mov_b64 s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, exec
; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0
; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1
; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:20 ; 4-byte Folded Spill
; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]{{\]}}, [[CMP0]]
; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}}
; GCN: s_cbranch_execz [[ENDIF:BB[0-9]+_[0-9]+]]
; GCN: ; %bb.{{[0-9]+}}: ; %if
; GCN: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
; GCN: s_mov_b32 m0, -1
; GCN: ds_read_b32 [[LOAD1:v[0-9]+]]
; GCN: buffer_load_dword [[RELOAD_LOAD0:v[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
; GCN: s_waitcnt vmcnt(0) lgkmcnt(0)
@ -52,7 +53,9 @@
; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET]] ; 4-byte Folded Reload
; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:20 ; 4-byte Folded Reload
; VMEM: s_waitcnt vmcnt(0)
; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 0
; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 1
@ -85,26 +88,29 @@ endif:
; VGPR: workitem_private_segment_byte_size = 16{{$}}
; GCN: {{^}}; %bb.0:
; GCN-DAG: s_mov_b32 m0, -1
; GCN-DAG: v_mov_b32_e32 [[PTR0:v[0-9]+]], 0{{$}}
; GCN: ds_read_b32 [[LOAD0:v[0-9]+]], [[PTR0]]
; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, v0
; GCN: s_mov_b32 m0, -1
; GCN: ds_read_b32 [[LOAD0:v[0-9]+]]
; GCN: v_cmp_eq_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], s{{[0-9]+}}, v0
; GCN: s_mov_b64 s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, exec
; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, [[CMP0]]
; Spill load
; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: s_mov_b64 s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, exec
; Spill saved exec
; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
; VMEM: v_writelane_b32 v[[V_SAVEEXEC:[0-9]+]], s[[SAVEEXEC_LO]], 0
; VMEM: v_writelane_b32 v[[V_SAVEEXEC]], s[[SAVEEXEC_HI]], 1
; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; VMEM: buffer_store_dword v[[V_SAVEEXEC]], off, s[0:3], 0 offset:24 ; 4-byte Folded Spill
; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, [[CMP0]]
; GCN: s_mov_b64 exec, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}}
; GCN-NEXT: s_cbranch_execz [[END:BB[0-9]+_[0-9]+]]
@ -121,7 +127,7 @@ endif:
; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[V_EXEC_SPILL_OFFSET]] ; 4-byte Folded Reload
; VMEM: buffer_load_dword v[[V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:24 ; 4-byte Folded Reload
; VMEM: s_waitcnt vmcnt(0)
; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 0
; VMEM: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], v[[V_RELOAD_SAVEEXEC]], 1
@ -133,7 +139,7 @@ endif:
define amdgpu_kernel void @divergent_loop(i32 addrspace(1)* %out) #0 {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%load0 = load volatile i32, i32 addrspace(3)* null
%load0 = load volatile i32, i32 addrspace(3)* undef
%cmp0 = icmp eq i32 %tid, 0
br i1 %cmp0, label %loop, label %end
@ -155,12 +161,8 @@ end:
; GCN-LABEL: {{^}}divergent_if_else_endif:
; GCN: {{^}}; %bb.0:
; GCN-DAG: s_mov_b32 m0, -1
; GCN-DAG: v_mov_b32_e32 [[PTR0:v[0-9]+]], 0{{$}}
; GCN: ds_read_b32 [[LOAD0:v[0-9]+]], [[PTR0]]
; Spill load
; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; GCN: s_mov_b32 m0, -1
; GCN: ds_read_b32 [[LOAD0:v[0-9]+]]
; GCN: s_mov_b32 [[ZERO:s[0-9]+]], 0
; GCN: v_cmp_ne_u32_e64 [[CMP0:s\[[0-9]+:[0-9]\]]], [[ZERO]], v0
@ -169,6 +171,9 @@ end:
; GCN: s_and_b64 s{{\[}}[[ANDEXEC_LO:[0-9]+]]:[[ANDEXEC_HI:[0-9]+]]{{\]}}, s{{\[}}[[SAVEEXEC_LO:[0-9]+]]:[[SAVEEXEC_HI:[0-9]+]]{{\]}}, [[CMP0]]
; GCN: s_xor_b64 s{{\[}}[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]{{\]}}, s{{\[}}[[ANDEXEC_LO]]:[[ANDEXEC_HI]]{{\]}}, s{{\[}}[[SAVEEXEC_LO]]:[[SAVEEXEC_HI]]{{\]}}
; Spill load
; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], 0 offset:[[LOAD0_OFFSET:[0-9]+]] ; 4-byte Folded Spill
; Spill saved exec
; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
@ -187,6 +192,7 @@ end:
; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
; VMEM: buffer_load_dword v[[FLOW_V_RELOAD_SAVEEXEC:[0-9]+]], off, s[0:3], 0 offset:[[SAVEEXEC_OFFSET]]
; VMEM: s_waitcnt vmcnt(0)
; VMEM: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], v[[FLOW_V_RELOAD_SAVEEXEC]], 0
@ -213,8 +219,8 @@ end:
; GCN: ; %bb.{{[0-9]+}}: ; %if
; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
; GCN: ds_read_b32
; GCN: buffer_load_dword v[[LOAD0_RELOAD:[0-9]+]], off, s[0:3], 0 offset:[[LOAD0_OFFSET]] ; 4-byte Folded Reload
; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, v{{[0-9]+}}, v[[LOAD0_RELOAD]]
; GCN: buffer_store_dword [[ADD]], off, s[0:3], 0 offset:[[RESULT_OFFSET]] ; 4-byte Folded Spill
; GCN-NEXT: s_branch [[ENDIF:BB[0-9]+_[0-9]+]]
@ -242,7 +248,7 @@ end:
define amdgpu_kernel void @divergent_if_else_endif(i32 addrspace(1)* %out) #0 {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%load0 = load volatile i32, i32 addrspace(3)* null
%load0 = load volatile i32, i32 addrspace(3)* undef
%cmp0 = icmp eq i32 %tid, 0
br i1 %cmp0, label %if, label %else

62
llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir
View File

@ -1,62 +0,0 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=regallocfast -o - %s | FileCheck %s
# Make sure incorrect kills aren't emitted on vcc
---
name: foo
tracksRegLiveness: true
machineFunctionInfo:
isEntryFunction: true
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: foo
; CHECK: liveins: $vgpr0
; CHECK: V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec
; CHECK: $sgpr4_sgpr5 = COPY $vcc
; CHECK: renamable $vgpr0 = V_CNDMASK_B32_e64 0, -1, 0, 3, killed $vcc, implicit $exec
; CHECK: S_ENDPGM 0, implicit killed $vgpr0, implicit killed $sgpr4_sgpr5
%0:vgpr_32 = COPY $vgpr0
V_CMP_NE_U32_e32 0, %0, implicit-def $vcc, implicit $exec
$sgpr4_sgpr5 = COPY $vcc
%1:sreg_64_xexec = COPY $vcc
%2:vgpr_32 = V_CNDMASK_B32_e64 0, -1, 0, 3, %1, implicit $exec
$vgpr0 = COPY %2
S_ENDPGM 0, implicit $vgpr0, implicit $sgpr4_sgpr5
...
# This would hit "Unexpected reg unit state" assert.
---
name: bar
tracksRegLiveness: true
machineFunctionInfo:
isEntryFunction: true
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: bar
; CHECK: liveins: $vgpr0
; CHECK: V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec
; CHECK: renamable $sgpr4_sgpr5 = COPY $vcc
; CHECK: SI_SPILL_S64_SAVE $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5)
; CHECK: renamable $sgpr4_sgpr5 = COPY $vcc
; CHECK: $vcc = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32 :: (load 8 from %stack.0, align 4, addrspace 5)
; CHECK: renamable $vgpr0 = V_CNDMASK_B32_e64 0, -1, 0, 3, killed $sgpr4_sgpr5, implicit $exec
; CHECK: S_ENDPGM 0, implicit killed $vgpr0, implicit killed renamable $vcc
%0:vgpr_32 = COPY $vgpr0
V_CMP_NE_U32_e32 0, %0, implicit-def $vcc, implicit $exec
%3:sreg_64_xexec = COPY $vcc
%1:sreg_64_xexec = COPY $vcc
%2:vgpr_32 = V_CNDMASK_B32_e64 0, -1, 0, 3, %1, implicit $exec
$vgpr0 = COPY %2
S_ENDPGM 0, implicit $vgpr0, implicit %3
...

27
llvm/test/CodeGen/AMDGPU/fastregalloc-illegal-subreg-physreg.mir
View File

@ -1,27 +0,0 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=regallocfast -o - %s | FileCheck %s
# This would hit "Illegal subregister index for physical register" verifier error since
# tied operands would skip dropping the subregister index.
---
name: invalid_subreg_index
tracksRegLiveness: true
machineFunctionInfo:
isEntryFunction: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0
; CHECK-LABEL: name: invalid_subreg_index
; CHECK: liveins: $vgpr0, $sgpr0
; CHECK: $m0 = COPY renamable $sgpr0
; CHECK: undef renamable $vgpr1 = V_INTERP_P2_F32 undef $vgpr1, undef $vgpr0, 0, 1, implicit $mode, implicit $m0, implicit $exec, implicit-def dead $vgpr0_vgpr1
; CHECK: S_ENDPGM 0, implicit killed renamable $sgpr0
%0:vgpr_32 = COPY $vgpr0
%1:sgpr_32 = COPY $sgpr0
$m0 = COPY %1
undef %2.sub1:vreg_64 = V_INTERP_P2_F32 undef %2.sub1, undef %0:vgpr_32, 0, 1, implicit $mode, implicit $m0, implicit $exec
S_ENDPGM 0, implicit %1
...

25
llvm/test/CodeGen/AMDGPU/fastregalloc-self-loop-heuristic.mir
View File

@ -18,7 +18,7 @@ body: |
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
; GCN: renamable $vgpr2 = GLOBAL_LOAD_DWORD renamable $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec
; GCN: GLOBAL_STORE_DWORD renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec
; GCN: GLOBAL_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec
; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
; GCN: bb.2:
; GCN: S_ENDPGM 0
@ -53,10 +53,9 @@ body: |
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
; GCN: renamable $vgpr2 = GLOBAL_LOAD_DWORD renamable $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec
; GCN: GLOBAL_STORE_DWORD renamable $vgpr0_vgpr1, renamable $vgpr2, 0, 0, 0, 0, implicit $exec
; GCN: GLOBAL_STORE_DWORD renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec
; GCN: renamable $vgpr2 = GLOBAL_LOAD_DWORD renamable $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec
; GCN: SI_SPILL_V32_SAVE $vgpr2, %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 4 into %stack.1, addrspace 5)
; GCN: GLOBAL_STORE_DWORD renamable $vgpr0_vgpr1, renamable $vgpr2, 0, 0, 0, 0, implicit $exec
; GCN: GLOBAL_STORE_DWORD killed renamable $vgpr0_vgpr1, killed renamable $vgpr2, 0, 0, 0, 0, implicit $exec
; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
; GCN: bb.2:
; GCN: S_ENDPGM 0
@ -93,10 +92,9 @@ body: |
; GCN: SI_SPILL_V64_SAVE killed $vgpr0_vgpr1, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 8 into %stack.0, align 4, addrspace 5)
; GCN: bb.1:
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
; GCN: renamable $vgpr2 = V_ADD_U32_e32 1, undef $vgpr0, implicit $exec
; GCN: SI_SPILL_V32_SAVE $vgpr2, %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 4 into %stack.1, addrspace 5)
; GCN: GLOBAL_STORE_DWORD renamable $vgpr0_vgpr1, renamable $vgpr2, 0, 0, 0, 0, implicit $exec
; GCN: renamable $vgpr0 = V_ADD_U32_e32 1, undef $vgpr0, implicit $exec
; GCN: $vgpr1_vgpr2 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
; GCN: GLOBAL_STORE_DWORD killed renamable $vgpr1_vgpr2, killed renamable $vgpr0, 0, 0, 0, 0, implicit $exec
; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
; GCN: bb.2:
; GCN: S_ENDPGM 0
@ -130,9 +128,9 @@ body: |
; GCN: bb.1:
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
; GCN: GLOBAL_STORE_DWORD renamable $vgpr0_vgpr1, undef renamable $vgpr0, 0, 0, 0, 0, implicit $exec
; GCN: renamable $vgpr0 = V_ADD_U32_e64 1, 1, 0, implicit $exec
; GCN: SI_SPILL_V32_SAVE killed $vgpr0, %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 4 into %stack.1, addrspace 5)
; GCN: GLOBAL_STORE_DWORD killed renamable $vgpr0_vgpr1, undef renamable $vgpr0, 0, 0, 0, 0, implicit $exec
; GCN: renamable $vgpr2 = V_ADD_U32_e64 1, 1, 0, implicit $exec
; GCN: SI_SPILL_V32_SAVE killed $vgpr2, %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 4 into %stack.1, addrspace 5)
; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
; GCN: bb.2:
; GCN: S_ENDPGM 0
@ -166,8 +164,9 @@ body: |
; GCN: bb.1:
; GCN: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; GCN: $vgpr0_vgpr1 = SI_SPILL_V64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
; GCN: undef renamable $vgpr3 = GLOBAL_LOAD_DWORD renamable $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit-def dead $vgpr2_vgpr3
; GCN: GLOBAL_STORE_DWORD renamable $vgpr0_vgpr1, undef renamable $vgpr1, 0, 0, 0, 0, implicit $exec
; GCN: undef renamable $vgpr3 = GLOBAL_LOAD_DWORD renamable $vgpr0_vgpr1, 0, 0, 0, 0, implicit $exec, implicit-def $vgpr2_vgpr3
; GCN: GLOBAL_STORE_DWORD killed renamable $vgpr0_vgpr1, undef renamable $vgpr3, 0, 0, 0, 0, implicit $exec
; GCN: SI_SPILL_V64_SAVE killed $vgpr2_vgpr3, %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 8 into %stack.1, align 4, addrspace 5)
; GCN: S_CBRANCH_EXECZ %bb.1, implicit $exec
; GCN: bb.2:
; GCN: S_ENDPGM 0

153
llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
View File

@ -12,96 +12,101 @@ define amdgpu_kernel void @extract_w_offset_vgpr(i32 addrspace(1)* %out) {
; GCN: bb.0.entry:
; GCN: successors: %bb.1(0x80000000)
; GCN: liveins: $vgpr0, $sgpr0_sgpr1
; GCN: SI_SPILL_V32_SAVE killed $vgpr0, %stack.3, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (store 4 into %stack.3, addrspace 5)
; GCN: renamable $sgpr0_sgpr1 = S_LOAD_DWORDX2_IMM killed renamable $sgpr0_sgpr1, 36, 0, 0 :: (dereferenceable invariant load 8 from %ir.out.kernarg.offset.cast, align 4, addrspace 4)
; GCN: renamable $sgpr6 = COPY renamable $sgpr1
; GCN: renamable $sgpr2 = COPY renamable $sgpr1
; GCN: renamable $sgpr0 = COPY renamable $sgpr0, implicit killed $sgpr0_sgpr1
; GCN: renamable $sgpr4 = S_MOV_B32 61440
; GCN: renamable $sgpr5 = S_MOV_B32 -1
; GCN: undef renamable $sgpr0 = COPY killed renamable $sgpr0, implicit-def $sgpr0_sgpr1_sgpr2_sgpr3
; GCN: renamable $sgpr1 = COPY killed renamable $sgpr6
; GCN: renamable $sgpr2 = COPY killed renamable $sgpr5
; GCN: renamable $sgpr3 = COPY killed renamable $sgpr4
; GCN: SI_SPILL_S128_SAVE killed $sgpr0_sgpr1_sgpr2_sgpr3, %stack.2, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 16 into %stack.2, align 4, addrspace 5)
; GCN: renamable $sgpr1 = S_MOV_B32 61440
; GCN: renamable $sgpr3 = S_MOV_B32 -1
; GCN: undef renamable $sgpr4 = COPY killed renamable $sgpr0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7
; GCN: renamable $sgpr5 = COPY killed renamable $sgpr2
; GCN: renamable $sgpr6 = COPY killed renamable $sgpr3
; GCN: renamable $sgpr7 = COPY killed renamable $sgpr1
; GCN: renamable $sgpr0 = S_MOV_B32 16
; GCN: renamable $sgpr1 = S_MOV_B32 15
; GCN: renamable $sgpr2 = S_MOV_B32 14
; GCN: renamable $sgpr3 = S_MOV_B32 13
; GCN: renamable $sgpr4 = S_MOV_B32 12
; GCN: renamable $sgpr5 = S_MOV_B32 11
; GCN: renamable $sgpr6 = S_MOV_B32 10
; GCN: renamable $sgpr7 = S_MOV_B32 9
; GCN: renamable $sgpr8 = S_MOV_B32 8
; GCN: renamable $sgpr9 = S_MOV_B32 7
; GCN: renamable $sgpr10 = S_MOV_B32 6
; GCN: renamable $sgpr11 = S_MOV_B32 5
; GCN: renamable $sgpr12 = S_MOV_B32 3
; GCN: renamable $sgpr13 = S_MOV_B32 2
; GCN: renamable $sgpr14 = S_MOV_B32 1
; GCN: renamable $sgpr15 = S_MOV_B32 0
; GCN: renamable $vgpr0 = COPY killed renamable $sgpr15
; GCN: renamable $vgpr30 = COPY killed renamable $sgpr14
; GCN: renamable $vgpr29 = COPY killed renamable $sgpr13
; GCN: renamable $vgpr28 = COPY killed renamable $sgpr12
; GCN: renamable $vgpr27 = COPY killed renamable $sgpr11
; GCN: renamable $vgpr26 = COPY killed renamable $sgpr10
; GCN: renamable $vgpr25 = COPY killed renamable $sgpr9
; GCN: renamable $vgpr24 = COPY killed renamable $sgpr8
; GCN: renamable $vgpr23 = COPY killed renamable $sgpr7
; GCN: renamable $vgpr22 = COPY killed renamable $sgpr6
; GCN: renamable $vgpr21 = COPY killed renamable $sgpr5
; GCN: renamable $vgpr20 = COPY killed renamable $sgpr4
; GCN: renamable $vgpr19 = COPY killed renamable $sgpr3
; GCN: renamable $vgpr18 = COPY killed renamable $sgpr2
; GCN: renamable $vgpr17 = COPY killed renamable $sgpr1
; GCN: renamable $sgpr8 = S_MOV_B32 12
; GCN: renamable $sgpr9 = S_MOV_B32 11
; GCN: renamable $sgpr10 = S_MOV_B32 10
; GCN: renamable $sgpr11 = S_MOV_B32 9
; GCN: renamable $sgpr12 = S_MOV_B32 8
; GCN: renamable $sgpr13 = S_MOV_B32 7
; GCN: renamable $sgpr14 = S_MOV_B32 6
; GCN: renamable $sgpr15 = S_MOV_B32 5
; GCN: renamable $sgpr16 = S_MOV_B32 3
; GCN: renamable $sgpr17 = S_MOV_B32 2
; GCN: renamable $sgpr18 = S_MOV_B32 1
; GCN: renamable $sgpr19 = S_MOV_B32 0
; GCN: renamable $vgpr1 = COPY killed renamable $sgpr19
; GCN: renamable $vgpr2 = COPY killed renamable $sgpr18
; GCN: renamable $vgpr3 = COPY killed renamable $sgpr17
; GCN: renamable $vgpr4 = COPY killed renamable $sgpr16
; GCN: renamable $vgpr5 = COPY killed renamable $sgpr15
; GCN: renamable $vgpr6 = COPY killed renamable $sgpr14
; GCN: renamable $vgpr7 = COPY killed renamable $sgpr13
; GCN: renamable $vgpr8 = COPY killed renamable $sgpr12
; GCN: renamable $vgpr9 = COPY killed renamable $sgpr11
; GCN: renamable $vgpr10 = COPY killed renamable $sgpr10
; GCN: renamable $vgpr11 = COPY killed renamable $sgpr9
; GCN: renamable $vgpr12 = COPY killed renamable $sgpr8
; GCN: renamable $vgpr13 = COPY killed renamable $sgpr3
; GCN: renamable $vgpr14 = COPY killed renamable $sgpr2
; GCN: renamable $vgpr15 = COPY killed renamable $sgpr1
; GCN: renamable $vgpr16 = COPY killed renamable $sgpr0
; GCN: undef renamable $vgpr0 = COPY killed renamable $vgpr0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
; GCN: renamable $vgpr1 = COPY killed renamable $vgpr30
; GCN: renamable $vgpr2 = COPY killed renamable $vgpr29
; GCN: renamable $vgpr3 = COPY killed renamable $vgpr28
; GCN: renamable $vgpr4 = COPY killed renamable $vgpr27
; GCN: renamable $vgpr5 = COPY killed renamable $vgpr26
; GCN: renamable $vgpr6 = COPY killed renamable $vgpr25
; GCN: renamable $vgpr7 = COPY killed renamable $vgpr24
; GCN: renamable $vgpr8 = COPY killed renamable $vgpr23
; GCN: renamable $vgpr9 = COPY killed renamable $vgpr22
; GCN: renamable $vgpr10 = COPY killed renamable $vgpr21
; GCN: renamable $vgpr11 = COPY killed renamable $vgpr20
; GCN: renamable $vgpr12 = COPY killed renamable $vgpr19
; GCN: renamable $vgpr13 = COPY killed renamable $vgpr18
; GCN: renamable $vgpr14 = COPY killed renamable $vgpr17
; GCN: renamable $vgpr15 = COPY killed renamable $vgpr16
; GCN: SI_SPILL_V512_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, %stack.1, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (store 64 into %stack.1, align 4, addrspace 5)
; GCN: undef renamable $vgpr17 = COPY killed renamable $vgpr1, implicit-def $vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32
; GCN: renamable $vgpr18 = COPY killed renamable $vgpr2
; GCN: renamable $vgpr19 = COPY killed renamable $vgpr3
; GCN: renamable $vgpr20 = COPY killed renamable $vgpr4
; GCN: renamable $vgpr21 = COPY killed renamable $vgpr5
; GCN: renamable $vgpr22 = COPY killed renamable $vgpr6
; GCN: renamable $vgpr23 = COPY killed renamable $vgpr7
; GCN: renamable $vgpr24 = COPY killed renamable $vgpr8
; GCN: renamable $vgpr25 = COPY killed renamable $vgpr9
; GCN: renamable $vgpr26 = COPY killed renamable $vgpr10
; GCN: renamable $vgpr27 = COPY killed renamable $vgpr11
; GCN: renamable $vgpr28 = COPY killed renamable $vgpr12
; GCN: renamable $vgpr29 = COPY killed renamable $vgpr13
; GCN: renamable $vgpr30 = COPY killed renamable $vgpr14
; GCN: renamable $vgpr31 = COPY killed renamable $vgpr15
; GCN: renamable $vgpr32 = COPY killed renamable $vgpr16
; GCN: renamable $sgpr0_sgpr1 = S_MOV_B64 $exec
; GCN: SI_SPILL_S64_SAVE killed $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5)
; GCN: renamable $vgpr0 = IMPLICIT_DEF
; GCN: renamable $sgpr0_sgpr1 = IMPLICIT_DEF
; GCN: renamable $vgpr1 = IMPLICIT_DEF
; GCN: renamable $sgpr2_sgpr3 = IMPLICIT_DEF
; GCN: SI_SPILL_V32_SAVE killed $vgpr0, %stack.0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5)
; GCN: SI_SPILL_S128_SAVE killed $sgpr4_sgpr5_sgpr6_sgpr7, %stack.1, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 16 into %stack.1, align 4, addrspace 5)
; GCN: SI_SPILL_V512_SAVE killed $vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31_vgpr32, %stack.2, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (store 64 into %stack.2, align 4, addrspace 5)
; GCN: SI_SPILL_S64_SAVE killed $sgpr0_sgpr1, %stack.3, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.3, align 4, addrspace 5)
; GCN: SI_SPILL_V32_SAVE killed $vgpr1, %stack.4, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (store 4 into %stack.4, addrspace 5)
; GCN: SI_SPILL_S64_SAVE killed $sgpr2_sgpr3, %stack.5, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.5, align 4, addrspace 5)
; GCN: bb.1:
; GCN: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; GCN: $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.4, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (load 8 from %stack.4, align 4, addrspace 5)
; GCN: $vgpr17 = SI_SPILL_V32_RESTORE %stack.5, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (load 4 from %stack.5, addrspace 5)
; GCN: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15 = SI_SPILL_V512_RESTORE %stack.1, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (load 64 from %stack.1, align 4, addrspace 5)
; GCN: $vgpr16 = SI_SPILL_V32_RESTORE %stack.3, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (load 4 from %stack.3, addrspace 5)
; GCN: renamable $sgpr2 = V_READFIRSTLANE_B32 $vgpr16, implicit $exec
; GCN: renamable $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 $sgpr2, $vgpr16, implicit $exec
; GCN: renamable $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 killed renamable $sgpr0_sgpr1, implicit-def $exec, implicit-def dead $scc, implicit $exec
; GCN: $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.5, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (load 8 from %stack.5, align 4, addrspace 5)
; GCN: $vgpr0 = SI_SPILL_V32_RESTORE %stack.4, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (load 4 from %stack.4, addrspace 5)
; GCN: $vgpr1 = SI_SPILL_V32_RESTORE %stack.0, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
; GCN: renamable $sgpr2 = V_READFIRSTLANE_B32 $vgpr1, implicit $exec
; GCN: renamable $sgpr4_sgpr5 = V_CMP_EQ_U32_e64 $sgpr2, killed $vgpr1, implicit $exec
; GCN: renamable $sgpr4_sgpr5 = S_AND_SAVEEXEC_B64 killed renamable $sgpr4_sgpr5, implicit-def $exec, implicit-def $scc, implicit $exec
; GCN: S_SET_GPR_IDX_ON killed renamable $sgpr2, 1, implicit-def $m0, implicit-def undef $mode, implicit $m0, implicit $mode
; GCN: renamable $vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, implicit $m0
; GCN: SI_SPILL_V32_SAVE $vgpr0, %stack.6, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (store 4 into %stack.6, addrspace 5)
; GCN: $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17 = SI_SPILL_V512_RESTORE %stack.2, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (load 64 from %stack.2, align 4, addrspace 5)
; GCN: renamable $vgpr18 = V_MOV_B32_e32 $vgpr3, implicit $exec, implicit killed $vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17, implicit $m0
; GCN: S_SET_GPR_IDX_OFF implicit-def $mode, implicit $mode
; GCN: SI_SPILL_V32_SAVE killed $vgpr0, %stack.5, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (store 4 into %stack.5, addrspace 5)
; GCN: renamable $sgpr2_sgpr3 = COPY renamable $sgpr0_sgpr1
; GCN: SI_SPILL_S64_SAVE killed $sgpr2_sgpr3, %stack.4, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.4, align 4, addrspace 5)
; GCN: $exec = S_XOR_B64_term $exec, killed renamable $sgpr0_sgpr1, implicit-def dead $scc
; GCN: renamable $vgpr19 = COPY renamable $vgpr18
; GCN: renamable $sgpr2_sgpr3 = COPY renamable $sgpr4_sgpr5
; GCN: SI_SPILL_S64_SAVE killed $sgpr2_sgpr3, %stack.5, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.5, align 4, addrspace 5)
; GCN: SI_SPILL_S64_SAVE killed $sgpr0_sgpr1, %stack.6, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (store 8 into %stack.6, align 4, addrspace 5)
; GCN: SI_SPILL_V32_SAVE killed $vgpr19, %stack.4, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (store 4 into %stack.4, addrspace 5)
; GCN: SI_SPILL_V32_SAVE killed $vgpr0, %stack.7, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (store 4 into %stack.7, addrspace 5)
; GCN: SI_SPILL_V32_SAVE killed $vgpr18, %stack.8, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (store 4 into %stack.8, addrspace 5)
; GCN: $exec = S_XOR_B64_term $exec, killed renamable $sgpr4_sgpr5, implicit-def $scc
; GCN: S_CBRANCH_EXECNZ %bb.1, implicit $exec
; GCN: bb.3:
; GCN: successors: %bb.2(0x80000000)
; GCN: $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (load 8 from %stack.0, align 4, addrspace 5)
; GCN: $exec = S_MOV_B64 renamable $sgpr0_sgpr1
; GCN: $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.3, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (load 8 from %stack.3, align 4, addrspace 5)
; GCN: $exec = S_MOV_B64 killed renamable $sgpr0_sgpr1
; GCN: bb.2:
; GCN: $vgpr0 = SI_SPILL_V32_RESTORE %stack.6, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (load 4 from %stack.6, addrspace 5)
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = SI_SPILL_S128_RESTORE %stack.2, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (load 16 from %stack.2, align 4, addrspace 5)
; GCN: BUFFER_STORE_DWORD_OFFSET killed renamable $vgpr0, killed renamable $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out.load, addrspace 1)
; GCN: $vgpr0 = SI_SPILL_V32_RESTORE %stack.8, $sgpr96_sgpr97_sgpr98_sgpr99, $sgpr32, 0, implicit $exec :: (load 4 from %stack.8, addrspace 5)
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = SI_SPILL_S128_RESTORE %stack.1, implicit $exec, implicit $sgpr96_sgpr97_sgpr98_sgpr99, implicit $sgpr32 :: (load 16 from %stack.1, align 4, addrspace 5)
; GCN: BUFFER_STORE_DWORD_OFFSET renamable $vgpr0, renamable $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (store 4 into %ir.out.load, addrspace 1)
; GCN: S_ENDPGM 0
entry:
%id = call i32 @llvm.amdgcn.workitem.id.x() #1

89
llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands.ll
View File

@ -236,57 +236,17 @@ entry:
; W64-O0-DAG: s_mov_b32 [[IDX_S:s[0-9]+]], s{{[0-9]+}}
; W64-O0-DAG: v_mov_b32_e32 [[IDX_V:v[0-9]+]], s{{[0-9]+}}
; W64-O0-DAG: s_mov_b64 [[SAVEEXEC:s\[[0-9]+:[0-9]+\]]], exec
; W64-O0-DAG: buffer_store_dword [[IDX_V]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} ; 4-byte Folded Spill
; W64-O0-DAG: buffer_store_dword [[IDX_V]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[IDX_OFF:[0-9]+]] ; 4-byte Folded Spill
; W64-O0: [[LOOPBB0:BB[0-9]+_[0-9]+]]: ; =>This Inner Loop Header: Depth=1
; W64-O0: buffer_load_dword [[IDX:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s32 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC0:[0-9]+]], off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC1:[0-9]+]], off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC2:[0-9]+]], off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC3:[0-9]+]], off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; W64-O0: s_waitcnt vmcnt(0)
; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP1:[0-9]+]], v[[VRSRC1]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC0:[0-9]+]], s[[S0]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC1:[0-9]+]], s[[SRSRCTMP1]]
; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}}
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP2:[0-9]+]], v[[VRSRC2]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP3:[0-9]+]], v[[VRSRC3]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC2:[0-9]+]], s[[SRSRCTMP2]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC3:[0-9]+]], s[[SRSRCTMP3]]
; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}}
; W64-O0-DAG: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
; W64-O0-DAG: s_mov_b32 s[[S1:[0-9]+]], s[[SRSRCTMP1]]
; W64-O0-DAG: s_mov_b32 s[[S2:[0-9]+]], s[[SRSRCTMP2]]
; W64-O0-DAG: s_mov_b32 s[[S3:[0-9]+]], s[[SRSRCTMP3]]
; W64-O0: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64-O0: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s{{\[}}[[S0]]:[[S3]]{{\]}}, {{.*}} idxen
; W64-O0: s_waitcnt vmcnt(0)
; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP:[0-9]+]] ; 4-byte Folded Spill
; W64-O0: s_xor_b64 exec, exec, [[SAVE]]
; W64-O0-NEXT: s_cbranch_execnz [[LOOPBB0]]
; XXX-W64-O0: s_mov_b64 exec, [[SAVEEXEC]]
; W64-O0: buffer_load_dword [[RES:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP]] ; 4-byte Folded Reload
; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF:[0-9]+]] ; 4-byte Folded Spill
; W64-O0: s_cbranch_execz [[TERMBB:BB[0-9]+_[0-9]+]]
; W64-O0: ; %bb.{{[0-9]+}}: ; %bb1
; W64-O0-DAG: buffer_store_dword {{v[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:[[IDX_OFF:[0-9]+]] ; 4-byte Folded Spill
; W64-O0-DAG: s_mov_b64 s{{\[}}[[SAVEEXEC0:[0-9]+]]:[[SAVEEXEC1:[0-9]+]]{{\]}}, exec
; W64-O0: v_writelane_b32 [[VSAVEEXEC:v[0-9]+]], s[[SAVEEXEC0]], [[SAVEEXEC_IDX0:[0-9]+]]
; W64-O0: v_writelane_b32 [[VSAVEEXEC]], s[[SAVEEXEC1]], [[SAVEEXEC_IDX1:[0-9]+]]
; W64-O0: [[LOOPBB1:BB[0-9]+_[0-9]+]]: ; =>This Inner Loop Header: Depth=1
; W64-O0: buffer_load_dword [[IDX:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s32 offset:[[IDX_OFF]] ; 4-byte Folded Reload
; W64-O0: [[LOOPBB0:BB[0-9]+_[0-9]+]]:
; W64-O0: buffer_load_dword v[[VRSRC0:[0-9]+]], off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC1:[0-9]+]], off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC2:[0-9]+]], off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC3:[0-9]+]], off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; W64-O0: s_waitcnt vmcnt(0)
; W64-O0-DAG: v_readfirstlane_b32 s[[S0:[0-9]+]], v[[VRSRC0]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP0:[0-9]+]], v[[VRSRC0]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP1:[0-9]+]], v[[VRSRC1]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC0:[0-9]+]], s[[S0]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC0:[0-9]+]], s[[SRSRCTMP0]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC1:[0-9]+]], s[[SRSRCTMP1]]
; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}}
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP2:[0-9]+]], v[[VRSRC2]]
@ -295,10 +255,51 @@ entry:
; W64-O0-DAG: s_mov_b32 s[[SRSRC3:[0-9]+]], s[[SRSRCTMP3]]
; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}}
; W64-O0-DAG: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
; W64-O0-DAG: s_mov_b32 s[[S0:[0-9]+]], s[[SRSRCTMP0]]
; W64-O0-DAG: s_mov_b32 s[[S1:[0-9]+]], s[[SRSRCTMP1]]
; W64-O0-DAG: s_mov_b32 s[[S2:[0-9]+]], s[[SRSRCTMP2]]
; W64-O0-DAG: s_mov_b32 s[[S3:[0-9]+]], s[[SRSRCTMP3]]
; W64-O0: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64-O0: buffer_load_dword [[IDX:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[IDX_OFF]] ; 4-byte Folded Reload
; W64-O0: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s{{\[}}[[S0]]:[[S3]]{{\]}}, {{.*}} idxen
; W64-O0: s_waitcnt vmcnt(0)
; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP:[0-9]+]] ; 4-byte Folded Spill
; W64-O0: s_xor_b64 exec, exec, [[SAVE]]
; W64-O0-NEXT: s_cbranch_execnz [[LOOPBB0]]
; CHECK-O0: s_mov_b64 exec, [[SAVEEXEC]]
; W64-O0: buffer_load_dword [[RES:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP]] ; 4-byte Folded Reload
; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF:[0-9]+]] ; 4-byte Folded Spill
; W64-O0: s_cbranch_execz [[TERMBB:BB[0-9]+_[0-9]+]]
; W64-O0: ; %bb.{{[0-9]+}}:
; W64-O0-DAG: s_mov_b64 s{{\[}}[[SAVEEXEC0:[0-9]+]]:[[SAVEEXEC1:[0-9]+]]{{\]}}, exec
; W64-O0-DAG: buffer_store_dword {{v[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[IDX_OFF:[0-9]+]] ; 4-byte Folded Spill
; W64-O0: v_writelane_b32 [[VSAVEEXEC:v[0-9]+]], s[[SAVEEXEC0]], [[SAVEEXEC_IDX0:[0-9]+]]
; W64-O0: v_writelane_b32 [[VSAVEEXEC:v[0-9]+]], s[[SAVEEXEC1]], [[SAVEEXEC_IDX1:[0-9]+]]
; W64-O0: [[LOOPBB1:BB[0-9]+_[0-9]+]]:
; W64-O0: buffer_load_dword v[[VRSRC0:[0-9]+]], off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC1:[0-9]+]], off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC2:[0-9]+]], off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; W64-O0: buffer_load_dword v[[VRSRC3:[0-9]+]], off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; W64-O0: s_waitcnt vmcnt(0)
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP0:[0-9]+]], v[[VRSRC0]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP1:[0-9]+]], v[[VRSRC1]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC0:[0-9]+]], s[[SRSRCTMP0]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC1:[0-9]+]], s[[SRSRCTMP1]]
; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP0:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC0]]:[[SRSRC1]]{{\]}}, v{{\[}}[[VRSRC0]]:[[VRSRC1]]{{\]}}
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP2:[0-9]+]], v[[VRSRC2]]
; W64-O0-DAG: v_readfirstlane_b32 s[[SRSRCTMP3:[0-9]+]], v[[VRSRC3]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC2:[0-9]+]], s[[SRSRCTMP2]]
; W64-O0-DAG: s_mov_b32 s[[SRSRC3:[0-9]+]], s[[SRSRCTMP3]]
; W64-O0-DAG: v_cmp_eq_u64_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{\[}}[[SRSRC2]]:[[SRSRC3]]{{\]}}, v{{\[}}[[VRSRC2]]:[[VRSRC3]]{{\]}}
; W64-O0-DAG: s_and_b64 [[AND:s\[[0-9]+:[0-9]+\]]], [[CMP0]], [[CMP1]]
; W64-O0-DAG: s_mov_b32 s[[S0:[0-9]+]], s[[SRSRCTMP0]]
; W64-O0-DAG: s_mov_b32 s[[S1:[0-9]+]], s[[SRSRCTMP1]]
; W64-O0-DAG: s_mov_b32 s[[S2:[0-9]+]], s[[SRSRCTMP2]]
; W64-O0-DAG: s_mov_b32 s[[S3:[0-9]+]], s[[SRSRCTMP3]]
; W64-O0: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], [[AND]]
; W64-O0: buffer_load_dword [[IDX:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[IDX_OFF]] ; 4-byte Folded Reload
; W64-O0: buffer_load_format_x [[RES:v[0-9]+]], [[IDX]], s{{\[}}[[S0]]:[[S3]]{{\]}}, {{.*}} idxen
; W64-O0: s_waitcnt vmcnt(0)
; W64-O0: buffer_store_dword [[RES]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:[[RES_OFF_TMP:[0-9]+]] ; 4-byte Folded Spill

1290
llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
View File

File diff suppressed because it is too large Load Diff

8
llvm/test/CodeGen/AMDGPU/reserve-vgpr-for-sgpr-spill.ll
View File

@ -11,8 +11,8 @@ define void @child_function() #0 {
; GCN: v_writelane_b32 v255, s30, 0
; GCN: v_writelane_b32 v255, s31, 1
; GCN: s_swappc_b64 s[30:31], s[4:5]
; GCN: v_readlane_b32 s30, v255, 0
; GCN: v_readlane_b32 s31, v255, 1
; GCN: v_readlane_b32 s4, v255, 0
; GCN: v_readlane_b32 s5, v255, 1
; GCN: v_readlane_b32 s33, v255, 2
; GCN: ; NumVgprs: 256
@ -57,8 +57,8 @@ define void @reserve_vgpr_with_no_lower_vgpr_available() #0 {
; GCN: v_writelane_b32 v254, s30, 0
; GCN: v_writelane_b32 v254, s31, 1
; GCN: s_swappc_b64 s[30:31], s[4:5]
; GCN: v_readlane_b32 s30, v254, 0
; GCN: v_readlane_b32 s31, v254, 1
; GCN: v_readlane_b32 s4, v254, 0
; GCN: v_readlane_b32 s5, v254, 1
; GCN: v_readlane_b32 s33, v254, 2
define void @reserve_lowest_available_vgpr() #0 {

58
llvm/test/CodeGen/AMDGPU/spill-agpr.mir
View File

@ -13,25 +13,25 @@ body: |
; SPILLED: bb.0:
; SPILLED: successors: %bb.1(0x80000000)
; SPILLED: S_NOP 0, implicit-def renamable $agpr0
; SPILLED: SI_SPILL_A32_SAVE killed $agpr0, %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 4 into %stack.1, addrspace 5)
; SPILLED: S_NOP 0, implicit-def renamable $agpr0
; SPILLED: S_NOP 0, implicit-def renamable $agpr1
; SPILLED: SI_SPILL_A32_SAVE killed $agpr0, %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 4 into %stack.0, addrspace 5)
; SPILLED: SI_SPILL_A32_SAVE killed $agpr1, %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (store 4 into %stack.1, addrspace 5)
; SPILLED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
; SPILLED: bb.1:
; SPILLED: successors: %bb.2(0x80000000)
; SPILLED: S_NOP 1
; SPILLED: bb.2:
; SPILLED: $agpr0 = SI_SPILL_A32_RESTORE %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 4 from %stack.1, addrspace 5)
; SPILLED: $agpr1 = SI_SPILL_A32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
; SPILLED: S_NOP 0, implicit killed renamable $agpr0, implicit killed renamable $agpr1
; SPILLED: $agpr0 = SI_SPILL_A32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
; SPILLED: $agpr1 = SI_SPILL_A32_RESTORE %stack.1, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 4 from %stack.1, addrspace 5)
; SPILLED: S_NOP 0, implicit renamable $agpr0, implicit renamable $agpr1
; EXPANDED-LABEL: name: spill_restore_agpr32
; EXPANDED: bb.0:
; EXPANDED: successors: %bb.1(0x80000000)
; EXPANDED: liveins: $vgpr0, $vgpr1
; EXPANDED: S_NOP 0, implicit-def renamable $agpr0
; EXPANDED: S_NOP 0, implicit-def renamable $agpr1
; EXPANDED: $vgpr0 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
; EXPANDED: S_NOP 0, implicit-def renamable $agpr0
; EXPANDED: $vgpr1 = V_ACCVGPR_READ_B32 killed $agpr0, implicit $exec
; EXPANDED: $vgpr1 = V_ACCVGPR_READ_B32 killed $agpr1, implicit $exec
; EXPANDED: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
; EXPANDED: bb.1:
; EXPANDED: successors: %bb.2(0x80000000)
@ -41,7 +41,7 @@ body: |
; EXPANDED: liveins: $vgpr0, $vgpr1
; EXPANDED: $agpr0 = V_ACCVGPR_WRITE_B32 $vgpr0, implicit $exec
; EXPANDED: $agpr1 = V_ACCVGPR_WRITE_B32 $vgpr1, implicit $exec
; EXPANDED: S_NOP 0, implicit killed renamable $agpr0, implicit killed renamable $agpr1
; EXPANDED: S_NOP 0, implicit renamable $agpr0, implicit renamable $agpr1
bb.0:
S_NOP 0, implicit-def %0:agpr_32
S_NOP 0, implicit-def %1:agpr_32
@ -72,7 +72,7 @@ body: |
; SPILLED: S_NOP 1
; SPILLED: bb.2:
; SPILLED: $agpr0_agpr1 = SI_SPILL_A64_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 8 from %stack.0, align 4, addrspace 5)
; SPILLED: S_NOP 0, implicit killed renamable $agpr0_agpr1
; SPILLED: S_NOP 0, implicit renamable $agpr0_agpr1
; EXPANDED-LABEL: name: spill_restore_agpr64
; EXPANDED: bb.0:
; EXPANDED: successors: %bb.1(0x80000000)
@ -89,7 +89,7 @@ body: |
; EXPANDED: liveins: $vgpr0, $vgpr1
; EXPANDED: $agpr0 = V_ACCVGPR_WRITE_B32 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1
; EXPANDED: $agpr1 = V_ACCVGPR_WRITE_B32 $vgpr1, implicit $exec, implicit-def $agpr0_agpr1
; EXPANDED: S_NOP 0, implicit killed renamable $agpr0_agpr1
; EXPANDED: S_NOP 0, implicit renamable $agpr0_agpr1
bb.0:
S_NOP 0, implicit-def %0:areg_64
S_CBRANCH_SCC1 implicit undef $scc, %bb.1
@ -118,7 +118,6 @@ body: |
; SPILLED: bb.1:
; SPILLED: successors: %bb.2(0x80000000)
; SPILLED: bb.2:
; SPILLED: $agpr0 = SI_SPILL_A32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
; SPILLED: S_NOP 0, implicit undef $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; SPILLED: S_NOP 0, implicit undef $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47
; SPILLED: S_NOP 0, implicit undef $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63
@ -135,7 +134,8 @@ body: |
; SPILLED: S_NOP 0, implicit undef $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; SPILLED: S_NOP 0, implicit undef $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247
; SPILLED: S_NOP 0, implicit undef $vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255
; SPILLED: S_NOP 0, implicit killed renamable $agpr0
; SPILLED: $agpr0 = SI_SPILL_A32_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
; SPILLED: S_NOP 0, implicit renamable $agpr0
; EXPANDED-LABEL: name: spill_restore_agpr32_used_all_vgprs
; EXPANDED: bb.0:
; EXPANDED: successors: %bb.1(0x80000000)
@ -149,8 +149,6 @@ body: |
; EXPANDED: bb.1:
; EXPANDED: successors: %bb.2(0x80000000)
; EXPANDED: bb.2:
; EXPANDED: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
; EXPANDED: $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
; EXPANDED: S_NOP 0, implicit undef $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
; EXPANDED: S_NOP 0, implicit undef $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47
; EXPANDED: S_NOP 0, implicit undef $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63
@ -167,7 +165,9 @@ body: |
; EXPANDED: S_NOP 0, implicit undef $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239
; EXPANDED: S_NOP 0, implicit undef $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247
; EXPANDED: S_NOP 0, implicit undef $vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255
; EXPANDED: S_NOP 0, implicit killed renamable $agpr0
; EXPANDED: $vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, 0, 0, 0, 0, 0, implicit $exec :: (load 4 from %stack.0, addrspace 5)
; EXPANDED: $agpr0 = V_ACCVGPR_WRITE_B32 killed $vgpr0, implicit $exec
; EXPANDED: S_NOP 0, implicit renamable $agpr0
bb.0:
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15, $vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31, $vgpr32_vgpr33_vgpr34_vgpr35_vgpr36_vgpr37_vgpr38_vgpr39_vgpr40_vgpr41_vgpr42_vgpr43_vgpr44_vgpr45_vgpr46_vgpr47, $vgpr48_vgpr49_vgpr50_vgpr51_vgpr52_vgpr53_vgpr54_vgpr55_vgpr56_vgpr57_vgpr58_vgpr59_vgpr60_vgpr61_vgpr62_vgpr63, $vgpr64_vgpr65_vgpr66_vgpr67_vgpr68_vgpr69_vgpr70_vgpr71_vgpr72_vgpr73_vgpr74_vgpr75_vgpr76_vgpr77_vgpr78_vgpr79, $vgpr80_vgpr81_vgpr82_vgpr83_vgpr84_vgpr85_vgpr86_vgpr87_vgpr88_vgpr89_vgpr90_vgpr91_vgpr92_vgpr93_vgpr94_vgpr95, $vgpr96_vgpr97_vgpr98_vgpr99_vgpr100_vgpr101_vgpr102_vgpr103_vgpr104_vgpr105_vgpr106_vgpr107_vgpr108_vgpr109_vgpr110_vgpr111, $vgpr112_vgpr113_vgpr114_vgpr115_vgpr116_vgpr117_vgpr118_vgpr119_vgpr120_vgpr121_vgpr122_vgpr123_vgpr124_vgpr125_vgpr126_vgpr127, $vgpr128_vgpr129_vgpr130_vgpr131_vgpr132_vgpr133_vgpr134_vgpr135_vgpr136_vgpr137_vgpr138_vgpr139_vgpr140_vgpr141_vgpr142_vgpr143, $vgpr144_vgpr145_vgpr146_vgpr147_vgpr148_vgpr149_vgpr150_vgpr151_vgpr152_vgpr153_vgpr154_vgpr155_vgpr156_vgpr157_vgpr158_vgpr159, $vgpr160_vgpr161_vgpr162_vgpr163_vgpr164_vgpr165_vgpr166_vgpr167_vgpr168_vgpr169_vgpr170_vgpr171_vgpr172_vgpr173_vgpr174_vgpr175, $vgpr176_vgpr177_vgpr178_vgpr179_vgpr180_vgpr181_vgpr182_vgpr183_vgpr184_vgpr185_vgpr186_vgpr187_vgpr188_vgpr189_vgpr190_vgpr191, $vgpr192_vgpr193_vgpr194_vgpr195_vgpr196_vgpr197_vgpr198_vgpr199_vgpr200_vgpr201_vgpr202_vgpr203_vgpr204_vgpr205_vgpr206_vgpr207, $vgpr208_vgpr209_vgpr210_vgpr211_vgpr212_vgpr213_vgpr214_vgpr215_vgpr216_vgpr217_vgpr218_vgpr219_vgpr220_vgpr221_vgpr222_vgpr223, $vgpr224_vgpr225_vgpr226_vgpr227_vgpr228_vgpr229_vgpr230_vgpr231_vgpr232_vgpr233_vgpr234_vgpr235_vgpr236_vgpr237_vgpr238_vgpr239, $vgpr240_vgpr241_vgpr242_vgpr243_vgpr244_vgpr245_vgpr246_vgpr247, $vgpr248_vgpr249_vgpr250_vgpr251_vgpr252_vgpr253_vgpr254_vgpr255
@ -214,7 +214,7 @@ body: |
; SPILLED: S_NOP 1
; SPILLED: bb.2:
; SPILLED: $agpr0_agpr1_agpr2 = SI_SPILL_A96_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 12 from %stack.0, align 4, addrspace 5)
; SPILLED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2
; SPILLED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2
; EXPANDED-LABEL: name: spill_restore_agpr96
; EXPANDED: bb.0:
; EXPANDED: successors: %bb.1(0x80000000)
@ -233,7 +233,7 @@ body: |
; EXPANDED: $agpr0 = V_ACCVGPR_WRITE_B32 $vgpr0, implicit $exec, implicit-def $agpr0_agpr1_agpr2
; EXPANDED: $agpr1 = V_ACCVGPR_WRITE_B32 $vgpr1, implicit $exec, implicit-def $agpr0_agpr1_agpr2
; EXPANDED: $agpr2 = V_ACCVGPR_WRITE_B32 $vgpr2, implicit $exec, implicit-def $agpr0_agpr1_agpr2
; EXPANDED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2
; EXPANDED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2
bb.0:
S_NOP 0, implicit-def %0:areg_96
S_CBRANCH_SCC1 implicit undef $scc, %bb.1
@ -263,7 +263,7 @@ body: |
; SPILLED: S_NOP 1
; SPILLED: bb.2:
; SPILLED: $agpr0_agpr1_agpr2_agpr3 = SI_SPILL_A128_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 16 from %stack.0, align 4, addrspace 5)
; SPILLED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2_agpr3
; SPILLED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2_agpr3
; EXPANDED-LABEL: name: spill_restore_agpr128
; EXPANDED: bb.0:
; EXPANDED: successors: %bb.1(0x80000000)
@ -284,7 +284,7 @@ body: |
; EXPANDED: $agpr1 = V_ACCVGPR_WRITE_B32 $vgpr1, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3
; EXPANDED: $agpr2 = V_ACCVGPR_WRITE_B32 $vgpr2, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3
; EXPANDED: $agpr3 = V_ACCVGPR_WRITE_B32 $vgpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3
; EXPANDED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2_agpr3
; EXPANDED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2_agpr3
bb.0:
S_NOP 0, implicit-def %0:areg_128
S_CBRANCH_SCC1 implicit undef $scc, %bb.1
@ -314,7 +314,7 @@ body: |
; SPILLED: S_NOP 1
; SPILLED: bb.2:
; SPILLED: $agpr0_agpr1_agpr2_agpr3_agpr4 = SI_SPILL_A160_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 20 from %stack.0, align 4, addrspace 5)
; SPILLED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2_agpr3_agpr4
; SPILLED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2_agpr3_agpr4
; EXPANDED-LABEL: name: spill_restore_agpr160
; EXPANDED: bb.0:
; EXPANDED: successors: %bb.1(0x80000000)
@ -337,7 +337,7 @@ body: |
; EXPANDED: $agpr2 = V_ACCVGPR_WRITE_B32 $vgpr2, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4
; EXPANDED: $agpr3 = V_ACCVGPR_WRITE_B32 $vgpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4
; EXPANDED: $agpr4 = V_ACCVGPR_WRITE_B32 $vgpr4, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4
; EXPANDED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2_agpr3_agpr4
; EXPANDED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2_agpr3_agpr4
bb.0:
S_NOP 0, implicit-def %0:areg_160
S_CBRANCH_SCC1 implicit undef $scc, %bb.1
@ -367,7 +367,7 @@ body: |
; SPILLED: S_NOP 1
; SPILLED: bb.2:
; SPILLED: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5 = SI_SPILL_A192_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 24 from %stack.0, align 4, addrspace 5)
; SPILLED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5
; SPILLED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5
; EXPANDED-LABEL: name: spill_restore_agpr192
; EXPANDED: bb.0:
; EXPANDED: successors: %bb.1(0x80000000)
@ -392,7 +392,7 @@ body: |
; EXPANDED: $agpr3 = V_ACCVGPR_WRITE_B32 $vgpr3, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5
; EXPANDED: $agpr4 = V_ACCVGPR_WRITE_B32 $vgpr4, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5
; EXPANDED: $agpr5 = V_ACCVGPR_WRITE_B32 $vgpr5, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5
; EXPANDED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5
; EXPANDED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5
bb.0:
S_NOP 0, implicit-def %0:areg_192
S_CBRANCH_SCC1 implicit undef $scc, %bb.1
@ -422,7 +422,7 @@ body: |
; SPILLED: S_NOP 1
; SPILLED: bb.2:
; SPILLED: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7 = SI_SPILL_A256_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 32 from %stack.0, align 4, addrspace 5)
; SPILLED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; SPILLED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; EXPANDED-LABEL: name: spill_restore_agpr256
; EXPANDED: bb.0:
; EXPANDED: successors: %bb.1(0x80000000)
@ -451,7 +451,7 @@ body: |
; EXPANDED: $agpr5 = V_ACCVGPR_WRITE_B32 $vgpr5, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; EXPANDED: $agpr6 = V_ACCVGPR_WRITE_B32 $vgpr6, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; EXPANDED: $agpr7 = V_ACCVGPR_WRITE_B32 $vgpr7, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; EXPANDED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
; EXPANDED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7
bb.0:
S_NOP 0, implicit-def %0:areg_256
S_CBRANCH_SCC1 implicit undef $scc, %bb.1
@ -481,7 +481,7 @@ body: |
; SPILLED: S_NOP 1
; SPILLED: bb.2:
; SPILLED: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15 = SI_SPILL_A512_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 64 from %stack.0, align 4, addrspace 5)
; SPILLED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; SPILLED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; EXPANDED-LABEL: name: spill_restore_agpr512
; EXPANDED: bb.0:
; EXPANDED: successors: %bb.1(0x80000000)
@ -526,7 +526,7 @@ body: |
; EXPANDED: $agpr13 = V_ACCVGPR_WRITE_B32 $vgpr13, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; EXPANDED: $agpr14 = V_ACCVGPR_WRITE_B32 $vgpr14, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; EXPANDED: $agpr15 = V_ACCVGPR_WRITE_B32 $vgpr15, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; EXPANDED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
; EXPANDED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15
bb.0:
S_NOP 0, implicit-def %0:areg_512
S_CBRANCH_SCC1 implicit undef $scc, %bb.1
@ -556,7 +556,7 @@ body: |
; SPILLED: S_NOP 1
; SPILLED: bb.2:
; SPILLED: $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31 = SI_SPILL_A1024_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 128 from %stack.0, align 4, addrspace 5)
; SPILLED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31
; SPILLED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31
; EXPANDED-LABEL: name: spill_restore_agpr1024
; EXPANDED: bb.0:
; EXPANDED: successors: %bb.1(0x80000000)
@ -633,7 +633,7 @@ body: |
; EXPANDED: $agpr29 = V_ACCVGPR_WRITE_B32 $vgpr29, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31
; EXPANDED: $agpr30 = V_ACCVGPR_WRITE_B32 $vgpr30, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31
; EXPANDED: $agpr31 = V_ACCVGPR_WRITE_B32 $vgpr31, implicit $exec, implicit-def $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31
; EXPANDED: S_NOP 0, implicit killed renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31
; EXPANDED: S_NOP 0, implicit renamable $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31
bb.0:
S_NOP 0, implicit-def %0:areg_1024
S_CBRANCH_SCC1 implicit undef $scc, %bb.1

51
llvm/test/CodeGen/AMDGPU/spill-m0.ll
View File

@ -1,32 +1,28 @@
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=TOVGPR -check-prefix=GCN %s
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=TOVGPR -check-prefix=GCN %s
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=TOVMEM -check-prefix=GCN %s
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=TOVMEM -check-prefix=GCN %s
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=TOVGPR -check-prefix=GCN %s
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=TOVGPR -check-prefix=GCN %s
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=TOVMEM -check-prefix=GCN %s
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=TOVMEM -check-prefix=GCN %s
; XXX - Why does it like to use vcc?
; GCN-LABEL: {{^}}spill_m0:
; GCN: #ASMSTART
; GCN-NEXT: s_mov_b32 m0, 0
; GCN-NEXT: #ASMEND
; GCN-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0
; GCN-DAG: s_cmp_lg_u32
; TOVGPR: v_writelane_b32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]], [[M0_LANE:[0-9]+]]
; TOVGPR-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0
; TOVGPR: v_writelane_b32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]], 2
; TOVMEM: v_writelane_b32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]], 0
; TOVMEM: s_mov_b32 [[COPY_EXEC_LO:s[0-9]+]], exec_lo
; TOVMEM: s_mov_b32 exec_lo, 1
; TOVMEM: buffer_store_dword [[SPILL_VREG]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4 ; 4-byte Folded Spill
; TOVMEM: s_mov_b32 exec_lo, [[COPY_EXEC_LO]]
; TOVMEM-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0
; TOVMEM-DAG: v_writelane_b32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]], 0
; TOVMEM: buffer_store_dword [[SPILL_VREG]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:12 ; 4-byte Folded Spill
; GCN: s_cbranch_scc1 [[ENDIF:BB[0-9]+_[0-9]+]]
; GCN: [[ENDIF]]:
; TOVGPR: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[SPILL_VREG]], [[M0_LANE]]
; TOVGPR: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[SPILL_VREG]], 2
; TOVGPR: s_mov_b32 m0, [[M0_RESTORE]]
; TOVMEM: buffer_load_dword [[RELOAD_VREG:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:4 ; 4-byte Folded Reload
; TOVMEM: buffer_load_dword [[RELOAD_VREG:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:12 ; 4-byte Folded Reload
; TOVMEM: s_waitcnt vmcnt(0)
; TOVMEM: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[RELOAD_VREG]], 0
; TOVMEM: s_mov_b32 m0, [[M0_RESTORE]]
@ -52,6 +48,8 @@ endif:
; m0 is killed, so it isn't necessary during the entry block spill to preserve it
; GCN-LABEL: {{^}}spill_kill_m0_lds:
; GCN: s_mov_b32 m0, s6
; GCN: v_interp_mov_f32
; GCN-NOT: v_readlane_b32 m0
; GCN-NOT: s_buffer_store_dword m0
@ -81,11 +79,10 @@ endif: ; preds = %else, %if
; Force save and restore of m0 during SMEM spill
; GCN-LABEL: {{^}}m0_unavailable_spill:
; GCN: s_load_dword [[REG0:s[0-9]+]], s[0:1], {{0x[0-9]+}}
; GCN: ; def m0, 1
; GCN: s_mov_b32 m0, [[REG0]]
; GCN: s_mov_b32 m0, s0
; GCN: v_interp_mov_f32
; GCN: ; clobber m0
@ -127,17 +124,16 @@ endif:
}
; GCN-LABEL: {{^}}restore_m0_lds:
; TOSMEM: s_load_dwordx2 [[REG:s\[[0-9]+:[0-9]+\]]]
; TOSMEM: s_cmp_eq_u32
; FIXME: RegScavenger::isRegUsed() always returns true if m0 is reserved, so we have to save and restore it
; FIXME-TOSMEM-NOT: m0
; TOSMEM: s_add_u32 m0, s3, {{0x[0-9]+}}
; TOSMEM: s_buffer_store_dword s1, s[88:91], m0 ; 4-byte Folded Spill
; TOSMEM: s_add_u32 m0, s3, 0x100
; TOSMEM: s_buffer_store_dword s{{[0-9]+}}, s[88:91], m0 ; 4-byte Folded Spill
; FIXME-TOSMEM-NOT: m0
; TOSMEM: s_load_dwordx2 [[REG:s\[[0-9]+:[0-9]+\]]]
; TOSMEM: s_add_u32 m0, s3, {{0x[0-9]+}}
; TOSMEM: s_waitcnt lgkmcnt(0)
; TOSMEM: s_add_u32 m0, s3, 0x200
; TOSMEM: s_buffer_store_dwordx2 [[REG]], s[88:91], m0 ; 8-byte Folded Spill
; FIXME-TOSMEM-NOT: m0
; TOSMEM: s_cmp_eq_u32
; TOSMEM: s_cbranch_scc1
; TOSMEM: s_mov_b32 m0, -1
@ -154,13 +150,6 @@ endif:
; TOSMEM: s_add_u32 m0, s3, 0x100
; TOSMEM: s_buffer_load_dword s2, s[88:91], m0 ; 4-byte Folded Reload
; FIXME-TOSMEM-NOT: m0
; TOSMEM: s_mov_b32 [[REG1:s[0-9]+]], m0
; TOSMEM: s_add_u32 m0, s3, 0x100
; TOSMEM: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[88:91], m0 ; 8-byte Folded Reload
; TOSMEM: s_mov_b32 m0, [[REG1]]
; TOSMEM: s_mov_b32 m0, -1
; TOSMEM: s_waitcnt lgkmcnt(0)
; TOSMEM-NOT: m0
; TOSMEM: s_mov_b32 m0, s2

8
llvm/test/CodeGen/AMDGPU/spill192.mir
View File

@ -24,7 +24,7 @@ body: |
; SPILLED: S_NOP 1
; SPILLED: bb.2:
; SPILLED: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9 = SI_SPILL_S192_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32 :: (load 24 from %stack.0, align 4, addrspace 5)
; SPILLED: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
; SPILLED: S_NOP 0, implicit renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
; EXPANDED-LABEL: name: spill_restore_sgpr192
; EXPANDED: bb.0:
; EXPANDED: successors: %bb.1(0x80000000)
@ -49,7 +49,7 @@ body: |
; EXPANDED: $sgpr7 = V_READLANE_B32_gfx6_gfx7 $vgpr0, 3
; EXPANDED: $sgpr8 = V_READLANE_B32_gfx6_gfx7 $vgpr0, 4
; EXPANDED: $sgpr9 = V_READLANE_B32_gfx6_gfx7 $vgpr0, 5
; EXPANDED: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
; EXPANDED: S_NOP 0, implicit renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
bb.0:
S_NOP 0, implicit-def %0:sgpr_192
S_CBRANCH_SCC1 implicit undef $scc, %bb.1
@ -79,7 +79,7 @@ body: |
; SPILLED: S_NOP 1
; SPILLED: bb.2:
; SPILLED: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V192_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 24 from %stack.0, align 4, addrspace 5)
; SPILLED: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
; SPILLED: S_NOP 0, implicit renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
; EXPANDED-LABEL: name: spill_restore_vgpr192
; EXPANDED: bb.0:
; EXPANDED: successors: %bb.1(0x80000000)
@ -91,7 +91,7 @@ body: |
; EXPANDED: S_NOP 1
; EXPANDED: bb.2:
; EXPANDED: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 = SI_SPILL_V192_RESTORE %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 0, implicit $exec :: (load 24 from %stack.0, align 4, addrspace 5)
; EXPANDED: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
; EXPANDED: S_NOP 0, implicit renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
bb.0:
S_NOP 0, implicit-def %0:vreg_192
S_CBRANCH_SCC1 implicit undef $scc, %bb.1

32
llvm/test/CodeGen/AMDGPU/unexpected-reg-unit-state.mir
View File

@ -1,32 +0,0 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -verify-machineinstrs -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=regallocfast -o - %s | FileCheck %s
---
name: bar
tracksRegLiveness: true
machineFunctionInfo:
isEntryFunction: true
scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
stackPtrOffsetReg: '$sgpr32'
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: bar
; CHECK: liveins: $vgpr0
; CHECK: V_CMP_NE_U32_e32 0, killed $vgpr0, implicit-def $vcc, implicit $exec
; CHECK: renamable $sgpr4_sgpr5 = COPY $vcc
; CHECK: SI_SPILL_S64_SAVE $sgpr4_sgpr5, %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32 :: (store 8 into %stack.0, align 4, addrspace 5)
; CHECK: renamable $sgpr4_sgpr5 = COPY $vcc
; CHECK: $vcc = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr32 :: (load 8 from %stack.0, align 4, addrspace 5)
; CHECK: renamable $vgpr0 = V_CNDMASK_B32_e64 0, -1, 0, 3, killed $sgpr4_sgpr5, implicit $exec
; CHECK: S_ENDPGM 0, implicit killed $vgpr0, implicit killed renamable $vcc
%0:vgpr_32 = COPY $vgpr0
V_CMP_NE_U32_e32 0, %0, implicit-def $vcc, implicit $exec
%3:sreg_64_xexec = COPY $vcc
%1:sreg_64_xexec = COPY $vcc
%2:vgpr_32 = V_CNDMASK_B32_e64 0, -1, 0, 3, %1, implicit $exec
$vgpr0 = COPY %2
S_ENDPGM 0, implicit $vgpr0, implicit %3
...

41
llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
View File

@ -69,8 +69,8 @@ if:
merge:
%merge_value = phi i32 [ 0, %entry ], [%tmp137, %if ]
; GFX9-O3: v_cmp_eq_u32_e32 vcc, v[[FIRST]], v[[SECOND]]
; GFX9-O0: buffer_load_dword v[[FIRST:[0-9]+]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[FIRST_IMM_OFFSET]]
; GFX9-O0: buffer_load_dword v[[SECOND:[0-9]+]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[SECOND_IMM_OFFSET]]
; GFX9-O0: buffer_load_dword v[[FIRST:[0-9]+]], off, s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, 0 offset:[[FIRST_IMM_OFFSET]]
; GFX9-O0: v_cmp_eq_u32_e64 s{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v[[FIRST]], v[[SECOND]]
%tmp138 = icmp eq i32 %tmp122, %merge_value
%tmp139 = sext i1 %tmp138 to i32
@ -82,7 +82,7 @@ merge:
}
; GFX9-LABEL: {{^}}called:
define hidden i32 @called(i32 %a) noinline {
define i32 @called(i32 %a) noinline {
; GFX9: v_add_u32_e32 v1, v0, v0
%add = add i32 %a, %a
; GFX9: v_mul_lo_u32 v0, v1, v0
@ -94,15 +94,10 @@ define hidden i32 @called(i32 %a) noinline {
; GFX9-LABEL: {{^}}call:
define amdgpu_kernel void @call(<4 x i32> inreg %tmp14, i32 inreg %arg) {
; GFX9-DAG: s_load_dword [[ARG:s[0-9]+]]
; GFX9-O0-DAG: s_mov_b32 s0, 0{{$}}
; GFX9-O0-DAG: v_mov_b32_e32 v0, [[ARG]]
; GFX9-O3: v_mov_b32_e32 v2, [[ARG]]
; GFX9-O0: v_mov_b32_e32 v0, s0
; GFX9-O3: v_mov_b32_e32 v2, s0
; GFX9-NEXT: s_not_b64 exec, exec
; GFX9-O0-NEXT: v_mov_b32_e32 v0, s0
; GFX9-O0-NEXT: v_mov_b32_e32 v0, s1
; GFX9-O3-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_not_b64 exec, exec
%tmp107 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 %arg, i32 0)
@ -112,11 +107,12 @@ define amdgpu_kernel void @call(<4 x i32> inreg %tmp14, i32 inreg %arg) {
%tmp134 = call i32 @called(i32 %tmp107)
; GFX9-O0: buffer_load_dword v1
; GFX9-O3: v_mov_b32_e32 v1, v0
; GFX9-O0: v_add_u32_e32 v1, v0, v1
; GFX9-O0: v_add_u32_e32 v0, v0, v1
; GFX9-O3: v_add_u32_e32 v1, v1, v2
%tmp136 = add i32 %tmp134, %tmp107
%tmp137 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp136)
; GFX9: buffer_store_dword v0
; GFX9-O0: buffer_store_dword v2
; GFX9-O3: buffer_store_dword v0
call void @llvm.amdgcn.raw.buffer.store.i32(i32 %tmp137, <4 x i32> %tmp14, i32 4, i32 0, i32 0)
ret void
}
@ -131,24 +127,19 @@ define i64 @called_i64(i64 %a) noinline {
; GFX9-LABEL: {{^}}call_i64:
define amdgpu_kernel void @call_i64(<4 x i32> inreg %tmp14, i64 inreg %arg) {
; GFX9: s_load_dwordx2 s{{\[}}[[ARG_LO:[0-9]+]]:[[ARG_HI:[0-9]+]]{{\]}}
; GFX9-O0: s_mov_b64 s{{\[}}[[ZERO_LO:[0-9]+]]:[[ZERO_HI:[0-9]+]]{{\]}}, 0{{$}}
; GFX9-O0: v_mov_b32_e32 v1, s[[ARG_LO]]
; GFX9-O0: v_mov_b32_e32 v2, s[[ARG_HI]]
; GFX9-O3-DAG: v_mov_b32_e32 v7, s[[ARG_HI]]
; GFX9-O3-DAG: v_mov_b32_e32 v6, s[[ARG_LO]]
; GFX9: s_not_b64 exec, exec
; GFX9-O0-NEXT: v_mov_b32_e32 v1, s[[ZERO_LO]]
; GFX9-O0-NEXT: v_mov_b32_e32 v2, s[[ZERO_HI]]
; GFX9-O0: v_mov_b32_e32 v0, s0
; GFX9-O0: v_mov_b32_e32 v1, s1
; GFX9-O3: v_mov_b32_e32 v7, s1
; GFX9-O3: v_mov_b32_e32 v6, s0
; GFX9-NEXT: s_not_b64 exec, exec
; GFX9-O0-NEXT: v_mov_b32_e32 v0, s2
; GFX9-O0-NEXT: v_mov_b32_e32 v1, s3
; GFX9-O3-NEXT: v_mov_b32_e32 v6, 0
; GFX9-O3-NEXT: v_mov_b32_e32 v7, 0
; GFX9-NEXT: s_not_b64 exec, exec
%tmp107 = tail call i64 @llvm.amdgcn.set.inactive.i64(i64 %arg, i64 0)
; GFX9-O0: buffer_store_dword v0
; GFX9-O0: buffer_store_dword v1
; GFX9-O0: buffer_store_dword v2
; GFX9: s_swappc_b64
%tmp134 = call i64 @called_i64(i64 %tmp107)
; GFX9-O0: buffer_load_dword v4

3
llvm/test/CodeGen/ARM/2010-08-04-StackVariable.ll
View File

@ -8,9 +8,6 @@
define i32 @_Z3fooi4SVal(i32 %i, %struct.SVal* noalias %location) #0 !dbg !4 {
entry:
%"alloca point" = bitcast i32 0 to i32
br label %realentry
realentry:
call void @llvm.dbg.value(metadata i32 %i, metadata !21, metadata !DIExpression()), !dbg !22
call void @llvm.dbg.value(metadata %struct.SVal* %location, metadata !23, metadata !DIExpression()), !dbg !22
%tmp = icmp ne i32 %i, 0, !dbg !25

9
llvm/test/CodeGen/ARM/Windows/alloca.ll
View File

@ -17,11 +17,10 @@ entry:
; CHECK: bl num_entries
; Any register is actually valid here, but turns out we use lr,
; because we do not have the kill flag on R0.
; CHECK: mov [[R0:r[0-9]+]], r0
; CHECK: movs [[R1:r[0-9]+]], #7
; CHECK: add.w [[R2:r[0-9]+]], [[R1]], [[R0]], lsl #2
; CHECK: bic [[R2]], [[R2]], #4
; CHECK: lsrs r4, [[R2]], #2
; CHECK: movs [[R1:r1]], #7
; CHECK: add.w [[R0:r[0-9]+]], [[R1]], [[R0]], lsl #2
; CHECK: bic [[R0]], [[R0]], #4
; CHECK: lsrs r4, [[R0]], #2
; CHECK: bl __chkstk
; CHECK: sub.w sp, sp, r4

10
llvm/test/CodeGen/ARM/cmpxchg-O0-be.ll
View File

@ -7,10 +7,12 @@
; CHECK_LABEL: main:
; CHECK: ldr [[R2:r[0-9]+]], {{\[}}[[R1:r[0-9]+]]{{\]}}
; CHECK-NEXT: ldr [[R1]], {{\[}}[[R1]], #4]
; CHECK: mov [[R4:r[0-9]+]], [[R1]]
; CHECK: ldr [[R5:r[0-9]+]], {{\[}}[[R1]]{{\]}}
; CHECK-NEXT: ldr [[R6:r[0-9]+]], {{\[}}[[R1]], #4]
; CHECK: mov [[R7:r[0-9]+]], [[R6]]
; CHECK: mov [[R4:r[0-9]+]], [[R2]]
; CHECK-NEXT: mov [[R5:r[0-9]+]], [[R1]]
; CHECK: ldr [[R2]], {{\[}}[[R1]]{{\]}}
; CHECK-NEXT: ldr [[R1]], {{\[}}[[R1]], #4]
; CHECK: mov [[R6:r[0-9]+]], [[R2]]
; CHECK-NEXT: mov [[R7:r[0-9]+]], [[R1]]
define arm_aapcs_vfpcc i32 @main() #0 {
entry:

32
llvm/test/CodeGen/ARM/cmpxchg-O0.ll
View File

@ -7,21 +7,19 @@
define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_8:
; CHECK-DAG: mov [[ADDR:r[0-9]+]], r0
; CHECK-DAG: mov [[NEW:r[0-9]+]], r2
; CHECK: dmb ish
; CHECK: uxtb [[DESIRED:r[0-9]+]], [[DESIRED]]
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldrexb [[OLD:[lr0-9]+]], {{\[}}[[ADDR]]{{\]}}
; CHECK: ldrexb [[OLD:[lr0-9]+]], [r0]
; CHECK: cmp [[OLD]], [[DESIRED]]
; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: strexb [[STATUS:r[0-9]+]], [[NEW]], {{\[}}[[ADDR]]{{\]}}
; CHECK: strexb [[STATUS:r[0-9]+]], r2, [r0]
; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
; CHECK: bne [[RETRY]]
; CHECK: [[DONE]]:
; Materialisation of a boolean is done with sub/clz/lsr
; CHECK: uxtb [[CMP1:r[0-9]+]], [[DESIRED]]
; CHECK: sub{{(\.w|s)?}} [[CMP1]], [[OLD]], [[CMP1]]
; CHECK: sub{{(\.w)?}} [[CMP1]], [[OLD]], [[CMP1]]
; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
; CHECK: lsr{{(s)?}} {{r[0-9]+}}, [[CMP2]], #5
; CHECK: dmb ish
@ -31,21 +29,19 @@ define { i8, i1 } @test_cmpxchg_8(i8* %addr, i8 %desired, i8 %new) nounwind {
define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_16:
; CHECK-DAG: mov [[ADDR:r[0-9]+]], r0
; CHECK-DAG: mov [[NEW:r[0-9]+]], r2
; CHECK: dmb ish
; CHECK: uxth [[DESIRED:r[0-9]+]], [[DESIRED]]
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldrexh [[OLD:[lr0-9]+]], {{\[}}[[ADDR]]{{\]}}
; CHECK: ldrexh [[OLD:[lr0-9]+]], [r0]
; CHECK: cmp [[OLD]], [[DESIRED]]
; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: strexh [[STATUS:r[0-9]+]], [[NEW]], {{\[}}[[ADDR]]{{\]}}
; CHECK: strexh [[STATUS:r[0-9]+]], r2, [r0]
; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
; CHECK: bne [[RETRY]]
; CHECK: [[DONE]]:
; Materialisation of a boolean is done with sub/clz/lsr
; CHECK: uxth [[CMP1:r[0-9]+]], [[DESIRED]]
; CHECK: sub{{(\.w|s)?}} [[CMP1]], [[OLD]], [[CMP1]]
; CHECK: sub{{(\.w)?}} [[CMP1]], [[OLD]], [[CMP1]]
; CHECK: clz [[CMP2:r[0-9]+]], [[CMP1]]
; CHECK: lsr{{(s)?}} {{r[0-9]+}}, [[CMP2]], #5
; CHECK: dmb ish
@ -55,15 +51,13 @@ define { i16, i1 } @test_cmpxchg_16(i16* %addr, i16 %desired, i16 %new) nounwind
define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_32:
; CHECK-DAG: mov [[ADDR:r[0-9]+]], r0
; CHECK-DAG: mov [[NEW:r[0-9]+]], r2
; CHECK: dmb ish
; CHECK-NOT: uxt
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldrex [[OLD:r[0-9]+]], {{\[}}[[ADDR]]{{\]}}
; CHECK: ldrex [[OLD:r[0-9]+]], [r0]
; CHECK: cmp [[OLD]], [[DESIRED]]
; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: strex [[STATUS:r[0-9]+]], [[NEW]], {{\[}}[[ADDR]]{{\]}}
; CHECK: strex [[STATUS:r[0-9]+]], r2, [r0]
; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
; CHECK: bne [[RETRY]]
; CHECK: [[DONE]]:
@ -78,15 +72,14 @@ define { i32, i1 } @test_cmpxchg_32(i32* %addr, i32 %desired, i32 %new) nounwind
define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind {
; CHECK-LABEL: test_cmpxchg_64:
; CHECK: mov [[ADDR:r[0-9]+]], r0
; CHECK: dmb ish
; CHECK-NOT: uxt
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], {{\[}}[[ADDR]]{{\]}}
; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [r0]
; CHECK: cmp [[OLDLO]], r6
; CHECK: cmpeq [[OLDHI]], r7
; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: strexd [[STATUS:[lr0-9]+]], r8, r9, [r1]
; CHECK: strexd [[STATUS:[lr0-9]+]], r4, r5, [r0]
; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
; CHECK: bne [[RETRY]]
; CHECK: [[DONE]]:
@ -97,15 +90,14 @@ define { i64, i1 } @test_cmpxchg_64(i64* %addr, i64 %desired, i64 %new) nounwind
define { i64, i1 } @test_nontrivial_args(i64* %addr, i64 %desired, i64 %new) {
; CHECK-LABEL: test_nontrivial_args:
; CHECK: mov [[ADDR:r[0-9]+]], r0
; CHECK: dmb ish
; CHECK-NOT: uxt
; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], {{\[}}[[ADDR]]{{\]}}
; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [r0]
; CHECK: cmp [[OLDLO]], {{r[0-9]+}}
; CHECK: cmpeq [[OLDHI]], {{r[0-9]+}}
; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
; CHECK: strexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, {{\[}}[[ADDR]]{{\]}}
; CHECK: strexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r0]
; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
; CHECK: bne [[RETRY]]
; CHECK: [[DONE]]:

14
llvm/test/CodeGen/ARM/crash-greedy-v6.ll
View File

@ -14,21 +14,21 @@ for.body.lr.ph: ; preds = %entry
for.body: ; preds = %for.body, %for.body.lr.ph
; SOURCE-SCHED: ldr
; SOURCE-SCHED: ldr
; SOURCE-SCHED: ldr
; SOURCE-SCHED: ldr
; SOURCE-SCHED: ldr
; SOURCE-SCHED: add
; SOURCE-SCHED: add
; SOURCE-SCHED: add
; SOURCE-SCHED: add
; SOURCE-SCHED: ldr
; SOURCE-SCHED: add
; SOURCE-SCHED: ldr
; SOURCE-SCHED: add
; SOURCE-SCHED: ldr
; SOURCE-SCHED: add
; SOURCE-SCHED: str
; SOURCE-SCHED: str
; SOURCE-SCHED: str
; SOURCE-SCHED: str
; SOURCE-SCHED: ldr
; SOURCE-SCHED: bl
; SOURCE-SCHED: ldr
; SOURCE-SCHED: add
; SOURCE-SCHED: ldr
; SOURCE-SCHED: cmp
; SOURCE-SCHED: bne
%i.031 = phi i32 [ 0, %for.body.lr.ph ], [ %0, %for.body ]

3
llvm/test/CodeGen/ARM/debug-info-blocks.ll
View File

@ -6,7 +6,8 @@
; CHECK: DW_TAG_variable
; CHECK-NOT: DW_TAG
; CHECK-NEXT: DW_AT_location [DW_FORM_sec_offset]
; CHECK-NEXT: [0x{{.*}}, 0x{{.*}}): {{.*}} DW_OP_plus_uconst 0x4, DW_OP_deref, DW_OP_plus_uconst 0x18)
; CHECK-NEXT: [0x{{.*}}, 0x{{.*}}): {{.*}} DW_OP_plus_uconst 0x4, DW_OP_deref, DW_OP_plus_uconst 0x18
; CHECK-NEXT: [0x{{.*}}, 0x{{.*}}): {{.*}} DW_OP_plus_uconst 0x4, DW_OP_deref, DW_OP_plus_uconst 0x18
; CHECK-NEXT: DW_AT_name {{.*}} "mydata"
; Radar 9331779

52
llvm/test/CodeGen/ARM/fast-isel-call.ll
View File

@ -41,31 +41,38 @@ define void @foo(i8 %a, i16 %b) nounwind {
; ARM: foo
; THUMB: foo
;; Materialize i1 1
; ARM: movw [[REG0:r[0-9]+]], #1
; THUMB: movs [[REG0:r[0-9]+]], #1
; ARM: movw r2, #1
;; zero-ext
; ARM: and [[REG1:r[0-9]+]], [[REG0]], #1
; THUMB: and [[REG1:r[0-9]+]], [[REG0]], #1
; ARM: and r2, r2, #1
; THUMB: and r2, r2, #1
%1 = call i32 @t0(i1 zeroext 1)
; ARM: sxtb r0, {{r[0-9]+}}
; THUMB: sxtb r0, {{r[0-9]+}}
; ARM: sxtb r2, r1
; ARM: mov r0, r2
; THUMB: sxtb r2, r1
; THUMB: mov r0, r2
%2 = call i32 @t1(i8 signext %a)
; ARM: and r0, {{r[0-9]+}}, #255
; THUMB: and r0, {{r[0-9]+}}, #255
; ARM: and r2, r1, #255
; ARM: mov r0, r2
; THUMB: and r2, r1, #255
; THUMB: mov r0, r2
%3 = call i32 @t2(i8 zeroext %a)
; ARM: sxth r0, {{r[0-9]+}}
; THUMB: sxth r0, {{r[0-9]+}}
; ARM: sxth r2, r1
; ARM: mov r0, r2
; THUMB: sxth r2, r1
; THUMB: mov r0, r2
%4 = call i32 @t3(i16 signext %b)
; ARM: uxth r0, {{r[0-9]+}}
; THUMB: uxth r0, {{r[0-9]+}}
; ARM: uxth r2, r1
; ARM: mov r0, r2
; THUMB: uxth r2, r1
; THUMB: mov r0, r2
%5 = call i32 @t4(i16 zeroext %b)
;; A few test to check materialization
;; Note: i1 1 was materialized with t1 call
; ARM: movw {{r[0-9]+}}, #255
; ARM: movw r1, #255
%6 = call i32 @t2(i8 zeroext 255)
; ARM: movw {{r[0-9]+}}, #65535
; THUMB: movw {{r[0-9]+}}, #65535
; ARM: movw r1, #65535
; THUMB: movw r1, #65535
%7 = call i32 @t4(i16 zeroext 65535)
ret void
}
@ -105,9 +112,10 @@ entry:
; ARM: bl {{_?}}bar
; ARM-LONG-LABEL: @t10
; ARM-LONG-MACHO: {{(movw)|(ldr)}} [[R1:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}
; ARM-LONG-MACHO: {{(movt [[R1]], :upper16:L_bar\$non_lazy_ptr)?}}
; ARM-LONG-MACHO: ldr [[R:r[0-9]+]], {{\[}}[[R1]]]
; ARM-LONG-MACHO: {{(movw)|(ldr)}} [[R:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}
; ARM-LONG-MACHO: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}}
; ARM-LONG-MACHO: str [[R]], [r7, [[SLOT:#[-0-9]+]]] @ 4-byte Spill
; ARM-LONG-MACHO: ldr [[R:l?r[0-9]*]], [r7, [[SLOT]]] @ 4-byte Reload
; ARM-LONG-ELF: movw [[R:l?r[0-9]*]], :lower16:bar
; ARM-LONG-ELF: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}}
@ -130,9 +138,11 @@ entry:
; THUMB-DAG: str.w [[R4]], [sp, #4]
; THUMB: bl {{_?}}bar
; THUMB-LONG-LABEL: @t10
; THUMB-LONG: {{(movw)|(ldr.n)}} [[R1:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}
; THUMB-LONG: {{(movt [[R1]], :upper16:L_bar\$non_lazy_ptr)?}}
; THUMB-LONG: ldr{{(.w)?}} [[R:r[0-9]+]], {{\[}}[[R1]]{{\]}}
; THUMB-LONG: {{(movw)|(ldr.n)}} [[R:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}}
; THUMB-LONG: {{(movt [[R]], :upper16:L_bar\$non_lazy_ptr)?}}
; THUMB-LONG: ldr{{(.w)?}} [[R]], {{\[}}[[R]]{{\]}}
; THUMB-LONG: str [[R]], [sp, [[SLOT:#[-0-9]+]]] @ 4-byte Spill
; THUMB-LONG: ldr.w [[R:l?r[0-9]*]], [sp, [[SLOT]]] @ 4-byte Reload
; THUMB-LONG: blx [[R]]
%call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70)
ret i32 0

210
llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll
View File

@ -55,13 +55,16 @@ define void @t2() nounwind ssp {
; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG1:r[0-9]+]], [r0]
; ARM-MACHO: ldr r0, [r0]
; ARM-ELF: movw [[REG1:r[0-9]+]], :lower16:temp
; ARM-ELF: movt [[REG1]], :upper16:temp
; ARM-ELF: movw r0, :lower16:temp
; ARM-ELF: movt r0, :upper16:temp
; ARM: add r0, [[REG1]], #4
; ARM: add r1, [[REG1]], #16
; ARM: add r1, r0, #4
; ARM: add r0, r0, #16
; ARM: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
; ARM: mov r0, r1
; ARM: ldr r1, [sp[[SLOT]]] @ 4-byte Reload
; ARM: movw r2, #17
; ARM: bl {{_?}}memcpy
; ARM-LONG-LABEL: t2:
@ -77,9 +80,12 @@ define void @t2() nounwind ssp {
; THUMB-LABEL: t2:
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; THUMB: ldr [[REG1:r[0-9]+]], [r0]
; THUMB: adds r0, [[REG1]], #4
; THUMB: adds r1, #16
; THUMB: ldr r0, [r0]
; THUMB: adds r1, r0, #4
; THUMB: adds r0, #16
; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
; THUMB: mov r0, r1
; THUMB: ldr r1, [sp[[SLOT]]] @ 4-byte Reload
; THUMB: movs r2, #17
; THUMB: bl {{_?}}memcpy
; THUMB-LONG-LABEL: t2:
@ -98,14 +104,15 @@ define void @t3() nounwind ssp {
; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
; ARM-MACHO: ldr r0, [r0]
; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
; ARM-ELF: movt [[REG0]], :upper16:temp
; ARM-ELF: movw r0, :lower16:temp
; ARM-ELF: movt r0, :upper16:temp
; ARM: add r0, [[REG0]], #4
; ARM: add r1, [[REG0]], #16
; ARM: add r1, r0, #4
; ARM: add r0, r0, #16
; ARM: mov r0, r1
; ARM: movw r2, #10
; ARM: bl {{_?}}memmove
; ARM-LONG-LABEL: t3:
@ -121,9 +128,12 @@ define void @t3() nounwind ssp {
; THUMB-LABEL: t3:
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; THUMB: ldr [[REG1:r[0-9]+]], [r0]
; THUMB: adds r0, [[REG1]], #4
; THUMB: adds r1, #16
; THUMB: ldr r0, [r0]
; THUMB: adds r1, r0, #4
; THUMB: adds r0, #16
; THUMB: str r0, [sp[[SLOT:[, #0-9]*]]] @ 4-byte Spill
; THUMB: mov r0, r1
; THUMB: ldr r1, [sp[[SLOT]]] @ 4-byte Reload
; THUMB: movs r2, #10
; THUMB: bl {{_?}}memmove
; THUMB-LONG-LABEL: t3:
@ -140,28 +150,28 @@ define void @t4() nounwind ssp {
; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
; ARM-MACHO: ldr r0, [r0]
; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
; ARM-ELF: movt [[REG0]], :upper16:temp
; ARM-ELF: movw r0, :lower16:temp
; ARM-ELF: movt r0, :upper16:temp
; ARM: ldr [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16]
; ARM: str [[REG1]], {{\[}}[[REG0]], #4]
; ARM: ldr [[REG2:r[0-9]+]], {{\[}}[[REG0]], #20]
; ARM: str [[REG2]], {{\[}}[[REG0]], #8]
; ARM: ldrh [[REG3:r[0-9]+]], {{\[}}[[REG0]], #24]
; ARM: strh [[REG3]], {{\[}}[[REG0]], #12]
; ARM: ldr r1, [r0, #16]
; ARM: str r1, [r0, #4]
; ARM: ldr r1, [r0, #20]
; ARM: str r1, [r0, #8]
; ARM: ldrh r1, [r0, #24]
; ARM: strh r1, [r0, #12]
; ARM: bx lr
; THUMB-LABEL: t4:
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; THUMB: ldr [[REG1:r[0-9]+]], [r0]
; THUMB: ldr [[REG2:r[0-9]+]], {{\[}}[[REG1]], #16]
; THUMB: str [[REG2]], {{\[}}[[REG1]], #4]
; THUMB: ldr [[REG3:r[0-9]+]], {{\[}}[[REG1]], #20]
; THUMB: str [[REG3]], {{\[}}[[REG1]], #8]
; THUMB: ldrh [[REG4:r[0-9]+]], {{\[}}[[REG1]], #24]
; THUMB: strh [[REG4]], {{\[}}[[REG1]], #12]
; THUMB: ldr r0, [r0]
; THUMB: ldr r1, [r0, #16]
; THUMB: str r1, [r0, #4]
; THUMB: ldr r1, [r0, #20]
; THUMB: str r1, [r0, #8]
; THUMB: ldrh r1, [r0, #24]
; THUMB: strh r1, [r0, #12]
; THUMB: bx lr
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 4 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
ret void
@ -174,36 +184,36 @@ define void @t5() nounwind ssp {
; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
; ARM-MACHO: ldr r0, [r0]
; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
; ARM-ELF: movt [[REG0]], :upper16:temp
; ARM-ELF: movw r0, :lower16:temp
; ARM-ELF: movt r0, :upper16:temp
; ARM: ldrh [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16]
; ARM: strh [[REG1]], {{\[}}[[REG0]], #4]
; ARM: ldrh [[REG2:r[0-9]+]], {{\[}}[[REG0]], #18]
; ARM: strh [[REG2]], {{\[}}[[REG0]], #6]
; ARM: ldrh [[REG3:r[0-9]+]], {{\[}}[[REG0]], #20]
; ARM: strh [[REG3]], {{\[}}[[REG0]], #8]
; ARM: ldrh [[REG4:r[0-9]+]], {{\[}}[[REG0]], #22]
; ARM: strh [[REG4]], {{\[}}[[REG0]], #10]
; ARM: ldrh [[REG5:r[0-9]+]], {{\[}}[[REG0]], #24]
; ARM: strh [[REG5]], {{\[}}[[REG0]], #12]
; ARM: ldrh r1, [r0, #16]
; ARM: strh r1, [r0, #4]
; ARM: ldrh r1, [r0, #18]
; ARM: strh r1, [r0, #6]
; ARM: ldrh r1, [r0, #20]
; ARM: strh r1, [r0, #8]
; ARM: ldrh r1, [r0, #22]
; ARM: strh r1, [r0, #10]
; ARM: ldrh r1, [r0, #24]
; ARM: strh r1, [r0, #12]
; ARM: bx lr
; THUMB-LABEL: t5:
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; THUMB: ldr [[REG1:r[0-9]+]], [r0]
; THUMB: ldrh [[REG2:r[0-9]+]], {{\[}}[[REG1]], #16]
; THUMB: strh [[REG2]], {{\[}}[[REG1]], #4]
; THUMB: ldrh [[REG3:r[0-9]+]], {{\[}}[[REG1]], #18]
; THUMB: strh [[REG3]], {{\[}}[[REG1]], #6]
; THUMB: ldrh [[REG4:r[0-9]+]], {{\[}}[[REG1]], #20]
; THUMB: strh [[REG4]], {{\[}}[[REG1]], #8]
; THUMB: ldrh [[REG5:r[0-9]+]], {{\[}}[[REG1]], #22]
; THUMB: strh [[REG5]], {{\[}}[[REG1]], #10]
; THUMB: ldrh [[REG6:r[0-9]+]], {{\[}}[[REG1]], #24]
; THUMB: strh [[REG6]], {{\[}}[[REG1]], #12]
; THUMB: ldr r0, [r0]
; THUMB: ldrh r1, [r0, #16]
; THUMB: strh r1, [r0, #4]
; THUMB: ldrh r1, [r0, #18]
; THUMB: strh r1, [r0, #6]
; THUMB: ldrh r1, [r0, #20]
; THUMB: strh r1, [r0, #8]
; THUMB: ldrh r1, [r0, #22]
; THUMB: strh r1, [r0, #10]
; THUMB: ldrh r1, [r0, #24]
; THUMB: strh r1, [r0, #12]
; THUMB: bx lr
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 2 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
ret void
@ -214,56 +224,56 @@ define void @t6() nounwind ssp {
; ARM-MACHO: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr r0, .LCPI)}}
; ARM-MACHO: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; ARM-MACHO: ldr [[REG0:r[0-9]+]], [r0]
; ARM-MACHO: ldr r0, [r0]
; ARM-ELF: movw [[REG0:r[0-9]+]], :lower16:temp
; ARM-ELF: movt [[REG0]], :upper16:temp
; ARM-ELF: movw r0, :lower16:temp
; ARM-ELF: movt r0, :upper16:temp
; ARM: ldrb [[REG1:r[0-9]+]], {{\[}}[[REG0]], #16]
; ARM: strb [[REG1]], {{\[}}[[REG0]], #4]
; ARM: ldrb [[REG2:r[0-9]+]], {{\[}}[[REG0]], #17]
; ARM: strb [[REG2]], {{\[}}[[REG0]], #5]
; ARM: ldrb [[REG3:r[0-9]+]], {{\[}}[[REG0]], #18]
; ARM: strb [[REG3]], {{\[}}[[REG0]], #6]
; ARM: ldrb [[REG4:r[0-9]+]], {{\[}}[[REG0]], #19]
; ARM: strb [[REG4]], {{\[}}[[REG0]], #7]
; ARM: ldrb [[REG5:r[0-9]+]], {{\[}}[[REG0]], #20]
; ARM: strb [[REG5]], {{\[}}[[REG0]], #8]
; ARM: ldrb [[REG6:r[0-9]+]], {{\[}}[[REG0]], #21]
; ARM: strb [[REG6]], {{\[}}[[REG0]], #9]
; ARM: ldrb [[REG7:r[0-9]+]], {{\[}}[[REG0]], #22]
; ARM: strb [[REG7]], {{\[}}[[REG0]], #10]
; ARM: ldrb [[REG8:r[0-9]+]], {{\[}}[[REG0]], #23]
; ARM: strb [[REG8]], {{\[}}[[REG0]], #11]
; ARM: ldrb [[REG9:r[0-9]+]], {{\[}}[[REG0]], #24]
; ARM: strb [[REG9]], {{\[}}[[REG0]], #12]
; ARM: ldrb [[REG10:r[0-9]+]], {{\[}}[[REG0]], #25]
; ARM: strb [[REG10]], {{\[}}[[REG0]], #13]
; ARM: ldrb r1, [r0, #16]
; ARM: strb r1, [r0, #4]
; ARM: ldrb r1, [r0, #17]
; ARM: strb r1, [r0, #5]
; ARM: ldrb r1, [r0, #18]
; ARM: strb r1, [r0, #6]
; ARM: ldrb r1, [r0, #19]
; ARM: strb r1, [r0, #7]
; ARM: ldrb r1, [r0, #20]
; ARM: strb r1, [r0, #8]
; ARM: ldrb r1, [r0, #21]
; ARM: strb r1, [r0, #9]
; ARM: ldrb r1, [r0, #22]
; ARM: strb r1, [r0, #10]
; ARM: ldrb r1, [r0, #23]
; ARM: strb r1, [r0, #11]
; ARM: ldrb r1, [r0, #24]
; ARM: strb r1, [r0, #12]
; ARM: ldrb r1, [r0, #25]
; ARM: strb r1, [r0, #13]
; ARM: bx lr
; THUMB-LABEL: t6:
; THUMB: {{(movw r0, :lower16:L_temp\$non_lazy_ptr)|(ldr.n r0, .LCPI)}}
; THUMB: {{(movt r0, :upper16:L_temp\$non_lazy_ptr)?}}
; THUMB: ldr [[REG0:r[0-9]+]], [r0]
; THUMB: ldrb [[REG2:r[0-9]+]], {{\[}}[[REG0]], #16]
; THUMB: strb [[REG2]], {{\[}}[[REG0]], #4]
; THUMB: ldrb [[REG3:r[0-9]+]], {{\[}}[[REG0]], #17]
; THUMB: strb [[REG3]], {{\[}}[[REG0]], #5]
; THUMB: ldrb [[REG4:r[0-9]+]], {{\[}}[[REG0]], #18]
; THUMB: strb [[REG4]], {{\[}}[[REG0]], #6]
; THUMB: ldrb [[REG5:r[0-9]+]], {{\[}}[[REG0]], #19]
; THUMB: strb [[REG5]], {{\[}}[[REG0]], #7]
; THUMB: ldrb [[REG6:r[0-9]+]], {{\[}}[[REG0]], #20]
; THUMB: strb [[REG6]], {{\[}}[[REG0]], #8]
; THUMB: ldrb [[REG7:r[0-9]+]], {{\[}}[[REG0]], #21]
; THUMB: strb [[REG7]], {{\[}}[[REG0]], #9]
; THUMB: ldrb [[REG8:r[0-9]+]], {{\[}}[[REG0]], #22]
; THUMB: strb [[REG8]], {{\[}}[[REG0]], #10]
; THUMB: ldrb [[REG9:r[0-9]+]], {{\[}}[[REG0]], #23]
; THUMB: strb [[REG9]], {{\[}}[[REG0]], #11]
; THUMB: ldrb [[REG10:r[0-9]+]], {{\[}}[[REG0]], #24]
; THUMB: strb [[REG10]], {{\[}}[[REG0]], #12]
; THUMB: ldrb [[REG11:r[0-9]+]], {{\[}}[[REG0]], #25]
; THUMB: strb [[REG11]], {{\[}}[[REG0]], #13]
; THUMB: ldr r0, [r0]
; THUMB: ldrb r1, [r0, #16]
; THUMB: strb r1, [r0, #4]
; THUMB: ldrb r1, [r0, #17]
; THUMB: strb r1, [r0, #5]
; THUMB: ldrb r1, [r0, #18]
; THUMB: strb r1, [r0, #6]
; THUMB: ldrb r1, [r0, #19]
; THUMB: strb r1, [r0, #7]
; THUMB: ldrb r1, [r0, #20]
; THUMB: strb r1, [r0, #8]
; THUMB: ldrb r1, [r0, #21]
; THUMB: strb r1, [r0, #9]
; THUMB: ldrb r1, [r0, #22]
; THUMB: strb r1, [r0, #10]
; THUMB: ldrb r1, [r0, #23]
; THUMB: strb r1, [r0, #11]
; THUMB: ldrb r1, [r0, #24]
; THUMB: strb r1, [r0, #12]
; THUMB: ldrb r1, [r0, #25]
; THUMB: strb r1, [r0, #13]
; THUMB: bx lr
call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 4), i8* align 1 getelementptr inbounds ([60 x i8], [60 x i8]* @temp, i32 0, i32 16), i32 10, i1 false)
ret void

69
llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
View File

@ -2,7 +2,7 @@
define i32 @t1(i32* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t1:
; THUMB: t1
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -1
%0 = load i32, i32* %add.ptr, align 4
; THUMB: ldr r{{[0-9]}}, [r0, #-4]
@ -11,7 +11,7 @@ entry:
define i32 @t2(i32* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t2:
; THUMB: t2
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -63
%0 = load i32, i32* %add.ptr, align 4
; THUMB: ldr r{{[0-9]}}, [r0, #-252]
@ -20,7 +20,7 @@ entry:
define i32 @t3(i32* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t3:
; THUMB: t3
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64
%0 = load i32, i32* %add.ptr, align 4
; THUMB: ldr r{{[0-9]}}, [r0]
@ -29,7 +29,7 @@ entry:
define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t4:
; THUMB: t4
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1
%0 = load i16, i16* %add.ptr, align 2
; THUMB: ldrh r{{[0-9]}}, [r0, #-2]
@ -38,7 +38,7 @@ entry:
define zeroext i16 @t5(i16* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t5:
; THUMB: t5
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -127
%0 = load i16, i16* %add.ptr, align 2
; THUMB: ldrh r{{[0-9]}}, [r0, #-254]
@ -47,7 +47,7 @@ entry:
define zeroext i16 @t6(i16* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t6:
; THUMB: t6
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128
%0 = load i16, i16* %add.ptr, align 2
; THUMB: ldrh r{{[0-9]}}, [r0]
@ -56,7 +56,7 @@ entry:
define zeroext i8 @t7(i8* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t7:
; THUMB: t7
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1
%0 = load i8, i8* %add.ptr, align 1
; THUMB: ldrb r{{[0-9]}}, [r0, #-1]
@ -65,7 +65,7 @@ entry:
define zeroext i8 @t8(i8* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t8:
; THUMB: t8
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -255
%0 = load i8, i8* %add.ptr, align 1
; THUMB: ldrb r{{[0-9]}}, [r0, #-255]
@ -74,7 +74,7 @@ entry:
define zeroext i8 @t9(i8* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t9:
; THUMB: t9
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256
%0 = load i8, i8* %add.ptr, align 1
; THUMB: ldrb r{{[0-9]}}, [r0]
@ -83,96 +83,81 @@ entry:
define void @t10(i32* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t10:
; THUMB: t10
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -1
store i32 0, i32* %add.ptr, align 4
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: str r{{[0-9]}}, {{\[}}[[REG]], #-4]
; THUMB: str r{{[0-9]}}, [r0, #-4]
ret void
}
define void @t11(i32* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t11:
; THUMB: t11
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -63
store i32 0, i32* %add.ptr, align 4
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: str r{{[0-9]}}, {{\[}}[[REG]], #-252]
; THUMB: str r{{[0-9]}}, [r0, #-252]
ret void
}
define void @t12(i32* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t12:
; THUMB: t12
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64
store i32 0, i32* %add.ptr, align 4
; THUMB: movw [[REG:r[0-9]+]], #65280
; THUMB: movt [[REG]], #65535
; THUMB: add [[REG]], r0
; THUMB: str r{{[0-9]}}, {{\[}}[[REG]]]
; THUMB: str r{{[0-9]}}, [r0]
ret void
}
define void @t13(i16* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t13:
; THUMB: t13
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1
store i16 0, i16* %add.ptr, align 2
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strh r{{[0-9]}}, {{\[}}[[REG]], #-2]
; THUMB: strh r{{[0-9]}}, [r0, #-2]
ret void
}
define void @t14(i16* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t14:
; THUMB: t14
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -127
store i16 0, i16* %add.ptr, align 2
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strh r{{[0-9]}}, {{\[}}[[REG]], #-254]
; THUMB: strh r{{[0-9]}}, [r0, #-254]
ret void
}
define void @t15(i16* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t15:
; THUMB: t15
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128
store i16 0, i16* %add.ptr, align 2
; THUMB: movw [[REG:r[0-9]+]], #65280
; THUMB: movt [[REG]], #65535
; THUMB: add [[REG]], r0
; THUMB: strh r{{[0-9]}}, {{\[}}[[REG]]]
; THUMB: strh r{{[0-9]}}, [r0]
ret void
}
define void @t16(i8* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t16:
; THUMB: t16
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1
store i8 0, i8* %add.ptr, align 1
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strb r{{[0-9]}}, {{\[}}[[REG]], #-1]
; THUMB: strb r{{[0-9]}}, [r0, #-1]
ret void
}
define void @t17(i8* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t17:
; THUMB: t17
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -255
store i8 0, i8* %add.ptr, align 1
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strb r{{[0-9]}}, {{\[}}[[REG]], #-255]
; THUMB: strb r{{[0-9]}}, [r0, #-255]
ret void
}
define void @t18(i8* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t18:
; THUMB: t18
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256
store i8 0, i8* %add.ptr, align 1
; THUMB: movw [[REG:r[0-9]+]], #65280
; THUMB: movt [[REG]], #65535
; THUMB: add [[REG]], r0
; THUMB: strb r{{[0-9]}}, {{\[}}[[REG]]]
; THUMB: strb r{{[0-9]}}, [r0]
ret void
}

32
llvm/test/CodeGen/ARM/fast-isel-select.ll
View File

@ -21,12 +21,14 @@ entry:
define i32 @t2(i1 %c, i32 %a) nounwind readnone {
entry:
; ARM: t2
; ARM: tst {{r[0-9]+}}, #1
; ARM: moveq {{r[0-9]+}}, #20
; ARM: tst r0, #1
; ARM: moveq r{{[1-9]}}, #20
; ARM: mov r0, r{{[1-9]}}
; THUMB-LABEL: t2
; THUMB: tst.w {{r[0-9]+}}, #1
; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: moveq {{r[0-9]+}}, #20
; THUMB: moveq r{{[1-9]}}, #20
; THUMB: mov r0, r{{[1-9]}}
%0 = select i1 %c, i32 %a, i32 20
ret i32 %0
}
@ -41,7 +43,7 @@ entry:
; THUMB: tst.w r0, #1
; THUMB: it ne
; THUMB: movne r2, r1
; THUMB: adds r0, r2, r1
; THUMB: add.w r0, r2, r1
%0 = select i1 %c, i32 %a, i32 %b
%1 = add i32 %0, %a
ret i32 %1
@ -65,12 +67,14 @@ entry:
define i32 @t5(i1 %c, i32 %a) nounwind readnone {
entry:
; ARM: t5
; ARM: tst {{r[0-9]+}}, #1
; ARM: mvneq {{r[0-9]+}}, #1
; ARM: tst r0, #1
; ARM: mvneq r{{[1-9]}}, #1
; ARM: mov r0, r{{[1-9]}}
; THUMB: t5
; THUMB: tst.w {{r[0-9]+}}, #1
; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: mvneq {{r[0-9]+}}, #1
; THUMB: mvneq r{{[1-9]}}, #1
; THUMB: mov r0, r{{[1-9]}}
%0 = select i1 %c, i32 %a, i32 -2
ret i32 %0
}
@ -79,12 +83,14 @@ entry:
define i32 @t6(i1 %c, i32 %a) nounwind readnone {
entry:
; ARM: t6
; ARM: tst {{r[0-9]+}}, #1
; ARM: mvneq {{r[0-9]+}}, #978944
; ARM: tst r0, #1
; ARM: mvneq r{{[1-9]}}, #978944
; ARM: mov r0, r{{[1-9]}}
; THUMB: t6
; THUMB: tst.w {{r[0-9]+}}, #1
; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: mvneq {{r[0-9]+}}, #978944
; THUMB: mvneq r{{[1-9]}}, #978944
; THUMB: mov r0, r{{[1-9]}}
%0 = select i1 %c, i32 %a, i32 -978945
ret i32 %0
}

28
llvm/test/CodeGen/ARM/fast-isel-vararg.ll
View File

@ -17,24 +17,26 @@ entry:
%4 = load i32, i32* %n, align 4
; ARM: VarArg
; ARM: mov [[FP:r[0-9]+]], sp
; ARM: sub sp, sp, #32
; ARM: sub sp, sp, #{{(36|40)}}
; ARM: ldr r1, {{\[}}[[FP]], #-4]
; ARM: ldr r2, {{\[}}[[FP]], #-8]
; ARM: ldr r3, {{\[}}[[FP]], #-12]
; ARM: ldr [[Ra:r[0-9]+|lr]], [sp, #16]
; ARM: ldr [[Rb:[lr]+[0-9]*]], [sp, #12]
; ARM: movw r0, #5
; ARM: str [[Ra]], [sp]
; ARM: ldr [[Ra:r[0-9]+]], {{\[}}[[FP]], #-16]
; ARM: ldr [[Rb:[lr]+[0-9]*]], [sp, #{{(16|20)}}]
; ARM: movw [[Rc:[lr]+[0-9]*]], #5
; Ra got spilled
; ARM: mov r0, [[Rc]]
; ARM: str {{.*}}, [sp]
; ARM: str [[Rb]], [sp, #4]
; ARM: bl {{_?CallVariadic}}
; THUMB: sub sp, #32
; THUMB: ldr r1, [sp, #28]
; THUMB: ldr r2, [sp, #24]
; THUMB: ldr r3, [sp, #20]
; THUMB: ldr.w [[Ra:r[0-9]+]], [sp, #16]
; THUMB: ldr.w [[Rb:r[0-9]+]], [sp, #12]
; THUMB: str.w [[Ra]], [sp]
; THUMB: str.w [[Rb]], [sp, #4]
; THUMB: sub sp, #{{36}}
; THUMB: ldr r1, [sp, #32]
; THUMB: ldr r2, [sp, #28]
; THUMB: ldr r3, [sp, #24]
; THUMB: ldr {{[a-z0-9]+}}, [sp, #20]
; THUMB: ldr.w {{[a-z0-9]+}}, [sp, #16]
; THUMB: str.w {{[a-z0-9]+}}, [sp]
; THUMB: str.w {{[a-z0-9]+}}, [sp, #4]
; THUMB: bl {{_?}}CallVariadic
%call = call i32 (i32, ...) @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4)
store i32 %call, i32* %tmp, align 4

9
llvm/test/CodeGen/ARM/ldrd.ll
View File

@ -81,12 +81,11 @@ return: ; preds = %bb, %entry
; CHECK-LABEL: Func1:
define void @Func1() nounwind ssp "frame-pointer"="all" {
entry:
; A8: movw [[BASER:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}}
; A8: movt [[BASER]], :upper16:{{.*}}TestVar{{.*}}
; A8: ldr [[BASE:r[0-9]+]], {{\[}}[[BASER]]]
; A8: movw [[BASE:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}}
; A8: movt [[BASE]], :upper16:{{.*}}TestVar{{.*}}
; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], {{\[}}[[BASE]], #4]
; A8-NEXT: add [[FIELD2]], [[FIELD1]]
; A8-NEXT: str [[FIELD2]], {{\[}}[[BASE]]{{\]}}
; A8-NEXT: add [[FIELD1]], [[FIELD2]]
; A8-NEXT: str [[FIELD1]], {{\[}}[[BASE]]{{\]}}
; CONSERVATIVE-NOT: ldrd
%orig_blocks = alloca [256 x i16], align 2
%0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start.p0i8(i64 512, i8* %0) nounwind

28
llvm/test/CodeGen/ARM/legalize-bitcast.ll
View File

@ -14,17 +14,17 @@ define i32 @vec_to_int() {
; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: @ implicit-def: $d17
; CHECK-NEXT: vmov.32 d17[0], r0
; CHECK-NEXT: vrev32.16 d18, d17
; CHECK-NEXT: vrev32.16 d17, d17
; CHECK-NEXT: vrev16.8 d16, d16
; CHECK-NEXT: @ kill: def $d16 killed $d16 def $q8
; CHECK-NEXT: vmov.f64 d17, d18
; CHECK-NEXT: vstmia sp, {d16, d17} @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d18, d16
; CHECK-NEXT: vmov.f64 d19, d17
; CHECK-NEXT: vstmia sp, {d18, d19} @ 16-byte Spill
; CHECK-NEXT: b .LBB0_1
; CHECK-NEXT: .LBB0_1: @ %bb.1
; CHECK-NEXT: vldmia sp, {d16, d17} @ 16-byte Reload
; CHECK-NEXT: vrev32.16 q8, q8
; CHECK-NEXT: vmov.f64 d16, d17
; CHECK-NEXT: vmov.32 r0, d16[0]
; CHECK-NEXT: vrev32.16 q9, q8
; CHECK-NEXT: @ kill: def $d19 killed $d19 killed $q9
; CHECK-NEXT: vmov.32 r0, d19[0]
; CHECK-NEXT: add sp, sp, #28
; CHECK-NEXT: pop {r4}
; CHECK-NEXT: bx lr
@ -41,15 +41,15 @@ bb.1:
define i16 @int_to_vec(i80 %in) {
; CHECK-LABEL: int_to_vec:
; CHECK: @ %bb.0:
; CHECK-NEXT: @ kill: def $r2 killed $r1
; CHECK-NEXT: @ kill: def $r2 killed $r0
; CHECK-NEXT: mov r3, r1
; CHECK-NEXT: mov r12, r0
; CHECK-NEXT: lsl r0, r0, #16
; CHECK-NEXT: orr r0, r0, r1, lsr #16
; CHECK-NEXT: @ implicit-def: $d18
; CHECK-NEXT: vmov.32 d18[0], r0
; CHECK-NEXT: @ implicit-def: $q8
; CHECK-NEXT: vmov.f64 d16, d18
; CHECK-NEXT: vrev32.16 q8, q8
; CHECK-NEXT: @ implicit-def: $d16
; CHECK-NEXT: vmov.32 d16[0], r0
; CHECK-NEXT: @ implicit-def: $q9
; CHECK-NEXT: vmov.f64 d18, d16
; CHECK-NEXT: vrev32.16 q8, q9
; CHECK-NEXT: @ kill: def $d16 killed $d16 killed $q8
; CHECK-NEXT: vmov.u16 r0, d16[0]
; CHECK-NEXT: bx lr

18
llvm/test/CodeGen/ARM/pr47454.ll
View File

@ -16,23 +16,23 @@ define internal fastcc void @main() {
; CHECK-NEXT: ldrh r0, [r11, #-2]
; CHECK-NEXT: bl __gnu_h2f_ieee
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vstr s0, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: vstr s0, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: bl getConstant
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl __gnu_h2f_ieee
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl __gnu_f2h_ieee
; CHECK-NEXT: vldr s0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vldr s0, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl __gnu_f2h_ieee
; CHECK-NEXT: mov r1, r0
; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: uxth r1, r1
; CHECK-NEXT: vmov s0, r1
; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: vmov s1, r0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: uxth r1, r0
; CHECK-NEXT: vmov s1, r1
; CHECK-NEXT: bl isEqual
; CHECK-NEXT: mov sp, r11
; CHECK-NEXT: pop {r11, pc}

7
llvm/test/CodeGen/ARM/stack-guard-reassign.ll
View File

@ -3,12 +3,11 @@
; Verify that the offset assigned to the stack protector is at the top of the
; frame, covering the locals.
; CHECK-LABEL: fn:
; CHECK: sub sp, sp, #24
; CHECK: sub sp, sp, #32
; CHECK-NEXT: sub sp, sp, #65536
; CHECK-NEXT: ldr r1, .LCPI0_0
; CHECK-NEXT: str r1, [sp, #8]
; CHECK-NEXT: ldr r1, [r1]
; CHECK-NEXT: ldr r2, [r1]
; CHECK-NEXT: add lr, sp, #65536
; CHECK-NEXT: str r1, [lr, #20]
; CHECK-NEXT: str r2, [lr, #28]
; CHECK: .LCPI0_0:
; CHECK-NEXT: .long __stack_chk_guard

38
llvm/test/CodeGen/ARM/swifterror.ll
View File

@ -21,9 +21,9 @@ define float @foo(%swift_error** swifterror %error_ptr_ref) {
; CHECK-O0: mov r{{.*}}, #16
; CHECK-O0: malloc
; CHECK-O0: mov [[ID2:r[0-9]+]], r0
; CHECK-O0: mov r8, [[ID2]]
; CHECK-O0: mov [[ID:r[0-9]+]], #1
; CHECK-O0: strb [[ID]], {{\[}}[[ID2]], #8]
; CHECK-O0: strb [[ID]], [r0, #8]
; CHECK-O0: mov r8, [[ID2]]
entry:
%call = call i8* @malloc(i64 16)
%call.0 = bitcast i8* %call to %swift_error*
@ -49,16 +49,16 @@ define float @caller(i8* %error_ref) {
; CHECK-O0-LABEL: caller:
; spill r0
; CHECK-O0-DAG: mov r8, #0
; CHECK-O0-DAG: str r0, [sp[[SLOT:(, #[0-9]+)?]]]
; CHECK-O0-DAG: str r0, [sp, [[SLOT:#[0-9]+]]
; CHECK-O0: bl {{.*}}foo
; CHECK-O0: mov [[TMP:r[0-9]+]], r8
; CHECK-O0: str [[TMP]], [sp[[SLOT2:(, #[0-9]+)?]]]
; CHECK-O0: str [[TMP]], [sp]
; CHECK-O0: bne
; CHECK-O0: ldr [[ID:r[0-9]+]], [sp[[SLOT]]]
; CHECK-O0: ldrb [[CODE:r[0-9]+]], [r0, #8]
; CHECK-O0: ldr [[ID:r[0-9]+]], [sp, [[SLOT]]]
; CHECK-O0: strb [[CODE]], [{{.*}}[[ID]]]
; reload r0
; CHECK-O0: ldr r0, [sp[[SLOT2]]]
; CHECK-O0: ldr r0, [sp]
; CHECK-O0: free
entry:
%error_ptr_ref = alloca swifterror %swift_error*
@ -98,14 +98,14 @@ define float @caller2(i8* %error_ref) {
; CHECK-O0-DAG: mov r8, #0
; CHECK-O0: bl {{.*}}foo
; CHECK-O0: mov r{{.*}}, r8
; CHECK-O0: str r0, [sp{{(, #[0-9]+)?}}]
; CHECK-O0: str r0, [sp]
; CHECK-O0: bne
; CHECK-O0: ble
; CHECK-O0: ldrb [[CODE:r[0-9]+]], [r0, #8]
; reload r0
; CHECK-O0: ldr [[ID:r[0-9]+]],
; CHECK-O0: ldrb [[CODE:r[0-9]+]], [r0, #8]
; CHECK-O0: strb [[CODE]], [{{.*}}[[ID]]]
; CHECK-O0: ldr r0, [sp{{(, #[0-9]+)?}}]
; CHECK-O0: ldr r0, [sp]
; CHECK-O0: free
entry:
%error_ptr_ref = alloca swifterror %swift_error*
@ -143,15 +143,16 @@ define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) {
; CHECK-APPLE-DAG: strb [[ID]], [r{{.*}}, #8]
; CHECK-O0-LABEL: foo_if:
; CHECK-O0: cmp r0, #0
; spill to stack
; CHECK-O0: str r8
; CHECK-O0: cmp r0, #0
; CHECK-O0: beq
; CHECK-O0: mov r0, #16
; CHECK-O0: malloc
; CHECK-O0: mov [[ID:r[0-9]+]], r0
; CHECK-O0: mov [[ID2:[a-z0-9]+]], #1
; CHECK-O0: strb [[ID2]], {{\[}}[[ID]], #8]
; CHECK-O0: strb [[ID2]], [r0, #8]
; CHECK-O0: mov r8, [[ID]]
; reload from stack
; CHECK-O0: ldr r8
entry:
@ -232,18 +233,18 @@ define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swi
; CHECK-APPLE-DAG: str r{{.*}}, [{{.*}}[[SRET]], #4]
; CHECK-O0-LABEL: foo_sret:
; CHECK-O0-DAG: mov r{{.*}}, #16
; CHECK-O0: mov r{{.*}}, #16
; spill to stack: sret and val1
; CHECK-O0-DAG: str r0
; CHECK-O0-DAG: str r1
; CHECK-O0: malloc
; CHECK-O0: mov [[ID:r[0-9]+]], #1
; CHECK-O0: strb [[ID]], [r0, #8]
; reload from stack: sret and val1
; CHECK-O0: ldr
; CHECK-O0: ldr
; CHECK-O0-DAG: mov r8
; CHECK-O0-DAG: mov [[ID:r[0-9]+]], #1
; CHECK-O0-DAG: strb [[ID]], [{{r[0-9]+}}, #8]
; CHECK-O0-DAG: str r{{.*}}, [{{.*}}, #4]
; CHECK-O0: str r{{.*}}, [{{.*}}, #4]
; CHECK-O0: mov r8
entry:
%call = call i8* @malloc(i64 16)
%call.0 = bitcast i8* %call to %swift_error*
@ -270,15 +271,16 @@ define float @caller3(i8* %error_ref) {
; CHECK-O0-LABEL: caller3:
; CHECK-O0-DAG: mov r8, #0
; CHECK-O0-DAG: mov r0
; CHECK-O0-DAG: mov r1
; CHECK-O0: bl {{.*}}foo_sret
; CHECK-O0: mov [[ID2:r[0-9]+]], r8
; CHECK-O0: str [[ID2]], [sp[[SLOT:.*]]]
; CHECK-O0: cmp r8
; CHECK-O0: str [[ID2]], [sp[[SLOT:.*]]]
; CHECK-O0: bne
; Access part of the error object and save it to error_ref
; CHECK-O0: ldr [[ID:r[0-9]+]]
; CHECK-O0: ldrb [[CODE:r[0-9]+]]
; CHECK-O0: ldr [[ID:r[0-9]+]]
; CHECK-O0: strb [[CODE]], [{{.*}}[[ID]]]
; CHECK-O0: ldr r0, [sp[[SLOT]]
; CHECK-O0: bl {{.*}}free

2070
llvm/test/CodeGen/ARM/thumb-big-stack.ll
View File

File diff suppressed because it is too large Load Diff

18
llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll
View File

@ -1,13 +1,13 @@
; RUN: llc -march=hexagon -O0 -hexagon-align-loads=0 < %s | FileCheck %s
; CHECK-LABEL: danny:
; CHECK: r1 = r0
; CHECK-DAG: [[T0:r[0-9]+]] = memuh(r1+#0)
; CHECK-DAG: [[T1:r[0-9]+]] = memuh(r1+#2)
; CHECK: r2 |= asl([[T1]],#16)
; CHECK-DAG: [[T2:r[0-9]+]] = memuh(r1+#4)
; CHECK-DAG: [[T3:r[0-9]+]] = memuh(r1+#6)
; CHECK: r1 |= asl([[T3]],#16)
; CHECK-DAG: [[T0:r[0-9]+]] = memuh(r0+#0)
; CHECK-DAG: [[T1:r[0-9]+]] = memuh(r0+#2)
; CHECK: [[T0]] |= asl([[T1]],#16)
; CHECK-DAG: [[T2:r[0-9]+]] = memuh(r0+#4)
; CHECK-DAG: [[T3:r[0-9]+]] = memuh(r0+#6)
; CHECK: [[T2]] |= asl([[T3]],#16)
; CHECK: combine([[T2]],[[T0]])
define <4 x i16> @danny(<4 x i16>* %p) {
%t0 = load <4 x i16>, <4 x i16>* %p, align 2
ret <4 x i16> %t0
@ -15,8 +15,8 @@ define <4 x i16> @danny(<4 x i16>* %p) {
; CHECK-LABEL: sammy:
; CHECK-DAG: [[T0:r[0-9]+]] = memw(r0+#0)
; CHECK-DAG: r1 = memw(r0+#4)
; CHECK: r0 = [[T0]]
; CHECK-DAG: [[T1:r[0-9]+]] = memw(r0+#4)
; CHECK: combine([[T1]],[[T0]])
define <4 x i16> @sammy(<4 x i16>* %p) {
%t0 = load <4 x i16>, <4 x i16>* %p, align 4
ret <4 x i16> %t0

6
llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
View File

@ -244,12 +244,12 @@ define void @cxiiiiconv() {
; ALL-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
; ALL-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
; 32R1-DAG: sll $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24
; 32R1-DAG: sra $4, $[[REG_C1_1]], 24
; 32R2-DAG: seb $4, $[[REG_C1]]
; 32R1-DAG: sra $5, $[[REG_C1_1]], 24
; 32R2-DAG: seb $5, $[[REG_C1]]
; FIXME: andi is superfulous
; ALL-DAG: lw $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
; ALL-DAG: lbu $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]])
; ALL-DAG: andi $5, $[[REG_UC1]], 255
; ALL-DAG: andi $4, $[[REG_UC1]], 255
; ALL-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
; ALL-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
; 32R1-DAG: sll $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16

33
llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll
View File

@ -17,9 +17,15 @@ declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1)
define void @cpy(i8* %src, i32 %i) {
; ALL-LABEL: cpy:
; ALL: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
; ALL: lw $[[T2:[0-9]+]], %got(memcpy)(${{[0-9]+}})
; ALL: jalr $[[T2]]
; ALL-DAG: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
; ALL-DAG: sw $4, 24($sp)
; ALL-DAG: move $4, $[[T0]]
; ALL-DAG: sw $5, 20($sp)
; ALL-DAG: lw $[[T1:[0-9]+]], 24($sp)
; ALL-DAG: move $5, $[[T1]]
; ALL-DAG: lw $6, 20($sp)
; ALL-DAG: lw $[[T2:[0-9]+]], %got(memcpy)(${{[0-9]+}})
; ALL: jalr $[[T2]]
; ALL-NEXT: nop
; ALL-NOT: {{.*}}$2{{.*}}
call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0), i8* %src, i32 %i, i1 false)
@ -30,8 +36,14 @@ define void @mov(i8* %src, i32 %i) {
; ALL-LABEL: mov:
; ALL: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
; ALL: lw $[[T2:[0-9]+]], %got(memmove)(${{[0-9]+}})
; ALL-DAG: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
; ALL-DAG: sw $4, 24($sp)
; ALL-DAG: move $4, $[[T0]]
; ALL-DAG: sw $5, 20($sp)
; ALL-DAG: lw $[[T1:[0-9]+]], 24($sp)
; ALL-DAG: move $5, $[[T1]]
; ALL-DAG: lw $6, 20($sp)
; ALL-DAG: lw $[[T2:[0-9]+]], %got(memmove)(${{[0-9]+}})
; ALL: jalr $[[T2]]
; ALL-NEXT: nop
; ALL-NOT: {{.*}}$2{{.*}}
@ -42,8 +54,15 @@ define void @mov(i8* %src, i32 %i) {
define void @clear(i32 %i) {
; ALL-LABEL: clear:
; ALL: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
; ALL: lw $[[T2:[0-9]+]], %got(memset)(${{[0-9]+}})
; ALL-DAG: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
; ALL-DAG: sw $4, 16($sp)
; ALL-DAG: move $4, $[[T0]]
; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 42
; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T1]], 24
; 32R1-DAG: sra $5, $[[T2]], 24
; 32R2-DAG: seb $5, $[[T1]]
; ALL-DAG: lw $6, 16($sp)
; ALL-DAG: lw $[[T2:[0-9]+]], %got(memset)(${{[0-9]+}})
; ALL: jalr $[[T2]]
; ALL-NEXT: nop
; ALL-NOT: {{.*}}$2{{.*}}

5
llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll
View File

@ -5,10 +5,9 @@ define void @test(i32 %x, i1* %p) nounwind {
; CHECK-LABEL: test:
; CHECK: # %bb.0:
; CHECK-NEXT: move $1, $4
; CHECK-NEXT: move $4, $1
; CHECK-NEXT: andi $2, $4, 1
; CHECK-NEXT: sb $2, 0($5)
; CHECK-NEXT: andi $1, $1, 1
; CHECK-NEXT: sb $1, 0($5)
; CHECK-NEXT: andi $1, $4, 1
; CHECK-NEXT: bgtz $1, $BB0_1
; CHECK-NEXT: nop
; CHECK-NEXT: # %bb.1: # %foo

57
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
View File

@ -86,11 +86,12 @@ entry:
define i64 @add_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: add_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addu $2, $6, $4
; MIPS32-NEXT: sltu $3, $2, $4
; MIPS32-NEXT: addu $1, $7, $5
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: addu $3, $1, $3
; MIPS32-NEXT: addu $1, $6, $4
; MIPS32-NEXT: sltu $2, $1, $4
; MIPS32-NEXT: addu $3, $7, $5
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: addu $3, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -101,30 +102,34 @@ entry:
define i128 @add_i128(i128 %a, i128 %b) {
; MIPS32-LABEL: add_i128:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $8, $4
; MIPS32-NEXT: move $3, $5
; MIPS32-NEXT: move $4, $6
; MIPS32-NEXT: addiu $1, $sp, 16
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 20
; MIPS32-NEXT: lw $6, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: addiu $1, $sp, 24
; MIPS32-NEXT: lw $5, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 28
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: addu $2, $2, $8
; MIPS32-NEXT: sltu $8, $2, $8
; MIPS32-NEXT: addu $3, $6, $3
; MIPS32-NEXT: andi $8, $8, 1
; MIPS32-NEXT: addu $3, $3, $8
; MIPS32-NEXT: sltu $6, $3, $6
; MIPS32-NEXT: addiu $2, $sp, 28
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: addiu $3, $sp, 32
; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: addiu $8, $sp, 36
; MIPS32-NEXT: lw $8, 0($8)
; MIPS32-NEXT: addu $1, $1, $4
; MIPS32-NEXT: sltu $4, $1, $4
; MIPS32-NEXT: addu $5, $2, $5
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: addu $4, $5, $4
; MIPS32-NEXT: andi $6, $6, 1
; MIPS32-NEXT: addu $4, $4, $6
; MIPS32-NEXT: sltu $5, $4, $5
; MIPS32-NEXT: addu $1, $1, $7
; MIPS32-NEXT: andi $5, $5, 1
; MIPS32-NEXT: addu $5, $1, $5
; MIPS32-NEXT: sltu $2, $4, $2
; MIPS32-NEXT: addu $5, $3, $6
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: addu $2, $5, $2
; MIPS32-NEXT: sltu $3, $2, $3
; MIPS32-NEXT: addu $5, $8, $7
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: addu $5, $5, $3
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: move $3, $4
; MIPS32-NEXT: lw $4, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:

24
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll
View File

@ -4,9 +4,9 @@
define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
; P5600-LABEL: add_v16i8:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.b $w1, 0($4)
; P5600-NEXT: ld.b $w0, 0($5)
; P5600-NEXT: addv.b $w0, $w0, $w1
; P5600-NEXT: ld.b $w0, 0($4)
; P5600-NEXT: ld.b $w1, 0($5)
; P5600-NEXT: addv.b $w0, $w1, $w0
; P5600-NEXT: st.b $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
@ -21,9 +21,9 @@ entry:
define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
; P5600-LABEL: add_v8i16:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.h $w1, 0($4)
; P5600-NEXT: ld.h $w0, 0($5)
; P5600-NEXT: addv.h $w0, $w0, $w1
; P5600-NEXT: ld.h $w0, 0($4)
; P5600-NEXT: ld.h $w1, 0($5)
; P5600-NEXT: addv.h $w0, $w1, $w0
; P5600-NEXT: st.h $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
@ -38,9 +38,9 @@ entry:
define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
; P5600-LABEL: add_v4i32:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.w $w1, 0($4)
; P5600-NEXT: ld.w $w0, 0($5)
; P5600-NEXT: addv.w $w0, $w0, $w1
; P5600-NEXT: ld.w $w0, 0($4)
; P5600-NEXT: ld.w $w1, 0($5)
; P5600-NEXT: addv.w $w0, $w1, $w0
; P5600-NEXT: st.w $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
@ -55,9 +55,9 @@ entry:
define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
; P5600-LABEL: add_v2i64:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.d $w1, 0($4)
; P5600-NEXT: ld.d $w0, 0($5)
; P5600-NEXT: addv.d $w0, $w0, $w1
; P5600-NEXT: ld.d $w0, 0($4)
; P5600-NEXT: ld.d $w1, 0($5)
; P5600-NEXT: addv.d $w0, $w1, $w0
; P5600-NEXT: st.d $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop

28
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/aggregate_struct_return.ll
View File

@ -6,10 +6,10 @@ define { float, float } @add_complex_float({ float, float }* %a, { float, float
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lwc1 $f0, 0($4)
; MIPS32-NEXT: lwc1 $f1, 4($4)
; MIPS32-NEXT: lwc1 $f3, 0($5)
; MIPS32-NEXT: lwc1 $f2, 4($5)
; MIPS32-NEXT: add.s $f0, $f0, $f3
; MIPS32-NEXT: add.s $f2, $f1, $f2
; MIPS32-NEXT: lwc1 $f2, 0($5)
; MIPS32-NEXT: lwc1 $f3, 4($5)
; MIPS32-NEXT: add.s $f0, $f0, $f2
; MIPS32-NEXT: add.s $f2, $f1, $f3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -33,10 +33,10 @@ define { double, double } @add_complex_double({ double, double }* %a, { double,
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ldc1 $f0, 0($4)
; MIPS32-NEXT: ldc1 $f2, 8($4)
; MIPS32-NEXT: ldc1 $f6, 0($5)
; MIPS32-NEXT: ldc1 $f4, 8($5)
; MIPS32-NEXT: add.d $f0, $f0, $f6
; MIPS32-NEXT: add.d $f2, $f2, $f4
; MIPS32-NEXT: ldc1 $f4, 0($5)
; MIPS32-NEXT: ldc1 $f6, 8($5)
; MIPS32-NEXT: add.d $f0, $f0, $f4
; MIPS32-NEXT: add.d $f2, $f2, $f6
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -66,9 +66,9 @@ define void @call_ret_complex_float({ float, float }* %z) {
; MIPS32-NEXT: sw $4, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: jal ret_complex_float
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $4, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: swc1 $f0, 0($4)
; MIPS32-NEXT: swc1 $f2, 4($4)
; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: swc1 $f0, 0($1)
; MIPS32-NEXT: swc1 $f2, 4($1)
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
@ -95,9 +95,9 @@ define void @call_ret_complex_double({ double, double }* %z) {
; MIPS32-NEXT: sw $4, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: jal ret_complex_double
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $4, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($4)
; MIPS32-NEXT: sdc1 $f2, 8($4)
; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f2, 8($1)
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra

272
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll
View File

@ -6,64 +6,64 @@ declare i32 @llvm.bitreverse.i32(i32)
define i32 @bitreverse_i32(i32 signext %a) {
; MIPS32-LABEL: bitreverse_i32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sll $2, $4, 24
; MIPS32-NEXT: srl $1, $4, 24
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: sll $1, $4, 24
; MIPS32-NEXT: srl $2, $4, 24
; MIPS32-NEXT: or $1, $2, $1
; MIPS32-NEXT: andi $2, $4, 65280
; MIPS32-NEXT: sll $2, $2, 8
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: srl $2, $4, 8
; MIPS32-NEXT: andi $2, $2, 65280
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: lui $1, 61680
; MIPS32-NEXT: ori $3, $1, 61680
; MIPS32-NEXT: and $1, $2, $3
; MIPS32-NEXT: srl $1, $1, 4
; MIPS32-NEXT: sll $2, $2, 4
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: lui $1, 52428
; MIPS32-NEXT: ori $3, $1, 52428
; MIPS32-NEXT: and $1, $2, $3
; MIPS32-NEXT: srl $1, $1, 2
; MIPS32-NEXT: sll $2, $2, 2
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: lui $1, 43690
; MIPS32-NEXT: ori $3, $1, 43690
; MIPS32-NEXT: and $1, $2, $3
; MIPS32-NEXT: srl $1, $1, 1
; MIPS32-NEXT: sll $2, $2, 1
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: lui $2, 61680
; MIPS32-NEXT: ori $2, $2, 61680
; MIPS32-NEXT: and $3, $1, $2
; MIPS32-NEXT: srl $3, $3, 4
; MIPS32-NEXT: sll $1, $1, 4
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: or $1, $3, $1
; MIPS32-NEXT: lui $2, 52428
; MIPS32-NEXT: ori $2, $2, 52428
; MIPS32-NEXT: and $3, $1, $2
; MIPS32-NEXT: srl $3, $3, 2
; MIPS32-NEXT: sll $1, $1, 2
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: or $1, $3, $1
; MIPS32-NEXT: lui $2, 43690
; MIPS32-NEXT: ori $2, $2, 43690
; MIPS32-NEXT: and $3, $1, $2
; MIPS32-NEXT: srl $3, $3, 1
; MIPS32-NEXT: sll $1, $1, 1
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: or $2, $3, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R2-LABEL: bitreverse_i32:
; MIPS32R2: # %bb.0: # %entry
; MIPS32R2-NEXT: wsbh $1, $4
; MIPS32R2-NEXT: rotr $2, $1, 16
; MIPS32R2-NEXT: lui $1, 61680
; MIPS32R2-NEXT: ori $3, $1, 61680
; MIPS32R2-NEXT: and $1, $2, $3
; MIPS32R2-NEXT: srl $1, $1, 4
; MIPS32R2-NEXT: sll $2, $2, 4
; MIPS32R2-NEXT: and $2, $2, $3
; MIPS32R2-NEXT: or $2, $1, $2
; MIPS32R2-NEXT: lui $1, 52428
; MIPS32R2-NEXT: ori $3, $1, 52428
; MIPS32R2-NEXT: and $1, $2, $3
; MIPS32R2-NEXT: srl $1, $1, 2
; MIPS32R2-NEXT: sll $2, $2, 2
; MIPS32R2-NEXT: and $2, $2, $3
; MIPS32R2-NEXT: or $2, $1, $2
; MIPS32R2-NEXT: lui $1, 43690
; MIPS32R2-NEXT: ori $3, $1, 43690
; MIPS32R2-NEXT: and $1, $2, $3
; MIPS32R2-NEXT: srl $1, $1, 1
; MIPS32R2-NEXT: sll $2, $2, 1
; MIPS32R2-NEXT: and $2, $2, $3
; MIPS32R2-NEXT: or $2, $1, $2
; MIPS32R2-NEXT: rotr $1, $1, 16
; MIPS32R2-NEXT: lui $2, 61680
; MIPS32R2-NEXT: ori $2, $2, 61680
; MIPS32R2-NEXT: and $3, $1, $2
; MIPS32R2-NEXT: srl $3, $3, 4
; MIPS32R2-NEXT: sll $1, $1, 4
; MIPS32R2-NEXT: and $1, $1, $2
; MIPS32R2-NEXT: or $1, $3, $1
; MIPS32R2-NEXT: lui $2, 52428
; MIPS32R2-NEXT: ori $2, $2, 52428
; MIPS32R2-NEXT: and $3, $1, $2
; MIPS32R2-NEXT: srl $3, $3, 2
; MIPS32R2-NEXT: sll $1, $1, 2
; MIPS32R2-NEXT: and $1, $1, $2
; MIPS32R2-NEXT: or $1, $3, $1
; MIPS32R2-NEXT: lui $2, 43690
; MIPS32R2-NEXT: ori $2, $2, 43690
; MIPS32R2-NEXT: and $3, $1, $2
; MIPS32R2-NEXT: srl $3, $3, 1
; MIPS32R2-NEXT: sll $1, $1, 1
; MIPS32R2-NEXT: and $1, $1, $2
; MIPS32R2-NEXT: or $2, $3, $1
; MIPS32R2-NEXT: jr $ra
; MIPS32R2-NEXT: nop
entry:
@ -75,107 +75,107 @@ declare i64 @llvm.bitreverse.i64(i64)
define i64 @bitreverse_i64(i64 signext %a) {
; MIPS32-LABEL: bitreverse_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $3, $4
; MIPS32-NEXT: sll $2, $5, 24
; MIPS32-NEXT: srl $1, $5, 24
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: sll $1, $5, 24
; MIPS32-NEXT: srl $2, $5, 24
; MIPS32-NEXT: or $1, $2, $1
; MIPS32-NEXT: andi $2, $5, 65280
; MIPS32-NEXT: sll $2, $2, 8
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: srl $2, $5, 8
; MIPS32-NEXT: andi $2, $2, 65280
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: lui $1, 61680
; MIPS32-NEXT: ori $6, $1, 61680
; MIPS32-NEXT: and $1, $2, $6
; MIPS32-NEXT: srl $1, $1, 4
; MIPS32-NEXT: sll $2, $2, 4
; MIPS32-NEXT: and $2, $2, $6
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: lui $1, 52428
; MIPS32-NEXT: ori $5, $1, 52428
; MIPS32-NEXT: and $1, $2, $5
; MIPS32-NEXT: srl $1, $1, 2
; MIPS32-NEXT: sll $2, $2, 2
; MIPS32-NEXT: and $2, $2, $5
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: lui $1, 43690
; MIPS32-NEXT: ori $4, $1, 43690
; MIPS32-NEXT: and $1, $2, $4
; MIPS32-NEXT: srl $1, $1, 1
; MIPS32-NEXT: sll $2, $2, 1
; MIPS32-NEXT: and $2, $2, $4
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: sll $7, $3, 24
; MIPS32-NEXT: srl $1, $3, 24
; MIPS32-NEXT: or $1, $1, $7
; MIPS32-NEXT: andi $7, $3, 65280
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: lui $2, 61680
; MIPS32-NEXT: ori $2, $2, 61680
; MIPS32-NEXT: and $3, $1, $2
; MIPS32-NEXT: srl $3, $3, 4
; MIPS32-NEXT: sll $1, $1, 4
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: or $1, $3, $1
; MIPS32-NEXT: lui $3, 52428
; MIPS32-NEXT: ori $3, $3, 52428
; MIPS32-NEXT: and $5, $1, $3
; MIPS32-NEXT: srl $5, $5, 2
; MIPS32-NEXT: sll $1, $1, 2
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: or $1, $5, $1
; MIPS32-NEXT: lui $5, 43690
; MIPS32-NEXT: ori $5, $5, 43690
; MIPS32-NEXT: and $6, $1, $5
; MIPS32-NEXT: srl $6, $6, 1
; MIPS32-NEXT: sll $1, $1, 1
; MIPS32-NEXT: and $1, $1, $5
; MIPS32-NEXT: or $1, $6, $1
; MIPS32-NEXT: sll $6, $4, 24
; MIPS32-NEXT: srl $7, $4, 24
; MIPS32-NEXT: or $6, $7, $6
; MIPS32-NEXT: andi $7, $4, 65280
; MIPS32-NEXT: sll $7, $7, 8
; MIPS32-NEXT: or $1, $1, $7
; MIPS32-NEXT: srl $3, $3, 8
; MIPS32-NEXT: andi $3, $3, 65280
; MIPS32-NEXT: or $3, $1, $3
; MIPS32-NEXT: and $1, $3, $6
; MIPS32-NEXT: srl $1, $1, 4
; MIPS32-NEXT: sll $3, $3, 4
; MIPS32-NEXT: and $3, $3, $6
; MIPS32-NEXT: or $3, $1, $3
; MIPS32-NEXT: and $1, $3, $5
; MIPS32-NEXT: srl $1, $1, 2
; MIPS32-NEXT: sll $3, $3, 2
; MIPS32-NEXT: and $3, $3, $5
; MIPS32-NEXT: or $3, $1, $3
; MIPS32-NEXT: and $1, $3, $4
; MIPS32-NEXT: srl $1, $1, 1
; MIPS32-NEXT: sll $3, $3, 1
; MIPS32-NEXT: and $3, $3, $4
; MIPS32-NEXT: or $3, $1, $3
; MIPS32-NEXT: or $6, $6, $7
; MIPS32-NEXT: srl $4, $4, 8
; MIPS32-NEXT: andi $4, $4, 65280
; MIPS32-NEXT: or $4, $6, $4
; MIPS32-NEXT: and $6, $4, $2
; MIPS32-NEXT: srl $6, $6, 4
; MIPS32-NEXT: sll $4, $4, 4
; MIPS32-NEXT: and $2, $4, $2
; MIPS32-NEXT: or $2, $6, $2
; MIPS32-NEXT: and $4, $2, $3
; MIPS32-NEXT: srl $4, $4, 2
; MIPS32-NEXT: sll $2, $2, 2
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: or $2, $4, $2
; MIPS32-NEXT: and $3, $2, $5
; MIPS32-NEXT: srl $3, $3, 1
; MIPS32-NEXT: sll $2, $2, 1
; MIPS32-NEXT: and $2, $2, $5
; MIPS32-NEXT: or $3, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R2-LABEL: bitreverse_i64:
; MIPS32R2: # %bb.0: # %entry
; MIPS32R2-NEXT: move $1, $4
; MIPS32R2-NEXT: wsbh $2, $5
; MIPS32R2-NEXT: rotr $3, $2, 16
; MIPS32R2-NEXT: wsbh $1, $5
; MIPS32R2-NEXT: rotr $1, $1, 16
; MIPS32R2-NEXT: lui $2, 61680
; MIPS32R2-NEXT: ori $6, $2, 61680
; MIPS32R2-NEXT: and $2, $3, $6
; MIPS32R2-NEXT: srl $2, $2, 4
; MIPS32R2-NEXT: sll $3, $3, 4
; MIPS32R2-NEXT: and $3, $3, $6
; MIPS32R2-NEXT: or $3, $2, $3
; MIPS32R2-NEXT: lui $2, 52428
; MIPS32R2-NEXT: ori $5, $2, 52428
; MIPS32R2-NEXT: and $2, $3, $5
; MIPS32R2-NEXT: srl $2, $2, 2
; MIPS32R2-NEXT: sll $3, $3, 2
; MIPS32R2-NEXT: and $3, $3, $5
; MIPS32R2-NEXT: or $3, $2, $3
; MIPS32R2-NEXT: lui $2, 43690
; MIPS32R2-NEXT: ori $4, $2, 43690
; MIPS32R2-NEXT: and $2, $3, $4
; MIPS32R2-NEXT: srl $2, $2, 1
; MIPS32R2-NEXT: sll $3, $3, 1
; MIPS32R2-NEXT: and $3, $3, $4
; MIPS32R2-NEXT: or $2, $2, $3
; MIPS32R2-NEXT: wsbh $1, $1
; MIPS32R2-NEXT: rotr $3, $1, 16
; MIPS32R2-NEXT: and $1, $3, $6
; MIPS32R2-NEXT: srl $1, $1, 4
; MIPS32R2-NEXT: sll $3, $3, 4
; MIPS32R2-NEXT: and $3, $3, $6
; MIPS32R2-NEXT: or $3, $1, $3
; MIPS32R2-NEXT: and $1, $3, $5
; MIPS32R2-NEXT: srl $1, $1, 2
; MIPS32R2-NEXT: sll $3, $3, 2
; MIPS32R2-NEXT: and $3, $3, $5
; MIPS32R2-NEXT: or $3, $1, $3
; MIPS32R2-NEXT: and $1, $3, $4
; MIPS32R2-NEXT: srl $1, $1, 1
; MIPS32R2-NEXT: sll $3, $3, 1
; MIPS32R2-NEXT: and $3, $3, $4
; MIPS32R2-NEXT: or $3, $1, $3
; MIPS32R2-NEXT: ori $2, $2, 61680
; MIPS32R2-NEXT: and $3, $1, $2
; MIPS32R2-NEXT: srl $3, $3, 4
; MIPS32R2-NEXT: sll $1, $1, 4
; MIPS32R2-NEXT: and $1, $1, $2
; MIPS32R2-NEXT: or $1, $3, $1
; MIPS32R2-NEXT: lui $3, 52428
; MIPS32R2-NEXT: ori $3, $3, 52428
; MIPS32R2-NEXT: and $5, $1, $3
; MIPS32R2-NEXT: srl $5, $5, 2
; MIPS32R2-NEXT: sll $1, $1, 2
; MIPS32R2-NEXT: and $1, $1, $3
; MIPS32R2-NEXT: or $1, $5, $1
; MIPS32R2-NEXT: lui $5, 43690
; MIPS32R2-NEXT: ori $5, $5, 43690
; MIPS32R2-NEXT: and $6, $1, $5
; MIPS32R2-NEXT: srl $6, $6, 1
; MIPS32R2-NEXT: sll $1, $1, 1
; MIPS32R2-NEXT: and $1, $1, $5
; MIPS32R2-NEXT: or $1, $6, $1
; MIPS32R2-NEXT: wsbh $4, $4
; MIPS32R2-NEXT: rotr $4, $4, 16
; MIPS32R2-NEXT: and $6, $4, $2
; MIPS32R2-NEXT: srl $6, $6, 4
; MIPS32R2-NEXT: sll $4, $4, 4
; MIPS32R2-NEXT: and $2, $4, $2
; MIPS32R2-NEXT: or $2, $6, $2
; MIPS32R2-NEXT: and $4, $2, $3
; MIPS32R2-NEXT: srl $4, $4, 2
; MIPS32R2-NEXT: sll $2, $2, 2
; MIPS32R2-NEXT: and $2, $2, $3
; MIPS32R2-NEXT: or $2, $4, $2
; MIPS32R2-NEXT: and $3, $2, $5
; MIPS32R2-NEXT: srl $3, $3, 1
; MIPS32R2-NEXT: sll $2, $2, 1
; MIPS32R2-NEXT: and $2, $2, $5
; MIPS32R2-NEXT: or $3, $3, $2
; MIPS32R2-NEXT: move $2, $1
; MIPS32R2-NEXT: jr $ra
; MIPS32R2-NEXT: nop
entry:

132
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
View File

@ -320,10 +320,10 @@ define i8 @ashr_i8(i8 %a) {
; MIPS32-LABEL: ashr_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 2
; MIPS32-NEXT: andi $2, $1, 255
; MIPS32-NEXT: sll $1, $4, 24
; MIPS32-NEXT: sra $1, $1, 24
; MIPS32-NEXT: srav $2, $1, $2
; MIPS32-NEXT: andi $1, $1, 255
; MIPS32-NEXT: sll $2, $4, 24
; MIPS32-NEXT: sra $2, $2, 24
; MIPS32-NEXT: srav $2, $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -335,9 +335,9 @@ define i16 @lshr_i16(i16 %a) {
; MIPS32-LABEL: lshr_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 2
; MIPS32-NEXT: andi $2, $1, 65535
; MIPS32-NEXT: andi $1, $4, 65535
; MIPS32-NEXT: srlv $2, $1, $2
; MIPS32-NEXT: andi $1, $1, 65535
; MIPS32-NEXT: andi $2, $4, 65535
; MIPS32-NEXT: srlv $2, $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -348,25 +348,29 @@ entry:
define i64 @shl_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: shl_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $3, $4
; MIPS32-NEXT: move $9, $6
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: ori $1, $zero, 32
; MIPS32-NEXT: subu $8, $9, $1
; MIPS32-NEXT: subu $4, $1, $9
; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: sltu $6, $9, $1
; MIPS32-NEXT: sltiu $1, $9, 1
; MIPS32-NEXT: sllv $7, $3, $9
; MIPS32-NEXT: srlv $4, $3, $4
; MIPS32-NEXT: sllv $9, $5, $9
; MIPS32-NEXT: or $4, $4, $9
; MIPS32-NEXT: sllv $3, $3, $8
; MIPS32-NEXT: andi $8, $6, 1
; MIPS32-NEXT: movn $2, $7, $8
; MIPS32-NEXT: andi $6, $6, 1
; MIPS32-NEXT: movn $3, $4, $6
; MIPS32-NEXT: subu $2, $6, $1
; MIPS32-NEXT: subu $3, $1, $6
; MIPS32-NEXT: ori $8, $zero, 0
; MIPS32-NEXT: sltu $1, $6, $1
; MIPS32-NEXT: sltiu $9, $6, 1
; MIPS32-NEXT: sllv $10, $4, $6
; MIPS32-NEXT: srlv $3, $4, $3
; MIPS32-NEXT: sllv $6, $5, $6
; MIPS32-NEXT: or $3, $3, $6
; MIPS32-NEXT: sllv $2, $4, $2
; MIPS32-NEXT: andi $4, $1, 1
; MIPS32-NEXT: movn $8, $10, $4
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn $3, $5, $1
; MIPS32-NEXT: movn $2, $3, $1
; MIPS32-NEXT: andi $1, $9, 1
; MIPS32-NEXT: movn $2, $5, $1
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $2, $8
; MIPS32-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -377,30 +381,24 @@ entry:
define i64 @ashl_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: ashl_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: sw $4, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $2, $5
; MIPS32-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: move $3, $6
; MIPS32-NEXT: ori $1, $zero, 32
; MIPS32-NEXT: subu $8, $3, $1
; MIPS32-NEXT: subu $7, $1, $3
; MIPS32-NEXT: sltu $4, $3, $1
; MIPS32-NEXT: sltiu $6, $3, 1
; MIPS32-NEXT: srav $1, $2, $3
; MIPS32-NEXT: srlv $3, $5, $3
; MIPS32-NEXT: sllv $7, $2, $7
; MIPS32-NEXT: or $7, $3, $7
; MIPS32-NEXT: sra $3, $2, 31
; MIPS32-NEXT: srav $2, $2, $8
; MIPS32-NEXT: andi $8, $4, 1
; MIPS32-NEXT: movn $2, $7, $8
; MIPS32-NEXT: andi $6, $6, 1
; MIPS32-NEXT: movn $2, $5, $6
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: movn $3, $1, $4
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: subu $2, $6, $1
; MIPS32-NEXT: subu $3, $1, $6
; MIPS32-NEXT: sltu $1, $6, $1
; MIPS32-NEXT: sltiu $8, $6, 1
; MIPS32-NEXT: srav $9, $5, $6
; MIPS32-NEXT: srlv $6, $4, $6
; MIPS32-NEXT: sllv $3, $5, $3
; MIPS32-NEXT: or $3, $6, $3
; MIPS32-NEXT: sra $6, $5, 31
; MIPS32-NEXT: srav $2, $5, $2
; MIPS32-NEXT: andi $5, $1, 1
; MIPS32-NEXT: movn $2, $3, $5
; MIPS32-NEXT: andi $3, $8, 1
; MIPS32-NEXT: movn $2, $4, $3
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn $6, $9, $1
; MIPS32-NEXT: move $3, $6
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -411,30 +409,24 @@ entry:
define i64 @lshr_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: lshr_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: sw $4, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $2, $5
; MIPS32-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: move $7, $6
; MIPS32-NEXT: ori $1, $zero, 32
; MIPS32-NEXT: subu $8, $7, $1
; MIPS32-NEXT: subu $9, $1, $7
; MIPS32-NEXT: ori $3, $zero, 0
; MIPS32-NEXT: sltu $4, $7, $1
; MIPS32-NEXT: sltiu $6, $7, 1
; MIPS32-NEXT: srlv $1, $2, $7
; MIPS32-NEXT: srlv $7, $5, $7
; MIPS32-NEXT: sllv $9, $2, $9
; MIPS32-NEXT: or $7, $7, $9
; MIPS32-NEXT: srlv $2, $2, $8
; MIPS32-NEXT: andi $8, $4, 1
; MIPS32-NEXT: movn $2, $7, $8
; MIPS32-NEXT: andi $6, $6, 1
; MIPS32-NEXT: movn $2, $5, $6
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: movn $3, $1, $4
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: subu $2, $6, $1
; MIPS32-NEXT: subu $3, $1, $6
; MIPS32-NEXT: ori $8, $zero, 0
; MIPS32-NEXT: sltu $1, $6, $1
; MIPS32-NEXT: sltiu $9, $6, 1
; MIPS32-NEXT: srlv $10, $5, $6
; MIPS32-NEXT: srlv $6, $4, $6
; MIPS32-NEXT: sllv $3, $5, $3
; MIPS32-NEXT: or $3, $6, $3
; MIPS32-NEXT: srlv $2, $5, $2
; MIPS32-NEXT: andi $5, $1, 1
; MIPS32-NEXT: movn $2, $3, $5
; MIPS32-NEXT: andi $3, $9, 1
; MIPS32-NEXT: movn $2, $4, $3
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn $8, $10, $1
; MIPS32-NEXT: move $3, $8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:

8
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll
View File

@ -30,21 +30,21 @@ define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) {
; MIPS32: # %bb.0:
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: sw $5, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: sw $5, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB1_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1:
; MIPS32-NEXT: j $BB1_3
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_2: # %if.then
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_3: # %if.else
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop

10
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/brindirect.ll
View File

@ -6,19 +6,19 @@ define i32 @indirectbr(i8 *%addr) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 1
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: jr $4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_1: # %L1
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_2: # %L2
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop

18
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll
View File

@ -6,9 +6,9 @@ declare i32 @llvm.bswap.i32(i32)
define i32 @bswap_i32(i32 %x) {
; MIPS32-LABEL: bswap_i32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sll $2, $4, 24
; MIPS32-NEXT: srl $1, $4, 24
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: sll $1, $4, 24
; MIPS32-NEXT: srl $2, $4, 24
; MIPS32-NEXT: or $1, $2, $1
; MIPS32-NEXT: andi $2, $4, 65280
; MIPS32-NEXT: sll $2, $2, 8
; MIPS32-NEXT: or $1, $1, $2
@ -33,18 +33,18 @@ declare i64 @llvm.bswap.i64(i64)
define i64 @bswap_i64(i64 %x) {
; MIPS32-LABEL: bswap_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sll $2, $5, 24
; MIPS32-NEXT: srl $1, $5, 24
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: sll $1, $5, 24
; MIPS32-NEXT: srl $2, $5, 24
; MIPS32-NEXT: or $1, $2, $1
; MIPS32-NEXT: andi $2, $5, 65280
; MIPS32-NEXT: sll $2, $2, 8
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: srl $2, $5, 8
; MIPS32-NEXT: andi $2, $2, 65280
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: sll $3, $4, 24
; MIPS32-NEXT: srl $1, $4, 24
; MIPS32-NEXT: or $1, $1, $3
; MIPS32-NEXT: sll $1, $4, 24
; MIPS32-NEXT: srl $3, $4, 24
; MIPS32-NEXT: or $1, $3, $1
; MIPS32-NEXT: andi $3, $4, 65280
; MIPS32-NEXT: sll $3, $3, 8
; MIPS32-NEXT: or $1, $1, $3

18
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/call.ll
View File

@ -29,10 +29,11 @@ define i32 @call_global(i32 %a0, i32 %a1, i32 %x, i32 %y) {
; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 24
; MIPS32_PIC-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: .cfi_offset 31, -4
; MIPS32_PIC-NEXT: addu $gp, $2, $25
; MIPS32_PIC-NEXT: addu $1, $2, $25
; MIPS32_PIC-NEXT: lw $25, %call16(f)($1)
; MIPS32_PIC-NEXT: move $4, $6
; MIPS32_PIC-NEXT: move $5, $7
; MIPS32_PIC-NEXT: lw $25, %call16(f)($gp)
; MIPS32_PIC-NEXT: move $gp, $1
; MIPS32_PIC-NEXT: jalr $25
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: addu $2, $2, $2
@ -88,11 +89,12 @@ define i32 @call_global_with_local_linkage(i32 %a0, i32 %a1, i32 %x, i32 %y) {
; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 24
; MIPS32_PIC-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: .cfi_offset 31, -4
; MIPS32_PIC-NEXT: addu $gp, $2, $25
; MIPS32_PIC-NEXT: addu $1, $2, $25
; MIPS32_PIC-NEXT: lw $2, %got(f_with_local_linkage)($1)
; MIPS32_PIC-NEXT: addiu $25, $2, %lo(f_with_local_linkage)
; MIPS32_PIC-NEXT: move $4, $6
; MIPS32_PIC-NEXT: move $5, $7
; MIPS32_PIC-NEXT: lw $1, %got(f_with_local_linkage)($gp)
; MIPS32_PIC-NEXT: addiu $25, $1, %lo(f_with_local_linkage)
; MIPS32_PIC-NEXT: move $gp, $1
; MIPS32_PIC-NEXT: jalr $25
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: addu $2, $2, $2
@ -113,9 +115,10 @@ define i32 @call_reg(i32 (i32, i32)* %f_ptr, i32 %x, i32 %y) {
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: move $25, $4
; MIPS32-NEXT: sw $4, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $4, $5
; MIPS32-NEXT: move $5, $6
; MIPS32-NEXT: lw $25, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: jalr $25
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
@ -129,9 +132,10 @@ define i32 @call_reg(i32 (i32, i32)* %f_ptr, i32 %x, i32 %y) {
; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 24
; MIPS32_PIC-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: .cfi_offset 31, -4
; MIPS32_PIC-NEXT: move $25, $4
; MIPS32_PIC-NEXT: sw $4, 16($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: move $4, $5
; MIPS32_PIC-NEXT: move $5, $6
; MIPS32_PIC-NEXT: lw $25, 16($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: jalr $25
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload

14
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll
View File

@ -17,14 +17,14 @@ declare i32 @llvm.ctlz.i32(i32, i1 immarg)
define i64 @ctlz_i64(i64 %a) {
; MIPS32-LABEL: ctlz_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $1, $4
; MIPS32-NEXT: ori $3, $zero, 0
; MIPS32-NEXT: sltiu $4, $5, 1
; MIPS32-NEXT: clz $1, $1
; MIPS32-NEXT: addiu $1, $1, 32
; MIPS32-NEXT: clz $2, $5
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: movn $2, $1, $4
; MIPS32-NEXT: sltiu $1, $5, 1
; MIPS32-NEXT: clz $2, $4
; MIPS32-NEXT: addiu $2, $2, 32
; MIPS32-NEXT: clz $4, $5
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn $4, $2, $1
; MIPS32-NEXT: move $2, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:

70
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctpop.ll
View File

@ -8,15 +8,15 @@ define i32 @ctpop_i32(i32 %a) {
; MIPS32-NEXT: lui $2, 21845
; MIPS32-NEXT: ori $2, $2, 21845
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: subu $2, $4, $1
; MIPS32-NEXT: srl $1, $2, 2
; MIPS32-NEXT: subu $1, $4, $1
; MIPS32-NEXT: srl $2, $1, 2
; MIPS32-NEXT: lui $3, 13107
; MIPS32-NEXT: ori $3, $3, 13107
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: addu $2, $1, $2
; MIPS32-NEXT: srl $1, $2, 4
; MIPS32-NEXT: addu $1, $1, $2
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: addu $1, $2, $1
; MIPS32-NEXT: srl $2, $1, 4
; MIPS32-NEXT: addu $1, $2, $1
; MIPS32-NEXT: lui $2, 3855
; MIPS32-NEXT: ori $2, $2, 3855
; MIPS32-NEXT: and $1, $1, $2
@ -38,37 +38,37 @@ define i64 @ctpop_i64(i64 %a) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: srl $1, $4, 1
; MIPS32-NEXT: lui $2, 21845
; MIPS32-NEXT: ori $7, $2, 21845
; MIPS32-NEXT: and $1, $1, $7
; MIPS32-NEXT: subu $2, $4, $1
; MIPS32-NEXT: srl $1, $2, 2
; MIPS32-NEXT: lui $3, 13107
; MIPS32-NEXT: ori $6, $3, 13107
; MIPS32-NEXT: and $1, $1, $6
; MIPS32-NEXT: and $2, $2, $6
; MIPS32-NEXT: addu $2, $1, $2
; MIPS32-NEXT: srl $1, $2, 4
; MIPS32-NEXT: addu $1, $1, $2
; MIPS32-NEXT: lui $2, 3855
; MIPS32-NEXT: ori $4, $2, 3855
; MIPS32-NEXT: ori $2, $2, 21845
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: subu $1, $4, $1
; MIPS32-NEXT: srl $3, $1, 2
; MIPS32-NEXT: lui $4, 13107
; MIPS32-NEXT: ori $4, $4, 13107
; MIPS32-NEXT: and $3, $3, $4
; MIPS32-NEXT: and $1, $1, $4
; MIPS32-NEXT: lui $2, 257
; MIPS32-NEXT: ori $3, $2, 257
; MIPS32-NEXT: mul $1, $1, $3
; MIPS32-NEXT: srl $2, $1, 24
; MIPS32-NEXT: srl $1, $5, 1
; MIPS32-NEXT: and $1, $1, $7
; MIPS32-NEXT: subu $5, $5, $1
; MIPS32-NEXT: srl $1, $5, 2
; MIPS32-NEXT: and $1, $1, $6
; MIPS32-NEXT: and $5, $5, $6
; MIPS32-NEXT: addu $5, $1, $5
; MIPS32-NEXT: srl $1, $5, 4
; MIPS32-NEXT: addu $1, $1, $5
; MIPS32-NEXT: and $1, $1, $4
; MIPS32-NEXT: mul $1, $1, $3
; MIPS32-NEXT: addu $1, $3, $1
; MIPS32-NEXT: srl $3, $1, 4
; MIPS32-NEXT: addu $1, $3, $1
; MIPS32-NEXT: lui $3, 3855
; MIPS32-NEXT: ori $3, $3, 3855
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: lui $6, 257
; MIPS32-NEXT: ori $6, $6, 257
; MIPS32-NEXT: mul $1, $1, $6
; MIPS32-NEXT: srl $1, $1, 24
; MIPS32-NEXT: addu $2, $1, $2
; MIPS32-NEXT: srl $7, $5, 1
; MIPS32-NEXT: and $2, $7, $2
; MIPS32-NEXT: subu $2, $5, $2
; MIPS32-NEXT: srl $5, $2, 2
; MIPS32-NEXT: and $5, $5, $4
; MIPS32-NEXT: and $2, $2, $4
; MIPS32-NEXT: addu $2, $5, $2
; MIPS32-NEXT: srl $4, $2, 4
; MIPS32-NEXT: addu $2, $4, $2
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: mul $2, $2, $6
; MIPS32-NEXT: srl $2, $2, 24
; MIPS32-NEXT: addu $2, $2, $1
; MIPS32-NEXT: ori $3, $zero, 0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop

86
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll
View File

@ -6,10 +6,10 @@ define i32 @cttz_i32(i32 %a) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: not $1, $4
; MIPS32-NEXT: addiu $2, $4, -1
; MIPS32-NEXT: and $2, $1, $2
; MIPS32-NEXT: ori $1, $zero, 32
; MIPS32-NEXT: clz $2, $2
; MIPS32-NEXT: subu $2, $1, $2
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: ori $2, $zero, 32
; MIPS32-NEXT: clz $1, $1
; MIPS32-NEXT: subu $2, $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -21,23 +21,23 @@ declare i32 @llvm.cttz.i32(i32, i1 immarg)
define i64 @cttz_i64(i64 %a) {
; MIPS32-LABEL: cttz_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $6, $4
; MIPS32-NEXT: ori $3, $zero, 0
; MIPS32-NEXT: sltiu $4, $6, 1
; MIPS32-NEXT: not $1, $5
; MIPS32-NEXT: addiu $2, $5, -1
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: ori $2, $zero, 32
; MIPS32-NEXT: clz $1, $1
; MIPS32-NEXT: subu $1, $2, $1
; MIPS32-NEXT: addiu $1, $1, 32
; MIPS32-NEXT: not $5, $6
; MIPS32-NEXT: addiu $6, $6, -1
; MIPS32-NEXT: and $5, $5, $6
; MIPS32-NEXT: clz $5, $5
; MIPS32-NEXT: subu $2, $2, $5
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: movn $2, $1, $4
; MIPS32-NEXT: sltiu $1, $4, 1
; MIPS32-NEXT: not $2, $5
; MIPS32-NEXT: addiu $5, $5, -1
; MIPS32-NEXT: and $2, $2, $5
; MIPS32-NEXT: ori $5, $zero, 32
; MIPS32-NEXT: clz $2, $2
; MIPS32-NEXT: subu $2, $5, $2
; MIPS32-NEXT: addiu $2, $2, 32
; MIPS32-NEXT: not $6, $4
; MIPS32-NEXT: addiu $4, $4, -1
; MIPS32-NEXT: and $4, $6, $4
; MIPS32-NEXT: clz $4, $4
; MIPS32-NEXT: subu $4, $5, $4
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn $4, $2, $1
; MIPS32-NEXT: move $2, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -53,10 +53,10 @@ define i32 @ffs_i32_expansion(i32 %a) {
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: not $2, $4
; MIPS32-NEXT: addiu $3, $4, -1
; MIPS32-NEXT: and $3, $2, $3
; MIPS32-NEXT: ori $2, $zero, 32
; MIPS32-NEXT: clz $3, $3
; MIPS32-NEXT: subu $2, $2, $3
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: ori $3, $zero, 32
; MIPS32-NEXT: clz $2, $2
; MIPS32-NEXT: subu $2, $3, $2
; MIPS32-NEXT: addiu $2, $2, 1
; MIPS32-NEXT: sltiu $3, $4, 1
; MIPS32-NEXT: andi $3, $3, 1
@ -74,35 +74,37 @@ entry:
define i64 @ffs_i64_expansion(i64 %a) {
; MIPS32-LABEL: ffs_i64_expansion:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $3, $zero, 1
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: sltiu $7, $4, 1
; MIPS32-NEXT: not $2, $5
; MIPS32-NEXT: addiu $6, $5, -1
; MIPS32-NEXT: and $6, $2, $6
; MIPS32-NEXT: ori $2, $zero, 32
; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: sltiu $3, $4, 1
; MIPS32-NEXT: not $6, $5
; MIPS32-NEXT: addiu $7, $5, -1
; MIPS32-NEXT: and $6, $6, $7
; MIPS32-NEXT: ori $7, $zero, 32
; MIPS32-NEXT: clz $6, $6
; MIPS32-NEXT: subu $6, $2, $6
; MIPS32-NEXT: subu $6, $7, $6
; MIPS32-NEXT: addiu $6, $6, 32
; MIPS32-NEXT: not $8, $4
; MIPS32-NEXT: addiu $9, $4, -1
; MIPS32-NEXT: and $8, $8, $9
; MIPS32-NEXT: clz $8, $8
; MIPS32-NEXT: subu $2, $2, $8
; MIPS32-NEXT: andi $7, $7, 1
; MIPS32-NEXT: movn $2, $6, $7
; MIPS32-NEXT: addiu $2, $2, 1
; MIPS32-NEXT: sltu $6, $2, $3
; MIPS32-NEXT: addiu $3, $1, 0
; MIPS32-NEXT: andi $6, $6, 1
; MIPS32-NEXT: addu $3, $3, $6
; MIPS32-NEXT: subu $7, $7, $8
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $7, $6, $3
; MIPS32-NEXT: addiu $3, $7, 1
; MIPS32-NEXT: sltu $1, $3, $1
; MIPS32-NEXT: addiu $6, $2, 0
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: addu $1, $6, $1
; MIPS32-NEXT: xori $4, $4, 0
; MIPS32-NEXT: xori $5, $5, 0
; MIPS32-NEXT: or $4, $4, $5
; MIPS32-NEXT: sltiu $4, $4, 1
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: movn $2, $1, $4
; MIPS32-NEXT: movn $3, $1, $4
; MIPS32-NEXT: movn $3, $2, $4
; MIPS32-NEXT: movn $1, $2, $4
; MIPS32-NEXT: move $2, $3
; MIPS32-NEXT: move $3, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:

43
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/dyn_stackalloc.ll
View File

@ -15,32 +15,35 @@ define void @Print_c_N_times(i8 %c, i32 %N) {
; MIPS32-NEXT: .cfi_offset 30, -8
; MIPS32-NEXT: move $fp, $sp
; MIPS32-NEXT: .cfi_def_cfa_register 30
; MIPS32-NEXT: sw $4, 8($fp) # 4-byte Folded Spill
; MIPS32-NEXT: move $6, $5
; MIPS32-NEXT: lw $5, 8($fp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $6, 12($fp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 1
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: sw $1, 16($fp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $6, 1
; MIPS32-NEXT: mul $1, $1, $2
; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: addiu $3, $5, 1
; MIPS32-NEXT: mul $1, $3, $1
; MIPS32-NEXT: addiu $1, $1, 7
; MIPS32-NEXT: addiu $2, $zero, 65528
; MIPS32-NEXT: and $2, $1, $2
; MIPS32-NEXT: move $1, $sp
; MIPS32-NEXT: subu $4, $1, $2
; MIPS32-NEXT: sw $4, 20($fp) # 4-byte Folded Spill
; MIPS32-NEXT: move $sp, $4
; MIPS32-NEXT: addiu $3, $zero, 65528
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: move $3, $sp
; MIPS32-NEXT: subu $1, $3, $1
; MIPS32-NEXT: move $sp, $1
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: sw $4, 20($fp) # 4-byte Folded Spill
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: lw $3, 20($fp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $5, 16($fp) # 4-byte Folded Spill
; MIPS32-NEXT: move $5, $3
; MIPS32-NEXT: lw $6, 16($fp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $2, 12($fp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $1, 8($fp) # 4-byte Folded Spill
; MIPS32-NEXT: jal memset
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $5, 12($fp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 16($fp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $4, 20($fp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 16
; MIPS32-NEXT: addu $2, $4, $5
; MIPS32-NEXT: sb $1, 0($2)
; MIPS32-NEXT: lw $1, 8($fp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 16($fp) # 4-byte Folded Reload
; MIPS32-NEXT: addu $3, $1, $2
; MIPS32-NEXT: lw $4, 12($fp) # 4-byte Folded Reload
; MIPS32-NEXT: sb $4, 0($3)
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: jal puts
; MIPS32-NEXT: nop
; MIPS32-NEXT: addiu $sp, $sp, 16

140
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll
View File

@ -27,9 +27,10 @@ entry:
define i1 @uno_s(float %x, float %y) {
; MIPS32-LABEL: uno_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.un.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -39,9 +40,10 @@ entry:
define i1 @ord_s(float %x, float %y) {
; MIPS32-LABEL: ord_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.un.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -53,9 +55,10 @@ entry:
define i1 @oeq_s(float %x, float %y) {
; MIPS32-LABEL: oeq_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.eq.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -65,9 +68,10 @@ entry:
define i1 @une_s(float %x, float %y) {
; MIPS32-LABEL: une_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.eq.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -79,9 +83,10 @@ entry:
define i1 @ueq_s(float %x, float %y) {
; MIPS32-LABEL: ueq_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ueq.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -91,9 +96,10 @@ entry:
define i1 @one_s(float %x, float %y) {
; MIPS32-LABEL: one_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ueq.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -105,9 +111,10 @@ entry:
define i1 @olt_s(float %x, float %y) {
; MIPS32-LABEL: olt_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.olt.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -117,9 +124,10 @@ entry:
define i1 @uge_s(float %x, float %y) {
; MIPS32-LABEL: uge_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.olt.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -131,9 +139,10 @@ entry:
define i1 @ult_s(float %x, float %y) {
; MIPS32-LABEL: ult_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -143,9 +152,10 @@ entry:
define i1 @oge_s(float %x, float %y) {
; MIPS32-LABEL: oge_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -157,9 +167,10 @@ entry:
define i1 @ole_s(float %x, float %y) {
; MIPS32-LABEL: ole_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ole.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -169,9 +180,10 @@ entry:
define i1 @ugt_s(float %x, float %y) {
; MIPS32-LABEL: ugt_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ole.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -183,9 +195,10 @@ entry:
define i1 @ule_s(float %x, float %y) {
; MIPS32-LABEL: ule_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ule.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -195,9 +208,10 @@ entry:
define i1 @ogt_s(float %x, float %y) {
; MIPS32-LABEL: ogt_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ule.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -231,9 +245,10 @@ entry:
define i1 @uno_d(double %x, double %y) {
; MIPS32-LABEL: uno_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.un.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -243,9 +258,10 @@ entry:
define i1 @ord_d(double %x, double %y) {
; MIPS32-LABEL: ord_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.un.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -257,9 +273,10 @@ entry:
define i1 @oeq_d(double %x, double %y) {
; MIPS32-LABEL: oeq_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.eq.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -269,9 +286,10 @@ entry:
define i1 @une_d(double %x, double %y) {
; MIPS32-LABEL: une_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.eq.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -283,9 +301,10 @@ entry:
define i1 @ueq_d(double %x, double %y) {
; MIPS32-LABEL: ueq_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ueq.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -295,9 +314,10 @@ entry:
define i1 @one_d(double %x, double %y) {
; MIPS32-LABEL: one_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ueq.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -309,9 +329,10 @@ entry:
define i1 @olt_d(double %x, double %y) {
; MIPS32-LABEL: olt_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.olt.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -321,9 +342,10 @@ entry:
define i1 @uge_d(double %x, double %y) {
; MIPS32-LABEL: uge_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.olt.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -335,9 +357,10 @@ entry:
define i1 @ult_d(double %x, double %y) {
; MIPS32-LABEL: ult_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ult.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -347,9 +370,10 @@ entry:
define i1 @oge_d(double %x, double %y) {
; MIPS32-LABEL: oge_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ult.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -361,9 +385,10 @@ entry:
define i1 @ole_d(double %x, double %y) {
; MIPS32-LABEL: ole_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ole.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -373,9 +398,10 @@ entry:
define i1 @ugt_d(double %x, double %y) {
; MIPS32-LABEL: ugt_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ole.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -387,9 +413,10 @@ entry:
define i1 @ule_d(double %x, double %y) {
; MIPS32-LABEL: ule_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ule.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -399,9 +426,10 @@ entry:
define i1 @ogt_d(double %x, double %y) {
; MIPS32-LABEL: ogt_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ule.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:

20
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_constants.ll
View File

@ -18,22 +18,22 @@ define double @e_double_precision() {
; FP32-LABEL: e_double_precision:
; FP32: # %bb.0: # %entry
; FP32-NEXT: lui $1, 16389
; FP32-NEXT: ori $2, $1, 48906
; FP32-NEXT: lui $1, 35604
; FP32-NEXT: ori $1, $1, 22377
; FP32-NEXT: mtc1 $1, $f0
; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: ori $1, $1, 48906
; FP32-NEXT: lui $2, 35604
; FP32-NEXT: ori $2, $2, 22377
; FP32-NEXT: mtc1 $2, $f0
; FP32-NEXT: mtc1 $1, $f1
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
;
; FP64-LABEL: e_double_precision:
; FP64: # %bb.0: # %entry
; FP64-NEXT: lui $1, 16389
; FP64-NEXT: ori $2, $1, 48906
; FP64-NEXT: lui $1, 35604
; FP64-NEXT: ori $1, $1, 22377
; FP64-NEXT: mtc1 $1, $f0
; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: ori $1, $1, 48906
; FP64-NEXT: lui $2, 35604
; FP64-NEXT: ori $2, $2, 22377
; FP64-NEXT: mtc1 $2, $f0
; FP64-NEXT: mthc1 $1, $f0
; FP64-NEXT: jr $ra
; FP64-NEXT: nop
entry:

116
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll
View File

@ -164,20 +164,20 @@ define zeroext i16 @f32tou16(float %a) {
; MIPS32-LABEL: f32tou16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.s $f0, $f12
; MIPS32-NEXT: mfc1 $2, $f0
; MIPS32-NEXT: lui $1, 20224
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: mfc1 $1, $f0
; MIPS32-NEXT: lui $2, 20224
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: sub.s $f1, $f12, $f0
; MIPS32-NEXT: trunc.w.s $f1, $f1
; MIPS32-NEXT: mfc1 $1, $f1
; MIPS32-NEXT: mfc1 $2, $f1
; MIPS32-NEXT: lui $3, 32768
; MIPS32-NEXT: xor $1, $1, $3
; MIPS32-NEXT: xor $2, $2, $3
; MIPS32-NEXT: addiu $3, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f0
; MIPS32-NEXT: movf $3, $zero, $fcc0
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $1, $2, $3
; MIPS32-NEXT: andi $2, $1, 65535
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: andi $2, $2, 65535
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -189,20 +189,20 @@ define zeroext i8 @f32tou8(float %a) {
; MIPS32-LABEL: f32tou8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.s $f0, $f12
; MIPS32-NEXT: mfc1 $2, $f0
; MIPS32-NEXT: lui $1, 20224
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: mfc1 $1, $f0
; MIPS32-NEXT: lui $2, 20224
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: sub.s $f1, $f12, $f0
; MIPS32-NEXT: trunc.w.s $f1, $f1
; MIPS32-NEXT: mfc1 $1, $f1
; MIPS32-NEXT: mfc1 $2, $f1
; MIPS32-NEXT: lui $3, 32768
; MIPS32-NEXT: xor $1, $1, $3
; MIPS32-NEXT: xor $2, $2, $3
; MIPS32-NEXT: addiu $3, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f0
; MIPS32-NEXT: movf $3, $zero, $fcc0
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $1, $2, $3
; MIPS32-NEXT: andi $2, $1, 255
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: andi $2, $2, 255
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -233,10 +233,10 @@ define i32 @f64tou32(double %a) {
; FP32: # %bb.0: # %entry
; FP32-NEXT: trunc.w.d $f0, $f12
; FP32-NEXT: mfc1 $1, $f0
; FP32-NEXT: lui $3, 16864
; FP32-NEXT: ori $2, $zero, 0
; FP32-NEXT: mtc1 $2, $f0
; FP32-NEXT: mtc1 $3, $f1
; FP32-NEXT: lui $2, 16864
; FP32-NEXT: ori $3, $zero, 0
; FP32-NEXT: mtc1 $3, $f0
; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: sub.d $f2, $f12, $f0
; FP32-NEXT: trunc.w.d $f2, $f2
; FP32-NEXT: mfc1 $2, $f2
@ -254,10 +254,10 @@ define i32 @f64tou32(double %a) {
; FP64: # %bb.0: # %entry
; FP64-NEXT: trunc.w.d $f0, $f12
; FP64-NEXT: mfc1 $1, $f0
; FP64-NEXT: lui $3, 16864
; FP64-NEXT: ori $2, $zero, 0
; FP64-NEXT: mtc1 $2, $f0
; FP64-NEXT: mthc1 $3, $f0
; FP64-NEXT: lui $2, 16864
; FP64-NEXT: ori $3, $zero, 0
; FP64-NEXT: mtc1 $3, $f0
; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: sub.d $f1, $f12, $f0
; FP64-NEXT: trunc.w.d $f1, $f1
; FP64-NEXT: mfc1 $2, $f1
@ -279,44 +279,44 @@ define zeroext i16 @f64tou16(double %a) {
; FP32-LABEL: f64tou16:
; FP32: # %bb.0: # %entry
; FP32-NEXT: trunc.w.d $f0, $f12
; FP32-NEXT: mfc1 $2, $f0
; FP32-NEXT: lui $3, 16864
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f0
; FP32-NEXT: mtc1 $3, $f1
; FP32-NEXT: mfc1 $1, $f0
; FP32-NEXT: lui $2, 16864
; FP32-NEXT: ori $3, $zero, 0
; FP32-NEXT: mtc1 $3, $f0
; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: sub.d $f2, $f12, $f0
; FP32-NEXT: trunc.w.d $f2, $f2
; FP32-NEXT: mfc1 $1, $f2
; FP32-NEXT: mfc1 $2, $f2
; FP32-NEXT: lui $3, 32768
; FP32-NEXT: xor $1, $1, $3
; FP32-NEXT: xor $2, $2, $3
; FP32-NEXT: addiu $3, $zero, 1
; FP32-NEXT: c.ult.d $f12, $f0
; FP32-NEXT: movf $3, $zero, $fcc0
; FP32-NEXT: andi $3, $3, 1
; FP32-NEXT: movn $1, $2, $3
; FP32-NEXT: andi $2, $1, 65535
; FP32-NEXT: movn $2, $1, $3
; FP32-NEXT: andi $2, $2, 65535
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
;
; FP64-LABEL: f64tou16:
; FP64: # %bb.0: # %entry
; FP64-NEXT: trunc.w.d $f0, $f12
; FP64-NEXT: mfc1 $2, $f0
; FP64-NEXT: lui $3, 16864
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f0
; FP64-NEXT: mthc1 $3, $f0
; FP64-NEXT: mfc1 $1, $f0
; FP64-NEXT: lui $2, 16864
; FP64-NEXT: ori $3, $zero, 0
; FP64-NEXT: mtc1 $3, $f0
; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: sub.d $f1, $f12, $f0
; FP64-NEXT: trunc.w.d $f1, $f1
; FP64-NEXT: mfc1 $1, $f1
; FP64-NEXT: mfc1 $2, $f1
; FP64-NEXT: lui $3, 32768
; FP64-NEXT: xor $1, $1, $3
; FP64-NEXT: xor $2, $2, $3
; FP64-NEXT: addiu $3, $zero, 1
; FP64-NEXT: c.ult.d $f12, $f0
; FP64-NEXT: movf $3, $zero, $fcc0
; FP64-NEXT: andi $3, $3, 1
; FP64-NEXT: movn $1, $2, $3
; FP64-NEXT: andi $2, $1, 65535
; FP64-NEXT: movn $2, $1, $3
; FP64-NEXT: andi $2, $2, 65535
; FP64-NEXT: jr $ra
; FP64-NEXT: nop
entry:
@ -328,44 +328,44 @@ define zeroext i8 @f64tou8(double %a) {
; FP32-LABEL: f64tou8:
; FP32: # %bb.0: # %entry
; FP32-NEXT: trunc.w.d $f0, $f12
; FP32-NEXT: mfc1 $2, $f0
; FP32-NEXT: lui $3, 16864
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f0
; FP32-NEXT: mtc1 $3, $f1
; FP32-NEXT: mfc1 $1, $f0
; FP32-NEXT: lui $2, 16864
; FP32-NEXT: ori $3, $zero, 0
; FP32-NEXT: mtc1 $3, $f0
; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: sub.d $f2, $f12, $f0
; FP32-NEXT: trunc.w.d $f2, $f2
; FP32-NEXT: mfc1 $1, $f2
; FP32-NEXT: mfc1 $2, $f2
; FP32-NEXT: lui $3, 32768
; FP32-NEXT: xor $1, $1, $3
; FP32-NEXT: xor $2, $2, $3
; FP32-NEXT: addiu $3, $zero, 1
; FP32-NEXT: c.ult.d $f12, $f0
; FP32-NEXT: movf $3, $zero, $fcc0
; FP32-NEXT: andi $3, $3, 1
; FP32-NEXT: movn $1, $2, $3
; FP32-NEXT: andi $2, $1, 255
; FP32-NEXT: movn $2, $1, $3
; FP32-NEXT: andi $2, $2, 255
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
;
; FP64-LABEL: f64tou8:
; FP64: # %bb.0: # %entry
; FP64-NEXT: trunc.w.d $f0, $f12
; FP64-NEXT: mfc1 $2, $f0
; FP64-NEXT: lui $3, 16864
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f0
; FP64-NEXT: mthc1 $3, $f0
; FP64-NEXT: mfc1 $1, $f0
; FP64-NEXT: lui $2, 16864
; FP64-NEXT: ori $3, $zero, 0
; FP64-NEXT: mtc1 $3, $f0
; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: sub.d $f1, $f12, $f0
; FP64-NEXT: trunc.w.d $f1, $f1
; FP64-NEXT: mfc1 $1, $f1
; FP64-NEXT: mfc1 $2, $f1
; FP64-NEXT: lui $3, 32768
; FP64-NEXT: xor $1, $1, $3
; FP64-NEXT: xor $2, $2, $3
; FP64-NEXT: addiu $3, $zero, 1
; FP64-NEXT: c.ult.d $f12, $f0
; FP64-NEXT: movf $3, $zero, $fcc0
; FP64-NEXT: andi $3, $3, 1
; FP64-NEXT: movn $1, $2, $3
; FP64-NEXT: andi $2, $1, 255
; FP64-NEXT: movn $2, $1, $3
; FP64-NEXT: andi $2, $2, 255
; FP64-NEXT: jr $ra
; FP64-NEXT: nop
entry:

7
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll
View File

@ -14,11 +14,12 @@ define i32 @main() {
; MIPS32-NEXT: addiu $4, $1, %lo($.str)
; MIPS32-NEXT: lui $1, 18838
; MIPS32-NEXT: ori $5, $1, 722
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: sw $1, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: jal printf
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra

12
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address_pic.ll
View File

@ -23,8 +23,9 @@ define i32 @call_global(i32 %a, i32 %b) {
; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 24
; MIPS32_PIC-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: .cfi_offset 31, -4
; MIPS32_PIC-NEXT: addu $gp, $2, $25
; MIPS32_PIC-NEXT: lw $25, %call16(f)($gp)
; MIPS32_PIC-NEXT: addu $1, $2, $25
; MIPS32_PIC-NEXT: lw $25, %call16(f)($1)
; MIPS32_PIC-NEXT: move $gp, $1
; MIPS32_PIC-NEXT: jalr $25
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
@ -45,9 +46,10 @@ define i32 @call_global_with_local_linkage(i32 %a, i32 %b) {
; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 24
; MIPS32_PIC-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: .cfi_offset 31, -4
; MIPS32_PIC-NEXT: addu $gp, $2, $25
; MIPS32_PIC-NEXT: lw $1, %got(f_with_local_linkage)($gp)
; MIPS32_PIC-NEXT: addiu $25, $1, %lo(f_with_local_linkage)
; MIPS32_PIC-NEXT: addu $1, $2, $25
; MIPS32_PIC-NEXT: lw $2, %got(f_with_local_linkage)($1)
; MIPS32_PIC-NEXT: addiu $25, $2, %lo(f_with_local_linkage)
; MIPS32_PIC-NEXT: move $gp, $1
; MIPS32_PIC-NEXT: jalr $25
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload

104
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
View File

@ -188,12 +188,13 @@ entry:
define i1 @sgt_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: sgt_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $2, $7, $5
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: slt $1, $7, $5
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $6, $4
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -205,13 +206,14 @@ define i1 @sge_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: sge_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $1, $5, $7
; MIPS32-NEXT: xori $2, $1, 1
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
; MIPS32-NEXT: xori $1, $1, 1
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $4, $6
; MIPS32-NEXT: xori $3, $3, 1
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -222,12 +224,13 @@ entry:
define i1 @slt_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: slt_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $2, $5, $7
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: slt $1, $5, $7
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $4, $6
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -239,13 +242,14 @@ define i1 @sle_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: sle_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $1, $7, $5
; MIPS32-NEXT: xori $2, $1, 1
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
; MIPS32-NEXT: xori $1, $1, 1
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $6, $4
; MIPS32-NEXT: xori $3, $3, 1
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -256,12 +260,13 @@ entry:
define i1 @ugt_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: ugt_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $2, $7, $5
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: sltu $1, $7, $5
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $6, $4
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -273,13 +278,14 @@ define i1 @uge_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: uge_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $1, $5, $7
; MIPS32-NEXT: xori $2, $1, 1
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
; MIPS32-NEXT: xori $1, $1, 1
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $4, $6
; MIPS32-NEXT: xori $3, $3, 1
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -290,12 +296,13 @@ entry:
define i1 @ult_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: ult_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $2, $5, $7
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: sltu $1, $5, $7
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $4, $6
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -307,13 +314,14 @@ define i1 @ule_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: ule_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $1, $7, $5
; MIPS32-NEXT: xori $2, $1, 1
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
; MIPS32-NEXT: xori $1, $1, 1
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $6, $4
; MIPS32-NEXT: xori $3, $3, 1
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:

238
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
View File

@ -7,35 +7,35 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -32
; MIPS32-NEXT: .cfi_def_cfa_offset 32
; MIPS32-NEXT: sw $4, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $1, $zero, 7
; MIPS32-NEXT: ori $2, $zero, 3
; MIPS32-NEXT: sw $2, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 2
; MIPS32-NEXT: sw $2, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 1
; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: sw $2, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $2, $zero, 65535
; MIPS32-NEXT: sw $2, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: subu $2, $4, $2
; MIPS32-NEXT: sw $2, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sltu $1, $1, $2
; MIPS32-NEXT: ori $3, $zero, 2
; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: ori $6, $zero, 0
; MIPS32-NEXT: addiu $7, $zero, 65535
; MIPS32-NEXT: ori $8, $zero, 0
; MIPS32-NEXT: subu $8, $4, $8
; MIPS32-NEXT: sltu $1, $1, $8
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: sw $4, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $8, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB0_6
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_1: # %entry
; MIPS32-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lui $1, %hi($JTI0_0)
; MIPS32-NEXT: sll $2, $2, 2
; MIPS32-NEXT: addu $1, $1, $2
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sll $3, $2, 2
; MIPS32-NEXT: addu $1, $1, $3
; MIPS32-NEXT: lw $1, %lo($JTI0_0)($1)
; MIPS32-NEXT: jr $1
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_2: # %sw.bb
; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@ -45,37 +45,37 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_4: # %sw.bb2
; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_5: # %sw.bb3
; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_6: # %sw.default
; MIPS32-NEXT: .insn
; MIPS32-NEXT: # %bb.7: # %sw.epilog
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ori $3, $zero, 8
; MIPS32-NEXT: subu $2, $2, $3
; MIPS32-NEXT: sw $2, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sltu $1, $1, $2
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB0_13
; MIPS32-NEXT: ori $1, $zero, 8
; MIPS32-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: subu $1, $2, $1
; MIPS32-NEXT: lw $3, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sltu $4, $3, $1
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $4, $BB0_13
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_8: # %sw.epilog
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lui $1, %hi($JTI0_1)
; MIPS32-NEXT: sll $2, $2, 2
; MIPS32-NEXT: addu $1, $1, $2
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sll $3, $2, 2
; MIPS32-NEXT: addu $1, $1, $3
; MIPS32-NEXT: lw $1, %lo($JTI0_1)($1)
; MIPS32-NEXT: jr $1
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_9: # %sw.bb4
; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@ -85,20 +85,35 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_11: # %sw.bb6
; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_12: # %sw.bb7
; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_13: # %sw.default8
; MIPS32-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_13: # %sw.default8
; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32: $JTI0_0:
; MIPS32-NEXT: .4byte ($BB0_2)
; MIPS32-NEXT: .4byte ($BB0_3)
; MIPS32-NEXT: .4byte ($BB0_4)
; MIPS32-NEXT: .4byte ($BB0_5)
; MIPS32-NEXT: .4byte ($BB0_2)
; MIPS32-NEXT: .4byte ($BB0_3)
; MIPS32-NEXT: .4byte ($BB0_4)
; MIPS32-NEXT: .4byte ($BB0_5)
; MIPS32-NEXT: $JTI0_1:
; MIPS32-NEXT: .4byte ($BB0_9)
; MIPS32-NEXT: .4byte ($BB0_10)
; MIPS32-NEXT: .4byte ($BB0_11)
; MIPS32-NEXT: .4byte ($BB0_12)
;
; MIPS32_PIC-LABEL: mod4_0_to_11:
; MIPS32_PIC: # %bb.0: # %entry
@ -107,104 +122,117 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32_PIC-NEXT: addiu $sp, $sp, -40
; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 40
; MIPS32_PIC-NEXT: addu $1, $2, $25
; MIPS32_PIC-NEXT: sw $1, 8($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $4, 12($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: ori $1, $zero, 7
; MIPS32_PIC-NEXT: ori $2, $zero, 3
; MIPS32_PIC-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: ori $2, $zero, 2
; MIPS32_PIC-NEXT: sw $2, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: ori $2, $zero, 1
; MIPS32_PIC-NEXT: sw $2, 24($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: ori $2, $zero, 0
; MIPS32_PIC-NEXT: sw $2, 28($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: addiu $2, $zero, 65535
; MIPS32_PIC-NEXT: sw $2, 32($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: ori $2, $zero, 0
; MIPS32_PIC-NEXT: subu $2, $4, $2
; MIPS32_PIC-NEXT: sw $2, 36($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sltu $1, $1, $2
; MIPS32_PIC-NEXT: andi $1, $1, 1
; MIPS32_PIC-NEXT: bnez $1, $BB0_6
; MIPS32_PIC-NEXT: ori $2, $zero, 7
; MIPS32_PIC-NEXT: ori $3, $zero, 3
; MIPS32_PIC-NEXT: ori $5, $zero, 2
; MIPS32_PIC-NEXT: ori $6, $zero, 1
; MIPS32_PIC-NEXT: ori $7, $zero, 0
; MIPS32_PIC-NEXT: addiu $8, $zero, 65535
; MIPS32_PIC-NEXT: ori $9, $zero, 0
; MIPS32_PIC-NEXT: subu $9, $4, $9
; MIPS32_PIC-NEXT: sltu $2, $2, $9
; MIPS32_PIC-NEXT: andi $2, $2, 1
; MIPS32_PIC-NEXT: sw $1, 36($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $4, 32($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $3, 28($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $5, 24($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $6, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $7, 16($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $8, 12($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $9, 8($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: bnez $2, $BB0_6
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_1: # %entry
; MIPS32_PIC-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $3, 36($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $1, %got($JTI0_0)($2)
; MIPS32_PIC-NEXT: sll $3, $3, 2
; MIPS32_PIC-NEXT: addu $1, $1, $3
; MIPS32_PIC-NEXT: lw $1, %lo($JTI0_0)($1)
; MIPS32_PIC-NEXT: addu $1, $1, $2
; MIPS32_PIC-NEXT: jr $1
; MIPS32_PIC-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, %got($JTI0_0)($1)
; MIPS32_PIC-NEXT: lw $3, 8($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: sll $4, $3, 2
; MIPS32_PIC-NEXT: addu $2, $2, $4
; MIPS32_PIC-NEXT: lw $2, %lo($JTI0_0)($2)
; MIPS32_PIC-NEXT: addu $2, $2, $1
; MIPS32_PIC-NEXT: jr $2
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_2: # %sw.bb
; MIPS32_PIC-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_3: # %sw.bb1
; MIPS32_PIC-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_4: # %sw.bb2
; MIPS32_PIC-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_4: # %sw.bb2
; MIPS32_PIC-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_5: # %sw.bb3
; MIPS32_PIC-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_6: # %sw.default
; MIPS32_PIC-NEXT: .insn
; MIPS32_PIC-NEXT: # %bb.7: # %sw.epilog
; MIPS32_PIC-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: ori $3, $zero, 8
; MIPS32_PIC-NEXT: subu $2, $2, $3
; MIPS32_PIC-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sltu $1, $1, $2
; MIPS32_PIC-NEXT: andi $1, $1, 1
; MIPS32_PIC-NEXT: bnez $1, $BB0_13
; MIPS32_PIC-NEXT: ori $1, $zero, 8
; MIPS32_PIC-NEXT: lw $2, 32($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: subu $1, $2, $1
; MIPS32_PIC-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: sltu $4, $3, $1
; MIPS32_PIC-NEXT: andi $4, $4, 1
; MIPS32_PIC-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: bnez $4, $BB0_13
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_8: # %sw.epilog
; MIPS32_PIC-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, %got($JTI0_1)($1)
; MIPS32_PIC-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $1, %got($JTI0_1)($2)
; MIPS32_PIC-NEXT: sll $3, $3, 2
; MIPS32_PIC-NEXT: addu $1, $1, $3
; MIPS32_PIC-NEXT: lw $1, %lo($JTI0_1)($1)
; MIPS32_PIC-NEXT: addu $1, $1, $2
; MIPS32_PIC-NEXT: jr $1
; MIPS32_PIC-NEXT: sll $4, $3, 2
; MIPS32_PIC-NEXT: addu $2, $2, $4
; MIPS32_PIC-NEXT: lw $2, %lo($JTI0_1)($2)
; MIPS32_PIC-NEXT: addu $2, $2, $1
; MIPS32_PIC-NEXT: jr $2
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_9: # %sw.bb4
; MIPS32_PIC-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_10: # %sw.bb5
; MIPS32_PIC-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_11: # %sw.bb6
; MIPS32_PIC-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_12: # %sw.bb7
; MIPS32_PIC-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_13: # %sw.default8
; MIPS32_PIC-NEXT: lw $2, 32($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: $BB0_10: # %sw.bb5
; MIPS32_PIC-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_11: # %sw.bb6
; MIPS32_PIC-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_12: # %sw.bb7
; MIPS32_PIC-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_13: # %sw.default8
; MIPS32_PIC-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC: $JTI0_0:
; MIPS32_PIC-NEXT: .gpword ($BB0_2)
; MIPS32_PIC-NEXT: .gpword ($BB0_3)
; MIPS32_PIC-NEXT: .gpword ($BB0_4)
; MIPS32_PIC-NEXT: .gpword ($BB0_5)
; MIPS32_PIC-NEXT: .gpword ($BB0_2)
; MIPS32_PIC-NEXT: .gpword ($BB0_3)
; MIPS32_PIC-NEXT: .gpword ($BB0_4)
; MIPS32_PIC-NEXT: .gpword ($BB0_5)
; MIPS32_PIC-NEXT: $JTI0_1:
; MIPS32_PIC-NEXT: .gpword ($BB0_9)
; MIPS32_PIC-NEXT: .gpword ($BB0_10)
; MIPS32_PIC-NEXT: .gpword ($BB0_11)
; MIPS32_PIC-NEXT: .gpword ($BB0_12)
entry:
switch i32 %a, label %sw.default [

20
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
View File

@ -15,11 +15,11 @@ define float @load_float_align1() {
; MIPS32-LABEL: load_float_align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align1)
; MIPS32-NEXT: addiu $2, $1, %lo(float_align1)
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 3($2)
; MIPS32-NEXT: lwr $1, 0($2)
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: addiu $1, $1, %lo(float_align1)
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
@ -38,11 +38,11 @@ define float @load_float_align2() {
; MIPS32-LABEL: load_float_align2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align2)
; MIPS32-NEXT: addiu $2, $1, %lo(float_align2)
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 3($2)
; MIPS32-NEXT: lwr $1, 0($2)
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: addiu $1, $1, %lo(float_align2)
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;

336
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_split_because_of_memsize_or_align.ll
View File

@ -131,23 +131,25 @@ entry:
define i64 @load5align1(%struct.MemSize5_Align1* %S) {
; MIPS32-LABEL: load5align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
; MIPS32-NEXT: lbu $1, 4($4)
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 3($4)
; MIPS32-NEXT: lwr $1, 0($4)
; MIPS32-NEXT: lbu $2, 4($4)
; MIPS32-NEXT: addiu $3, $zero, 65535
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: andi $3, $1, 255
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: andi $3, $2, 255
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load5align1:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lw $2, 0($4)
; MIPS32R6-NEXT: lbu $1, 4($4)
; MIPS32R6-NEXT: lw $1, 0($4)
; MIPS32R6-NEXT: lbu $2, 4($4)
; MIPS32R6-NEXT: addiu $3, $zero, 65535
; MIPS32R6-NEXT: and $2, $2, $3
; MIPS32R6-NEXT: andi $3, $1, 255
; MIPS32R6-NEXT: and $1, $1, $3
; MIPS32R6-NEXT: andi $3, $2, 255
; MIPS32R6-NEXT: move $2, $1
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize5_Align1* %S to i40*
@ -159,23 +161,25 @@ entry:
define i64 @load5align2(%struct.MemSize5_Align2* %S) {
; MIPS32-LABEL: load5align2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
; MIPS32-NEXT: lbu $1, 4($4)
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 3($4)
; MIPS32-NEXT: lwr $1, 0($4)
; MIPS32-NEXT: lbu $2, 4($4)
; MIPS32-NEXT: addiu $3, $zero, 65535
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: andi $3, $1, 255
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: andi $3, $2, 255
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load5align2:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lw $2, 0($4)
; MIPS32R6-NEXT: lbu $1, 4($4)
; MIPS32R6-NEXT: lw $1, 0($4)
; MIPS32R6-NEXT: lbu $2, 4($4)
; MIPS32R6-NEXT: addiu $3, $zero, 65535
; MIPS32R6-NEXT: and $2, $2, $3
; MIPS32R6-NEXT: andi $3, $1, 255
; MIPS32R6-NEXT: and $1, $1, $3
; MIPS32R6-NEXT: andi $3, $2, 255
; MIPS32R6-NEXT: move $2, $1
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize5_Align2* %S to i40*
@ -187,21 +191,23 @@ entry:
define i64 @load5align4(%struct.MemSize5_Align4* %S) {
; MIPS32-LABEL: load5align4:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lw $2, 0($4)
; MIPS32-NEXT: lbu $1, 4($4)
; MIPS32-NEXT: lw $1, 0($4)
; MIPS32-NEXT: lbu $2, 4($4)
; MIPS32-NEXT: addiu $3, $zero, 65535
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: andi $3, $1, 255
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: andi $3, $2, 255
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load5align4:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lw $2, 0($4)
; MIPS32R6-NEXT: lbu $1, 4($4)
; MIPS32R6-NEXT: lw $1, 0($4)
; MIPS32R6-NEXT: lbu $2, 4($4)
; MIPS32R6-NEXT: addiu $3, $zero, 65535
; MIPS32R6-NEXT: and $2, $2, $3
; MIPS32R6-NEXT: andi $3, $1, 255
; MIPS32R6-NEXT: and $1, $1, $3
; MIPS32R6-NEXT: andi $3, $2, 255
; MIPS32R6-NEXT: move $2, $1
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize5_Align4* %S to i40*
@ -213,21 +219,23 @@ entry:
define i64 @load5align8(%struct.MemSize5_Align8* %S) {
; MIPS32-LABEL: load5align8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lw $2, 0($4)
; MIPS32-NEXT: lbu $1, 4($4)
; MIPS32-NEXT: lw $1, 0($4)
; MIPS32-NEXT: lbu $2, 4($4)
; MIPS32-NEXT: addiu $3, $zero, 65535
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: andi $3, $1, 255
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: andi $3, $2, 255
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load5align8:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lw $2, 0($4)
; MIPS32R6-NEXT: lbu $1, 4($4)
; MIPS32R6-NEXT: lw $1, 0($4)
; MIPS32R6-NEXT: lbu $2, 4($4)
; MIPS32R6-NEXT: addiu $3, $zero, 65535
; MIPS32R6-NEXT: and $2, $2, $3
; MIPS32R6-NEXT: andi $3, $1, 255
; MIPS32R6-NEXT: and $1, $1, $3
; MIPS32R6-NEXT: andi $3, $2, 255
; MIPS32R6-NEXT: move $2, $1
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize5_Align8* %S to i40*
@ -239,25 +247,27 @@ entry:
define i64 @load6align1(%struct.MemSize6_Align1* %S) {
; MIPS32-LABEL: load6align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 7($4)
; MIPS32-NEXT: lwr $1, 4($4)
; MIPS32-NEXT: lwl $1, 3($4)
; MIPS32-NEXT: lwr $1, 0($4)
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 7($4)
; MIPS32-NEXT: lwr $2, 4($4)
; MIPS32-NEXT: addiu $3, $zero, 65535
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: andi $3, $1, 65535
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: andi $3, $2, 65535
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load6align1:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lw $2, 0($4)
; MIPS32R6-NEXT: lhu $1, 4($4)
; MIPS32R6-NEXT: lw $1, 0($4)
; MIPS32R6-NEXT: lhu $2, 4($4)
; MIPS32R6-NEXT: addiu $3, $zero, 65535
; MIPS32R6-NEXT: and $2, $2, $3
; MIPS32R6-NEXT: andi $3, $1, 65535
; MIPS32R6-NEXT: and $1, $1, $3
; MIPS32R6-NEXT: andi $3, $2, 65535
; MIPS32R6-NEXT: move $2, $1
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize6_Align1* %S to i48*
@ -269,23 +279,25 @@ entry:
define i64 @load6align2(%struct.MemSize6_Align2* %S) {
; MIPS32-LABEL: load6align2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
; MIPS32-NEXT: lhu $1, 4($4)
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 3($4)
; MIPS32-NEXT: lwr $1, 0($4)
; MIPS32-NEXT: lhu $2, 4($4)
; MIPS32-NEXT: addiu $3, $zero, 65535
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: andi $3, $1, 65535
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: andi $3, $2, 65535
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load6align2:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lw $2, 0($4)
; MIPS32R6-NEXT: lhu $1, 4($4)
; MIPS32R6-NEXT: lw $1, 0($4)
; MIPS32R6-NEXT: lhu $2, 4($4)
; MIPS32R6-NEXT: addiu $3, $zero, 65535
; MIPS32R6-NEXT: and $2, $2, $3
; MIPS32R6-NEXT: andi $3, $1, 65535
; MIPS32R6-NEXT: and $1, $1, $3
; MIPS32R6-NEXT: andi $3, $2, 65535
; MIPS32R6-NEXT: move $2, $1
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize6_Align2* %S to i48*
@ -297,21 +309,23 @@ entry:
define i64 @load6align4(%struct.MemSize6_Align4* %S) {
; MIPS32-LABEL: load6align4:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lw $2, 0($4)
; MIPS32-NEXT: lhu $1, 4($4)
; MIPS32-NEXT: lw $1, 0($4)
; MIPS32-NEXT: lhu $2, 4($4)
; MIPS32-NEXT: addiu $3, $zero, 65535
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: andi $3, $1, 65535
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: andi $3, $2, 65535
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load6align4:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lw $2, 0($4)
; MIPS32R6-NEXT: lhu $1, 4($4)
; MIPS32R6-NEXT: lw $1, 0($4)
; MIPS32R6-NEXT: lhu $2, 4($4)
; MIPS32R6-NEXT: addiu $3, $zero, 65535
; MIPS32R6-NEXT: and $2, $2, $3
; MIPS32R6-NEXT: andi $3, $1, 65535
; MIPS32R6-NEXT: and $1, $1, $3
; MIPS32R6-NEXT: andi $3, $2, 65535
; MIPS32R6-NEXT: move $2, $1
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize6_Align4* %S to i48*
@ -323,21 +337,23 @@ entry:
define i64 @load6align8(%struct.MemSize6_Align8* %S) {
; MIPS32-LABEL: load6align8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lw $2, 0($4)
; MIPS32-NEXT: lhu $1, 4($4)
; MIPS32-NEXT: lw $1, 0($4)
; MIPS32-NEXT: lhu $2, 4($4)
; MIPS32-NEXT: addiu $3, $zero, 65535
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: andi $3, $1, 65535
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: andi $3, $2, 65535
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load6align8:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lw $2, 0($4)
; MIPS32R6-NEXT: lhu $1, 4($4)
; MIPS32R6-NEXT: lw $1, 0($4)
; MIPS32R6-NEXT: lhu $2, 4($4)
; MIPS32R6-NEXT: addiu $3, $zero, 65535
; MIPS32R6-NEXT: and $2, $2, $3
; MIPS32R6-NEXT: andi $3, $1, 65535
; MIPS32R6-NEXT: and $1, $1, $3
; MIPS32R6-NEXT: andi $3, $2, 65535
; MIPS32R6-NEXT: move $2, $1
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize6_Align8* %S to i48*
@ -349,29 +365,31 @@ entry:
define i64 @load7align1(%struct.MemSize7_Align1* %S) {
; MIPS32-LABEL: load7align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 7($4)
; MIPS32-NEXT: lwr $1, 4($4)
; MIPS32-NEXT: addiu $4, $zero, 65535
; MIPS32-NEXT: lui $3, 255
; MIPS32-NEXT: ori $3, $3, 65535
; MIPS32-NEXT: and $2, $2, $4
; MIPS32-NEXT: and $3, $1, $3
; MIPS32-NEXT: lwl $1, 3($4)
; MIPS32-NEXT: lwr $1, 0($4)
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 7($4)
; MIPS32-NEXT: lwr $2, 4($4)
; MIPS32-NEXT: addiu $3, $zero, 65535
; MIPS32-NEXT: lui $4, 255
; MIPS32-NEXT: ori $4, $4, 65535
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: and $3, $2, $4
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load7align1:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lw $2, 0($4)
; MIPS32R6-NEXT: lw $1, 4($4)
; MIPS32R6-NEXT: addiu $4, $zero, 65535
; MIPS32R6-NEXT: lui $3, 255
; MIPS32R6-NEXT: ori $3, $3, 65535
; MIPS32R6-NEXT: and $2, $2, $4
; MIPS32R6-NEXT: and $3, $1, $3
; MIPS32R6-NEXT: lw $1, 0($4)
; MIPS32R6-NEXT: lw $2, 4($4)
; MIPS32R6-NEXT: addiu $3, $zero, 65535
; MIPS32R6-NEXT: lui $4, 255
; MIPS32R6-NEXT: ori $4, $4, 65535
; MIPS32R6-NEXT: and $1, $1, $3
; MIPS32R6-NEXT: and $3, $2, $4
; MIPS32R6-NEXT: move $2, $1
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize7_Align1* %S to i56*
@ -383,29 +401,31 @@ entry:
define i64 @load7align2(%struct.MemSize7_Align2* %S) {
; MIPS32-LABEL: load7align2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($4)
; MIPS32-NEXT: lwr $2, 0($4)
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 7($4)
; MIPS32-NEXT: lwr $1, 4($4)
; MIPS32-NEXT: addiu $4, $zero, 65535
; MIPS32-NEXT: lui $3, 255
; MIPS32-NEXT: ori $3, $3, 65535
; MIPS32-NEXT: and $2, $2, $4
; MIPS32-NEXT: and $3, $1, $3
; MIPS32-NEXT: lwl $1, 3($4)
; MIPS32-NEXT: lwr $1, 0($4)
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 7($4)
; MIPS32-NEXT: lwr $2, 4($4)
; MIPS32-NEXT: addiu $3, $zero, 65535
; MIPS32-NEXT: lui $4, 255
; MIPS32-NEXT: ori $4, $4, 65535
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: and $3, $2, $4
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load7align2:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lw $2, 0($4)
; MIPS32R6-NEXT: lw $1, 4($4)
; MIPS32R6-NEXT: addiu $4, $zero, 65535
; MIPS32R6-NEXT: lui $3, 255
; MIPS32R6-NEXT: ori $3, $3, 65535
; MIPS32R6-NEXT: and $2, $2, $4
; MIPS32R6-NEXT: and $3, $1, $3
; MIPS32R6-NEXT: lw $1, 0($4)
; MIPS32R6-NEXT: lw $2, 4($4)
; MIPS32R6-NEXT: addiu $3, $zero, 65535
; MIPS32R6-NEXT: lui $4, 255
; MIPS32R6-NEXT: ori $4, $4, 65535
; MIPS32R6-NEXT: and $1, $1, $3
; MIPS32R6-NEXT: and $3, $2, $4
; MIPS32R6-NEXT: move $2, $1
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize7_Align2* %S to i56*
@ -417,25 +437,27 @@ entry:
define i64 @load7align4(%struct.MemSize7_Align4* %S) {
; MIPS32-LABEL: load7align4:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lw $2, 0($4)
; MIPS32-NEXT: lw $1, 4($4)
; MIPS32-NEXT: addiu $4, $zero, 65535
; MIPS32-NEXT: lui $3, 255
; MIPS32-NEXT: ori $3, $3, 65535
; MIPS32-NEXT: and $2, $2, $4
; MIPS32-NEXT: and $3, $1, $3
; MIPS32-NEXT: lw $1, 0($4)
; MIPS32-NEXT: lw $2, 4($4)
; MIPS32-NEXT: addiu $3, $zero, 65535
; MIPS32-NEXT: lui $4, 255
; MIPS32-NEXT: ori $4, $4, 65535
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: and $3, $2, $4
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load7align4:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lw $2, 0($4)
; MIPS32R6-NEXT: lw $1, 4($4)
; MIPS32R6-NEXT: addiu $4, $zero, 65535
; MIPS32R6-NEXT: lui $3, 255
; MIPS32R6-NEXT: ori $3, $3, 65535
; MIPS32R6-NEXT: and $2, $2, $4
; MIPS32R6-NEXT: and $3, $1, $3
; MIPS32R6-NEXT: lw $1, 0($4)
; MIPS32R6-NEXT: lw $2, 4($4)
; MIPS32R6-NEXT: addiu $3, $zero, 65535
; MIPS32R6-NEXT: lui $4, 255
; MIPS32R6-NEXT: ori $4, $4, 65535
; MIPS32R6-NEXT: and $1, $1, $3
; MIPS32R6-NEXT: and $3, $2, $4
; MIPS32R6-NEXT: move $2, $1
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize7_Align4* %S to i56*
@ -447,25 +469,27 @@ entry:
define i64 @load7align8(%struct.MemSize7_Align8* %S) {
; MIPS32-LABEL: load7align8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lw $2, 0($4)
; MIPS32-NEXT: lw $1, 4($4)
; MIPS32-NEXT: addiu $4, $zero, 65535
; MIPS32-NEXT: lui $3, 255
; MIPS32-NEXT: ori $3, $3, 65535
; MIPS32-NEXT: and $2, $2, $4
; MIPS32-NEXT: and $3, $1, $3
; MIPS32-NEXT: lw $1, 0($4)
; MIPS32-NEXT: lw $2, 4($4)
; MIPS32-NEXT: addiu $3, $zero, 65535
; MIPS32-NEXT: lui $4, 255
; MIPS32-NEXT: ori $4, $4, 65535
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: and $3, $2, $4
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: load7align8:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lw $2, 0($4)
; MIPS32R6-NEXT: lw $1, 4($4)
; MIPS32R6-NEXT: addiu $4, $zero, 65535
; MIPS32R6-NEXT: lui $3, 255
; MIPS32R6-NEXT: ori $3, $3, 65535
; MIPS32R6-NEXT: and $2, $2, $4
; MIPS32R6-NEXT: and $3, $1, $3
; MIPS32R6-NEXT: lw $1, 0($4)
; MIPS32R6-NEXT: lw $2, 4($4)
; MIPS32R6-NEXT: addiu $3, $zero, 65535
; MIPS32R6-NEXT: lui $4, 255
; MIPS32R6-NEXT: ori $4, $4, 65535
; MIPS32R6-NEXT: and $1, $1, $3
; MIPS32R6-NEXT: and $3, $2, $4
; MIPS32R6-NEXT: move $2, $1
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize7_Align8* %S to i56*
@ -478,15 +502,15 @@ define double @load_double_align1() {
; MIPS32-LABEL: load_double_align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(double_align1)
; MIPS32-NEXT: addiu $3, $1, %lo(double_align1)
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 3($3)
; MIPS32-NEXT: lwr $1, 0($3)
; MIPS32-NEXT: addiu $1, $1, %lo(double_align1)
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 7($3)
; MIPS32-NEXT: lwr $2, 4($3)
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: mtc1 $2, $f1
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
; MIPS32-NEXT: # implicit-def: $v1
; MIPS32-NEXT: lwl $3, 7($1)
; MIPS32-NEXT: lwr $3, 4($1)
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: mtc1 $3, $f1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
@ -505,15 +529,15 @@ define double @load_double_align2() {
; MIPS32-LABEL: load_double_align2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(double_align2)
; MIPS32-NEXT: addiu $3, $1, %lo(double_align2)
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 3($3)
; MIPS32-NEXT: lwr $1, 0($3)
; MIPS32-NEXT: addiu $1, $1, %lo(double_align2)
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 7($3)
; MIPS32-NEXT: lwr $2, 4($3)
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: mtc1 $2, $f1
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
; MIPS32-NEXT: # implicit-def: $v1
; MIPS32-NEXT: lwl $3, 7($1)
; MIPS32-NEXT: lwr $3, 4($1)
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: mtc1 $3, $f1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
@ -532,11 +556,11 @@ define double @load_double_align4() {
; MIPS32-LABEL: load_double_align4:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(double_align4)
; MIPS32-NEXT: addiu $2, $1, %lo(double_align4)
; MIPS32-NEXT: lw $1, 0($2)
; MIPS32-NEXT: lw $2, 4($2)
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: mtc1 $2, $f1
; MIPS32-NEXT: addiu $1, $1, %lo(double_align4)
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: lw $1, 4($1)
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: mtc1 $1, $f1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;

502
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s32.ll
View File

@ -6,124 +6,126 @@ define void @long_chain_ambiguous_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32*
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -48
; MIPS32-NEXT: .cfi_def_cfa_offset 48
; MIPS32-NEXT: sw $4, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 32($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 64
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 36($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 68
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 72
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: addiu $2, $sp, 68
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: addiu $3, $sp, 72
; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: andi $8, $4, 1
; MIPS32-NEXT: sw $1, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: bnez $1, $BB0_12
; MIPS32-NEXT: sw $4, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 36($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 32($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $8, $BB0_12
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB0_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_2: # %pre.PHI.1
; MIPS32-NEXT: lw $1, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB0_7
; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB0_7
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.3: # %pre.PHI.1
; MIPS32-NEXT: j $BB0_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_4: # %pre.PHI.1.0
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB0_8
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB0_8
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.5: # %pre.PHI.1.0
; MIPS32-NEXT: j $BB0_6
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_6: # %b.PHI.1.0
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB0_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_7: # %b.PHI.1.1
; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB0_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_8: # %b.PHI.1.2
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB0_9: # %b.PHI.1
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $2, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: sw $2, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB0_11
; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $3, $2, 1
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: sw $1, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $3, $BB0_11
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.10: # %b.PHI.1
; MIPS32-NEXT: j $BB0_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_11: # %b.PHI.1.end
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 0($2)
; MIPS32-NEXT: addiu $sp, $sp, 48
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_12: # %pre.PHI.2
; MIPS32-NEXT: lw $1, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB0_14
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB0_14
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.13: # %pre.PHI.2
; MIPS32-NEXT: j $BB0_15
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_14: # %b.PHI.2.0
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB0_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_15: # %b.PHI.2.1
; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB0_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $2, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: sw $2, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB0_19
; MIPS32-NEXT: lw $1, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $3, $2, 1
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $3, $BB0_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.17: # %b.PHI.2
; MIPS32-NEXT: j $BB0_18
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_18: # %b.PHI.2.end
; MIPS32-NEXT: lw $1, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 0($2)
; MIPS32-NEXT: addiu $sp, $sp, 48
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_19: # %b.PHI.3
; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $5, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: andi $5, $5, 1
; MIPS32-NEXT: movn $4, $1, $5
; MIPS32-NEXT: andi $5, $3, 1
; MIPS32-NEXT: move $3, $1
; MIPS32-NEXT: movn $3, $4, $5
; MIPS32-NEXT: sw $3, 0($2)
; MIPS32-NEXT: sw $1, 0($2)
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $4, $3, 1
; MIPS32-NEXT: movn $1, $2, $4
; MIPS32-NEXT: lw $4, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $5, $4, 1
; MIPS32-NEXT: move $6, $2
; MIPS32-NEXT: movn $6, $1, $5
; MIPS32-NEXT: lw $1, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $6, 0($1)
; MIPS32-NEXT: sw $2, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, 48
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@ -191,130 +193,132 @@ define void @long_chain_i32_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i32* %a, i32* %
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -56
; MIPS32-NEXT: .cfi_def_cfa_offset 56
; MIPS32-NEXT: sw $4, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 32($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 36($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 72
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 76
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 80
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 48($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: addiu $2, $sp, 76
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: addiu $3, $sp, 80
; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: ori $8, $zero, 0
; MIPS32-NEXT: andi $9, $4, 1
; MIPS32-NEXT: sw $1, 52($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: bnez $1, $BB1_12
; MIPS32-NEXT: sw $4, 48($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 36($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 32($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $8, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $9, $BB1_12
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB1_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_2: # %pre.PHI.1
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB1_7
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB1_7
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.3: # %pre.PHI.1
; MIPS32-NEXT: j $BB1_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_4: # %pre.PHI.1.0
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB1_8
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB1_8
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.5: # %pre.PHI.1.0
; MIPS32-NEXT: j $BB1_6
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_6: # %b.PHI.1.0
; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB1_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_7: # %b.PHI.1.1
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB1_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_8: # %b.PHI.1.2
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB1_9: # %b.PHI.1
; MIPS32-NEXT: lw $2, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $3, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: sw $3, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB1_11
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB1_9: # %b.PHI.1
; MIPS32-NEXT: lw $1, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $3, $2, 1
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: lw $5, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $4, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $3, $BB1_11
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.10: # %b.PHI.1
; MIPS32-NEXT: j $BB1_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_11: # %b.PHI.1.end
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 0($2)
; MIPS32-NEXT: addiu $sp, $sp, 56
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_12: # %pre.PHI.2
; MIPS32-NEXT: lw $1, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB1_14
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB1_14
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.13: # %pre.PHI.2
; MIPS32-NEXT: j $BB1_15
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_14: # %b.PHI.2.0
; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB1_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_15: # %b.PHI.2.1
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB1_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $2, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: move $3, $2
; MIPS32-NEXT: sw $3, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB1_19
; MIPS32-NEXT: lw $1, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $3, $2, 1
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: move $5, $1
; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $4, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $3, $BB1_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.17: # %b.PHI.2
; MIPS32-NEXT: j $BB1_18
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_18: # %b.PHI.2.end
; MIPS32-NEXT: lw $1, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 0($2)
; MIPS32-NEXT: addiu $sp, $sp, 56
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_19: # %b.PHI.3
; MIPS32-NEXT: lw $2, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $5, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $4, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $5, $5, 1
; MIPS32-NEXT: movn $4, $1, $5
; MIPS32-NEXT: andi $5, $3, 1
; MIPS32-NEXT: move $3, $1
; MIPS32-NEXT: movn $3, $4, $5
; MIPS32-NEXT: sw $3, 0($2)
; MIPS32-NEXT: sw $1, 0($2)
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $4, $3, 1
; MIPS32-NEXT: movn $1, $2, $4
; MIPS32-NEXT: lw $4, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $5, $4, 1
; MIPS32-NEXT: move $6, $2
; MIPS32-NEXT: movn $6, $1, $5
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $6, 0($1)
; MIPS32-NEXT: sw $2, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, 56
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@ -381,124 +385,126 @@ define void @long_chain_ambiguous_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, flo
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -48
; MIPS32-NEXT: .cfi_def_cfa_offset 48
; MIPS32-NEXT: sw $4, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 32($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 64
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 36($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 68
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 72
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: addiu $2, $sp, 68
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: addiu $3, $sp, 72
; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: andi $8, $4, 1
; MIPS32-NEXT: sw $1, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: bnez $1, $BB2_12
; MIPS32-NEXT: sw $4, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 36($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 32($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $8, $BB2_12
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB2_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_2: # %pre.PHI.1
; MIPS32-NEXT: lw $1, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB2_7
; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB2_7
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.3: # %pre.PHI.1
; MIPS32-NEXT: j $BB2_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_4: # %pre.PHI.1.0
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB2_8
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB2_8
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.5: # %pre.PHI.1.0
; MIPS32-NEXT: j $BB2_6
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_6: # %b.PHI.1.0
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB2_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_7: # %b.PHI.1.1
; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB2_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_8: # %b.PHI.1.2
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB2_9: # %b.PHI.1
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $2, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: sw $2, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB2_11
; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $3, $2, 1
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: sw $1, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $3, $BB2_11
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.10: # %b.PHI.1
; MIPS32-NEXT: j $BB2_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_11: # %b.PHI.1.end
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 0($2)
; MIPS32-NEXT: addiu $sp, $sp, 48
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_12: # %pre.PHI.2
; MIPS32-NEXT: lw $1, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB2_14
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB2_14
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.13: # %pre.PHI.2
; MIPS32-NEXT: j $BB2_15
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_14: # %b.PHI.2.0
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB2_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_15: # %b.PHI.2.1
; MIPS32-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB2_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $2, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: sw $2, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB2_19
; MIPS32-NEXT: lw $1, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $3, $2, 1
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $4, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $3, $BB2_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.17: # %b.PHI.2
; MIPS32-NEXT: j $BB2_18
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_18: # %b.PHI.2.end
; MIPS32-NEXT: lw $1, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 0($2)
; MIPS32-NEXT: addiu $sp, $sp, 48
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_19: # %b.PHI.3
; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $5, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: andi $5, $5, 1
; MIPS32-NEXT: movn $4, $1, $5
; MIPS32-NEXT: andi $5, $3, 1
; MIPS32-NEXT: move $3, $1
; MIPS32-NEXT: movn $3, $4, $5
; MIPS32-NEXT: sw $3, 0($2)
; MIPS32-NEXT: sw $1, 0($2)
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $4, $3, 1
; MIPS32-NEXT: movn $1, $2, $4
; MIPS32-NEXT: lw $4, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $5, $4, 1
; MIPS32-NEXT: move $6, $2
; MIPS32-NEXT: movn $6, $1, $5
; MIPS32-NEXT: lw $1, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $6, 0($1)
; MIPS32-NEXT: sw $2, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, 48
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@ -566,40 +572,40 @@ define void @long_chain_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, float* %a, fl
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -56
; MIPS32-NEXT: .cfi_def_cfa_offset 56
; MIPS32-NEXT: sw $4, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 32($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 36($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 72
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 76
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 80
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 48($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: swc1 $f0, 52($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: bnez $1, $BB3_12
; MIPS32-NEXT: addiu $2, $sp, 76
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: addiu $3, $sp, 80
; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: ori $8, $zero, 0
; MIPS32-NEXT: mtc1 $8, $f0
; MIPS32-NEXT: andi $8, $4, 1
; MIPS32-NEXT: sw $1, 52($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $4, 48($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 36($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 32($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: swc1 $f0, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $8, $BB3_12
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB3_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_2: # %pre.PHI.1
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB3_7
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB3_7
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.3: # %pre.PHI.1
; MIPS32-NEXT: j $BB3_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_4: # %pre.PHI.1.0
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB3_8
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB3_8
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.5: # %pre.PHI.1.0
; MIPS32-NEXT: j $BB3_6
@ -611,39 +617,40 @@ define void @long_chain_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, float* %a, fl
; MIPS32-NEXT: j $BB3_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_7: # %b.PHI.1.1
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lwc1 $f0, 0($1)
; MIPS32-NEXT: swc1 $f0, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB3_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_8: # %b.PHI.1.2
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lwc1 $f0, 0($1)
; MIPS32-NEXT: swc1 $f0, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB3_9: # %b.PHI.1
; MIPS32-NEXT: lwc1 $f0, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lwc1 $f1, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: swc1 $f1, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: swc1 $f1, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lwc1 $f0, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: mov.s $f1, $f0
; MIPS32-NEXT: lwc1 $f2, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: swc1 $f0, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB3_11
; MIPS32-NEXT: swc1 $f1, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: swc1 $f2, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $2, $BB3_11
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.10: # %b.PHI.1
; MIPS32-NEXT: j $BB3_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_11: # %b.PHI.1.end
; MIPS32-NEXT: lwc1 $f0, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lwc1 $f0, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: swc1 $f0, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, 56
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_12: # %pre.PHI.2
; MIPS32-NEXT: lw $1, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB3_14
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB3_14
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.13: # %pre.PHI.2
; MIPS32-NEXT: j $BB3_15
@ -655,42 +662,43 @@ define void @long_chain_float_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, float* %a, fl
; MIPS32-NEXT: j $BB3_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_15: # %b.PHI.2.1
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lwc1 $f0, 0($1)
; MIPS32-NEXT: swc1 $f0, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB3_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lwc1 $f0, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: swc1 $f0, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: mov.s $f1, $f0
; MIPS32-NEXT: mov.s $f2, $f0
; MIPS32-NEXT: swc1 $f0, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: swc1 $f1, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: swc1 $f0, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB3_19
; MIPS32-NEXT: swc1 $f2, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $2, $BB3_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.17: # %b.PHI.2
; MIPS32-NEXT: j $BB3_18
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_18: # %b.PHI.2.end
; MIPS32-NEXT: lwc1 $f0, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: swc1 $f0, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, 56
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_19: # %b.PHI.3
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lwc1 $f0, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lwc1 $f2, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: lwc1 $f0, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lwc1 $f1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: movn.s $f0, $f1, $2
; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $3, $2, 1
; MIPS32-NEXT: mov.s $f2, $f1
; MIPS32-NEXT: movn.s $f2, $f0, $3
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: mov.s $f1, $f0
; MIPS32-NEXT: movn.s $f1, $f2, $2
; MIPS32-NEXT: swc1 $f1, 0($1)
; MIPS32-NEXT: swc1 $f0, 0($1)
; MIPS32-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: swc1 $f2, 0($3)
; MIPS32-NEXT: swc1 $f1, 0($3)
; MIPS32-NEXT: addiu $sp, $sp, 56
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop

502
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/long_ambiguous_chain_s64.ll
View File

@ -6,124 +6,126 @@ define void @long_chain_ambiguous_i64_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64*
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -72
; MIPS32-NEXT: .cfi_def_cfa_offset 72
; MIPS32-NEXT: sw $4, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 48($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 52($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 56($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 88
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 60($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 92
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 64($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 96
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: addiu $2, $sp, 92
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: addiu $3, $sp, 96
; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: andi $8, $4, 1
; MIPS32-NEXT: sw $1, 68($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: bnez $1, $BB0_12
; MIPS32-NEXT: sw $4, 64($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 60($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 56($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 52($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 48($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $8, $BB0_12
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB0_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_2: # %pre.PHI.1
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB0_7
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB0_7
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.3: # %pre.PHI.1
; MIPS32-NEXT: j $BB0_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_4: # %pre.PHI.1.0
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB0_8
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB0_8
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.5: # %pre.PHI.1.0
; MIPS32-NEXT: j $BB0_6
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_6: # %b.PHI.1.0
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB0_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_7: # %b.PHI.1.1
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB0_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_8: # %b.PHI.1.2
; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill
; MIPS32-NEXT: $BB0_9: # %b.PHI.1
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 32($sp) # 8-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 16($sp) # 8-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: mov.d $f2, $f0
; MIPS32-NEXT: sdc1 $f0, 24($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB0_11
; MIPS32-NEXT: sdc1 $f2, 16($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $2, $BB0_11
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.10: # %b.PHI.1
; MIPS32-NEXT: j $BB0_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_11: # %b.PHI.1.end
; MIPS32-NEXT: ldc1 $f0, 16($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 24($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, 72
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_12: # %pre.PHI.2
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB0_14
; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB0_14
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.13: # %pre.PHI.2
; MIPS32-NEXT: j $BB0_15
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_14: # %b.PHI.2.0
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB0_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_15: # %b.PHI.2.1
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill
; MIPS32-NEXT: $BB0_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 8($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: mov.d $f2, $f0
; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: sdc1 $f0, 24($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB0_19
; MIPS32-NEXT: sdc1 $f2, 16($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $2, $BB0_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.17: # %b.PHI.2
; MIPS32-NEXT: j $BB0_18
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_18: # %b.PHI.2.end
; MIPS32-NEXT: ldc1 $f0, 0($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, 72
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_19: # %b.PHI.3
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 24($sp) # 8-byte Folded Reload
; MIPS32-NEXT: mov.d $f4, $f0
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: ldc1 $f0, 16($sp) # 8-byte Folded Reload
; MIPS32-NEXT: ldc1 $f2, 16($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: movn.d $f0, $f2, $2
; MIPS32-NEXT: lw $2, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $3, $2, 1
; MIPS32-NEXT: mov.d $f4, $f2
; MIPS32-NEXT: movn.d $f4, $f0, $3
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: mov.d $f2, $f0
; MIPS32-NEXT: movn.d $f2, $f4, $2
; MIPS32-NEXT: sdc1 $f2, 0($1)
; MIPS32-NEXT: sdc1 $f0, 0($1)
; MIPS32-NEXT: lw $3, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f4, 0($3)
; MIPS32-NEXT: sdc1 $f2, 0($3)
; MIPS32-NEXT: addiu $sp, $sp, 72
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@ -191,39 +193,39 @@ define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* %
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -80
; MIPS32-NEXT: .cfi_def_cfa_offset 80
; MIPS32-NEXT: sw $4, 48($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 52($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 56($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 60($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 96
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 64($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 100
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 68($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 104
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 72($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: addiu $2, $sp, 100
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: addiu $3, $sp, 104
; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: ori $8, $zero, 0
; MIPS32-NEXT: andi $9, $4, 1
; MIPS32-NEXT: sw $1, 76($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: bnez $1, $BB1_12
; MIPS32-NEXT: sw $4, 72($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 68($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 64($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 60($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 56($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 52($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $8, 48($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $9, $BB1_12
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB1_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_2: # %pre.PHI.1
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB1_7
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB1_7
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.3: # %pre.PHI.1
; MIPS32-NEXT: j $BB1_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_4: # %pre.PHI.1.0
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB1_8
; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB1_8
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.5: # %pre.PHI.1.0
; MIPS32-NEXT: j $BB1_6
@ -231,56 +233,58 @@ define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* %
; MIPS32-NEXT: $BB1_6: # %b.PHI.1.0
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: lw $1, 4($1)
; MIPS32-NEXT: sw $2, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $1, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $3, 4($1)
; MIPS32-NEXT: sw $2, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB1_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_7: # %b.PHI.1.1
; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 76($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: lw $1, 4($1)
; MIPS32-NEXT: sw $2, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $1, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $3, 4($1)
; MIPS32-NEXT: sw $2, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB1_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_8: # %b.PHI.1.2
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: lw $1, 4($1)
; MIPS32-NEXT: sw $2, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $1, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB1_9: # %b.PHI.1
; MIPS32-NEXT: lw $2, 76($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $4, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $3, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $4, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: sw $4, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $3, $2
; MIPS32-NEXT: sw $3, 32($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 36($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB1_11
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: lw $3, 4($1)
; MIPS32-NEXT: sw $2, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 40($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB1_9: # %b.PHI.1
; MIPS32-NEXT: lw $1, 40($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $4, $3, 1
; MIPS32-NEXT: move $5, $2
; MIPS32-NEXT: move $6, $1
; MIPS32-NEXT: lw $7, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $8, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 36($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 32($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $8, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $4, $BB1_11
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.10: # %b.PHI.1
; MIPS32-NEXT: j $BB1_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_11: # %b.PHI.1.end
; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 72($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $3, 0($2)
; MIPS32-NEXT: sw $1, 4($2)
; MIPS32-NEXT: lw $1, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 0($2)
; MIPS32-NEXT: lw $3, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $3, 4($2)
; MIPS32-NEXT: addiu $sp, $sp, 80
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_12: # %pre.PHI.2
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB1_14
; MIPS32-NEXT: lw $1, 72($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB1_14
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.13: # %pre.PHI.2
; MIPS32-NEXT: j $BB1_15
@ -288,64 +292,66 @@ define void @long_chain_i64_in_gpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, i64* %a, i64* %
; MIPS32-NEXT: $BB1_14: # %b.PHI.2.0
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: lw $1, 4($1)
; MIPS32-NEXT: sw $2, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $1, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $3, 4($1)
; MIPS32-NEXT: sw $2, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB1_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_15: # %b.PHI.2.1
; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 76($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: lw $1, 4($1)
; MIPS32-NEXT: sw $2, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $1, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $3, 4($1)
; MIPS32-NEXT: sw $2, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB1_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $4, $3, 1
; MIPS32-NEXT: move $5, $2
; MIPS32-NEXT: move $6, $1
; MIPS32-NEXT: move $7, $2
; MIPS32-NEXT: move $8, $1
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: move $4, $3
; MIPS32-NEXT: sw $4, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $4, $2
; MIPS32-NEXT: sw $4, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 32($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 36($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB1_19
; MIPS32-NEXT: sw $5, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $8, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $4, $BB1_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.17: # %b.PHI.2
; MIPS32-NEXT: j $BB1_18
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_18: # %b.PHI.2.end
; MIPS32-NEXT: lw $1, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 72($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 0($2)
; MIPS32-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $3, 0($2)
; MIPS32-NEXT: sw $1, 4($2)
; MIPS32-NEXT: sw $3, 4($2)
; MIPS32-NEXT: addiu $sp, $sp, 80
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_19: # %b.PHI.3
; MIPS32-NEXT: lw $2, 72($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $5, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $7, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $4, 32($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $6, 36($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $7, $7, 1
; MIPS32-NEXT: movn $4, $3, $7
; MIPS32-NEXT: movn $6, $1, $7
; MIPS32-NEXT: andi $7, $5, 1
; MIPS32-NEXT: move $5, $3
; MIPS32-NEXT: movn $5, $4, $7
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: movn $4, $6, $7
; MIPS32-NEXT: sw $5, 0($2)
; MIPS32-NEXT: sw $4, 4($2)
; MIPS32-NEXT: sw $3, 0($2)
; MIPS32-NEXT: sw $1, 4($2)
; MIPS32-NEXT: lw $4, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $5, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $6, $5, 1
; MIPS32-NEXT: movn $2, $4, $6
; MIPS32-NEXT: movn $1, $3, $6
; MIPS32-NEXT: lw $6, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $7, $6, 1
; MIPS32-NEXT: move $8, $4
; MIPS32-NEXT: movn $8, $2, $7
; MIPS32-NEXT: move $2, $3
; MIPS32-NEXT: movn $2, $1, $7
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $8, 0($1)
; MIPS32-NEXT: sw $2, 4($1)
; MIPS32-NEXT: sw $4, 0($1)
; MIPS32-NEXT: sw $3, 4($1)
; MIPS32-NEXT: addiu $sp, $sp, 80
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@ -412,124 +418,126 @@ define void @long_chain_ambiguous_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, do
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -72
; MIPS32-NEXT: .cfi_def_cfa_offset 72
; MIPS32-NEXT: sw $4, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 48($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 52($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 56($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 88
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 60($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 92
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 64($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 96
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: addiu $2, $sp, 92
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: addiu $3, $sp, 96
; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: andi $8, $4, 1
; MIPS32-NEXT: sw $1, 68($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: bnez $1, $BB2_12
; MIPS32-NEXT: sw $4, 64($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 60($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 56($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 52($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 48($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 44($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $8, $BB2_12
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB2_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_2: # %pre.PHI.1
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB2_7
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB2_7
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.3: # %pre.PHI.1
; MIPS32-NEXT: j $BB2_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_4: # %pre.PHI.1.0
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB2_8
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB2_8
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.5: # %pre.PHI.1.0
; MIPS32-NEXT: j $BB2_6
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_6: # %b.PHI.1.0
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB2_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_7: # %b.PHI.1.1
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB2_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_8: # %b.PHI.1.2
; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill
; MIPS32-NEXT: $BB2_9: # %b.PHI.1
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 32($sp) # 8-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 16($sp) # 8-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: mov.d $f2, $f0
; MIPS32-NEXT: sdc1 $f0, 24($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB2_11
; MIPS32-NEXT: sdc1 $f2, 16($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $2, $BB2_11
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.10: # %b.PHI.1
; MIPS32-NEXT: j $BB2_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_11: # %b.PHI.1.end
; MIPS32-NEXT: ldc1 $f0, 16($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 24($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, 72
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_12: # %pre.PHI.2
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB2_14
; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB2_14
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.13: # %pre.PHI.2
; MIPS32-NEXT: j $BB2_15
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_14: # %b.PHI.2.0
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB2_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_15: # %b.PHI.2.1
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill
; MIPS32-NEXT: $BB2_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 8($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: mov.d $f2, $f0
; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: sdc1 $f0, 24($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB2_19
; MIPS32-NEXT: sdc1 $f2, 16($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $2, $BB2_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.17: # %b.PHI.2
; MIPS32-NEXT: j $BB2_18
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_18: # %b.PHI.2.end
; MIPS32-NEXT: ldc1 $f0, 0($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, 72
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_19: # %b.PHI.3
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 48($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 24($sp) # 8-byte Folded Reload
; MIPS32-NEXT: mov.d $f4, $f0
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: ldc1 $f0, 16($sp) # 8-byte Folded Reload
; MIPS32-NEXT: ldc1 $f2, 16($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: movn.d $f0, $f2, $2
; MIPS32-NEXT: lw $2, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $3, $2, 1
; MIPS32-NEXT: mov.d $f4, $f2
; MIPS32-NEXT: movn.d $f4, $f0, $3
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: mov.d $f2, $f0
; MIPS32-NEXT: movn.d $f2, $f4, $2
; MIPS32-NEXT: sdc1 $f2, 0($1)
; MIPS32-NEXT: sdc1 $f0, 0($1)
; MIPS32-NEXT: lw $3, 44($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f4, 0($3)
; MIPS32-NEXT: sdc1 $f2, 0($3)
; MIPS32-NEXT: addiu $sp, $sp, 72
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@ -597,133 +605,135 @@ define void @long_chain_double_in_fpr(i1 %cnd0, i1 %cnd1, i1 %cnd2, double* %a,
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -88
; MIPS32-NEXT: .cfi_def_cfa_offset 88
; MIPS32-NEXT: sw $4, 52($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 56($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 60($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 64($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 104
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 68($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 108
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 72($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 112
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 76($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: mtc1 $2, $f1
; MIPS32-NEXT: sdc1 $f0, 80($sp) # 8-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: bnez $1, $BB3_12
; MIPS32-NEXT: addiu $2, $sp, 108
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: addiu $3, $sp, 112
; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: ori $8, $zero, 0
; MIPS32-NEXT: ori $9, $zero, 0
; MIPS32-NEXT: mtc1 $9, $f0
; MIPS32-NEXT: mtc1 $8, $f1
; MIPS32-NEXT: andi $8, $4, 1
; MIPS32-NEXT: sw $1, 84($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $4, 80($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 76($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 72($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 68($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 64($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 60($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sdc1 $f0, 48($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $8, $BB3_12
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB3_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_2: # %pre.PHI.1
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB3_7
; MIPS32-NEXT: lw $1, 76($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB3_7
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.3: # %pre.PHI.1
; MIPS32-NEXT: j $BB3_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_4: # %pre.PHI.1.0
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB3_8
; MIPS32-NEXT: lw $1, 72($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB3_8
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.5: # %pre.PHI.1.0
; MIPS32-NEXT: j $BB3_6
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_6: # %b.PHI.1.0
; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 40($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB3_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_7: # %b.PHI.1.1
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 84($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 40($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB3_9
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_8: # %b.PHI.1.2
; MIPS32-NEXT: lw $1, 72($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 40($sp) # 8-byte Folded Spill
; MIPS32-NEXT: $BB3_9: # %b.PHI.1
; MIPS32-NEXT: ldc1 $f0, 80($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f2, 40($sp) # 8-byte Folded Reload
; MIPS32-NEXT: sdc1 $f2, 16($sp) # 8-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: sdc1 $f2, 24($sp) # 8-byte Folded Spill
; MIPS32-NEXT: ldc1 $f0, 40($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 72($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: mov.d $f2, $f0
; MIPS32-NEXT: ldc1 $f4, 48($sp) # 8-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB3_11
; MIPS32-NEXT: sdc1 $f2, 24($sp) # 8-byte Folded Spill
; MIPS32-NEXT: sdc1 $f4, 16($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $2, $BB3_11
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.10: # %b.PHI.1
; MIPS32-NEXT: j $BB3_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_11: # %b.PHI.1.end
; MIPS32-NEXT: ldc1 $f0, 16($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 76($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 32($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, 88
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_12: # %pre.PHI.2
; MIPS32-NEXT: lw $1, 52($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB3_14
; MIPS32-NEXT: lw $1, 80($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: bnez $2, $BB3_14
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.13: # %pre.PHI.2
; MIPS32-NEXT: j $BB3_15
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_14: # %b.PHI.2.0
; MIPS32-NEXT: lw $1, 64($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB3_16
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_15: # %b.PHI.2.1
; MIPS32-NEXT: lw $1, 68($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 84($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f0, 8($sp) # 8-byte Folded Spill
; MIPS32-NEXT: $BB3_16: # %b.PHI.2
; MIPS32-NEXT: lw $1, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 8($sp) # 8-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: lw $1, 76($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: mov.d $f2, $f0
; MIPS32-NEXT: mov.d $f4, $f0
; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
; MIPS32-NEXT: sdc1 $f2, 24($sp) # 8-byte Folded Spill
; MIPS32-NEXT: sdc1 $f0, 32($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB3_19
; MIPS32-NEXT: sdc1 $f4, 16($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $2, $BB3_19
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.17: # %b.PHI.2
; MIPS32-NEXT: j $BB3_18
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_18: # %b.PHI.2.end
; MIPS32-NEXT: ldc1 $f0, 0($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 76($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, 88
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_19: # %b.PHI.3
; MIPS32-NEXT: lw $1, 76($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 56($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 24($sp) # 8-byte Folded Reload
; MIPS32-NEXT: ldc1 $f4, 32($sp) # 8-byte Folded Reload
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: ldc1 $f0, 16($sp) # 8-byte Folded Reload
; MIPS32-NEXT: ldc1 $f2, 24($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 72($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $2, $1, 1
; MIPS32-NEXT: movn.d $f0, $f2, $2
; MIPS32-NEXT: lw $2, 76($sp) # 4-byte Folded Reload
; MIPS32-NEXT: andi $3, $2, 1
; MIPS32-NEXT: mov.d $f4, $f2
; MIPS32-NEXT: movn.d $f4, $f0, $3
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: mov.d $f2, $f0
; MIPS32-NEXT: movn.d $f2, $f4, $2
; MIPS32-NEXT: sdc1 $f2, 0($1)
; MIPS32-NEXT: sdc1 $f0, 0($1)
; MIPS32-NEXT: lw $3, 60($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f4, 0($3)
; MIPS32-NEXT: sdc1 $f2, 0($3)
; MIPS32-NEXT: addiu $sp, $sp, 88
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop

142
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll
View File

@ -86,14 +86,13 @@ entry:
define i64 @mul_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: mul_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $3, $4
; MIPS32-NEXT: mul $2, $6, $3
; MIPS32-NEXT: mul $1, $7, $3
; MIPS32-NEXT: mul $4, $6, $5
; MIPS32-NEXT: multu $6, $3
; MIPS32-NEXT: mfhi $3
; MIPS32-NEXT: addu $1, $1, $4
; MIPS32-NEXT: addu $3, $1, $3
; MIPS32-NEXT: mul $2, $6, $4
; MIPS32-NEXT: mul $1, $7, $4
; MIPS32-NEXT: mul $3, $6, $5
; MIPS32-NEXT: multu $6, $4
; MIPS32-NEXT: mfhi $4
; MIPS32-NEXT: addu $1, $1, $3
; MIPS32-NEXT: addu $3, $1, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -104,73 +103,72 @@ entry:
define i128 @mul_i128(i128 %a, i128 %b) {
; MIPS32-LABEL: mul_i128:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $14, $4
; MIPS32-NEXT: move $13, $5
; MIPS32-NEXT: move $12, $6
; MIPS32-NEXT: move $9, $7
; MIPS32-NEXT: addiu $1, $sp, 16
; MIPS32-NEXT: lw $6, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 20
; MIPS32-NEXT: lw $7, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 24
; MIPS32-NEXT: lw $8, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 28
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: mul $2, $6, $14
; MIPS32-NEXT: mul $3, $7, $14
; MIPS32-NEXT: mul $4, $6, $13
; MIPS32-NEXT: multu $6, $14
; MIPS32-NEXT: mfhi $5
; MIPS32-NEXT: addu $3, $3, $4
; MIPS32-NEXT: sltu $4, $3, $4
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: addu $3, $3, $5
; MIPS32-NEXT: sltu $5, $3, $5
; MIPS32-NEXT: andi $5, $5, 1
; MIPS32-NEXT: addu $10, $4, $5
; MIPS32-NEXT: mul $4, $8, $14
; MIPS32-NEXT: mul $5, $7, $13
; MIPS32-NEXT: mul $24, $6, $12
; MIPS32-NEXT: multu $7, $14
; MIPS32-NEXT: mfhi $15
; MIPS32-NEXT: multu $6, $13
; MIPS32-NEXT: mfhi $11
; MIPS32-NEXT: addu $4, $4, $5
; MIPS32-NEXT: sltu $5, $4, $5
; MIPS32-NEXT: andi $5, $5, 1
; MIPS32-NEXT: addu $4, $4, $24
; MIPS32-NEXT: sltu $24, $4, $24
; MIPS32-NEXT: andi $24, $24, 1
; MIPS32-NEXT: addu $5, $5, $24
; MIPS32-NEXT: addu $4, $4, $15
; MIPS32-NEXT: sltu $15, $4, $15
; MIPS32-NEXT: andi $15, $15, 1
; MIPS32-NEXT: addu $5, $5, $15
; MIPS32-NEXT: addu $4, $4, $11
; MIPS32-NEXT: sltu $11, $4, $11
; MIPS32-NEXT: addiu $2, $sp, 20
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: addiu $3, $sp, 24
; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: addiu $8, $sp, 28
; MIPS32-NEXT: lw $8, 0($8)
; MIPS32-NEXT: mul $9, $1, $4
; MIPS32-NEXT: mul $10, $2, $4
; MIPS32-NEXT: mul $11, $1, $5
; MIPS32-NEXT: multu $1, $4
; MIPS32-NEXT: mfhi $12
; MIPS32-NEXT: addu $10, $10, $11
; MIPS32-NEXT: sltu $11, $10, $11
; MIPS32-NEXT: andi $11, $11, 1
; MIPS32-NEXT: addu $5, $5, $11
; MIPS32-NEXT: addu $4, $4, $10
; MIPS32-NEXT: sltu $10, $4, $10
; MIPS32-NEXT: andi $10, $10, 1
; MIPS32-NEXT: addu $5, $5, $10
; MIPS32-NEXT: mul $1, $1, $14
; MIPS32-NEXT: mul $11, $8, $13
; MIPS32-NEXT: mul $10, $7, $12
; MIPS32-NEXT: mul $9, $6, $9
; MIPS32-NEXT: multu $8, $14
; MIPS32-NEXT: mfhi $8
; MIPS32-NEXT: multu $7, $13
; MIPS32-NEXT: mfhi $7
; MIPS32-NEXT: multu $6, $12
; MIPS32-NEXT: mfhi $6
; MIPS32-NEXT: addu $1, $1, $11
; MIPS32-NEXT: addu $1, $1, $10
; MIPS32-NEXT: addu $1, $1, $9
; MIPS32-NEXT: addu $1, $1, $8
; MIPS32-NEXT: addu $1, $1, $7
; MIPS32-NEXT: addu $1, $1, $6
; MIPS32-NEXT: addu $5, $1, $5
; MIPS32-NEXT: addu $10, $10, $12
; MIPS32-NEXT: sltu $12, $10, $12
; MIPS32-NEXT: andi $12, $12, 1
; MIPS32-NEXT: addu $11, $11, $12
; MIPS32-NEXT: mul $12, $3, $4
; MIPS32-NEXT: mul $13, $2, $5
; MIPS32-NEXT: mul $14, $1, $6
; MIPS32-NEXT: multu $2, $4
; MIPS32-NEXT: mfhi $15
; MIPS32-NEXT: multu $1, $5
; MIPS32-NEXT: mfhi $24
; MIPS32-NEXT: addu $12, $12, $13
; MIPS32-NEXT: sltu $13, $12, $13
; MIPS32-NEXT: andi $13, $13, 1
; MIPS32-NEXT: addu $12, $12, $14
; MIPS32-NEXT: sltu $14, $12, $14
; MIPS32-NEXT: andi $14, $14, 1
; MIPS32-NEXT: addu $13, $13, $14
; MIPS32-NEXT: addu $12, $12, $15
; MIPS32-NEXT: sltu $14, $12, $15
; MIPS32-NEXT: andi $14, $14, 1
; MIPS32-NEXT: addu $13, $13, $14
; MIPS32-NEXT: addu $12, $12, $24
; MIPS32-NEXT: sltu $14, $12, $24
; MIPS32-NEXT: andi $14, $14, 1
; MIPS32-NEXT: addu $13, $13, $14
; MIPS32-NEXT: addu $12, $12, $11
; MIPS32-NEXT: sltu $11, $12, $11
; MIPS32-NEXT: andi $11, $11, 1
; MIPS32-NEXT: addu $11, $13, $11
; MIPS32-NEXT: mul $8, $8, $4
; MIPS32-NEXT: mul $13, $3, $5
; MIPS32-NEXT: mul $14, $2, $6
; MIPS32-NEXT: mul $7, $1, $7
; MIPS32-NEXT: multu $3, $4
; MIPS32-NEXT: mfhi $3
; MIPS32-NEXT: multu $2, $5
; MIPS32-NEXT: mfhi $2
; MIPS32-NEXT: multu $1, $6
; MIPS32-NEXT: mfhi $1
; MIPS32-NEXT: addu $4, $8, $13
; MIPS32-NEXT: addu $4, $4, $14
; MIPS32-NEXT: addu $4, $4, $7
; MIPS32-NEXT: addu $3, $4, $3
; MIPS32-NEXT: addu $2, $3, $2
; MIPS32-NEXT: addu $1, $2, $1
; MIPS32-NEXT: addu $5, $1, $11
; MIPS32-NEXT: move $2, $9
; MIPS32-NEXT: move $3, $10
; MIPS32-NEXT: move $4, $12
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:

24
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/mul_vec.ll
View File

@ -4,9 +4,9 @@
define void @mul_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
; P5600-LABEL: mul_v16i8:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.b $w1, 0($4)
; P5600-NEXT: ld.b $w0, 0($5)
; P5600-NEXT: mulv.b $w0, $w0, $w1
; P5600-NEXT: ld.b $w0, 0($4)
; P5600-NEXT: ld.b $w1, 0($5)
; P5600-NEXT: mulv.b $w0, $w1, $w0
; P5600-NEXT: st.b $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
@ -21,9 +21,9 @@ entry:
define void @mul_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
; P5600-LABEL: mul_v8i16:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.h $w1, 0($4)
; P5600-NEXT: ld.h $w0, 0($5)
; P5600-NEXT: mulv.h $w0, $w0, $w1
; P5600-NEXT: ld.h $w0, 0($4)
; P5600-NEXT: ld.h $w1, 0($5)
; P5600-NEXT: mulv.h $w0, $w1, $w0
; P5600-NEXT: st.h $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
@ -38,9 +38,9 @@ entry:
define void @mul_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
; P5600-LABEL: mul_v4i32:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.w $w1, 0($4)
; P5600-NEXT: ld.w $w0, 0($5)
; P5600-NEXT: mulv.w $w0, $w0, $w1
; P5600-NEXT: ld.w $w0, 0($4)
; P5600-NEXT: ld.w $w1, 0($5)
; P5600-NEXT: mulv.w $w0, $w1, $w0
; P5600-NEXT: st.w $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
@ -55,9 +55,9 @@ entry:
define void @mul_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
; P5600-LABEL: mul_v2i64:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.d $w1, 0($4)
; P5600-NEXT: ld.d $w0, 0($5)
; P5600-NEXT: mulv.d $w0, $w0, $w1
; P5600-NEXT: ld.d $w0, 0($4)
; P5600-NEXT: ld.d $w1, 0($5)
; P5600-NEXT: mulv.d $w0, $w1, $w0
; P5600-NEXT: st.d $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop

117
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/phi.ll
View File

@ -6,24 +6,25 @@ define i1 @phi_i1(i1 %cnd, i1 %a, i1 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: .cfi_def_cfa_offset 16
; MIPS32-NEXT: sw $5, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB0_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB0_3
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_2: # %cond.true
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB0_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_3: # %cond.false
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB0_4: # %cond.end
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: addiu $sp, $sp, 16
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@ -46,24 +47,25 @@ define i8 @phi_i8(i1 %cnd, i8 %a, i8 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: .cfi_def_cfa_offset 16
; MIPS32-NEXT: sw $5, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB1_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB1_3
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_2: # %cond.true
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB1_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_3: # %cond.false
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB1_4: # %cond.end
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: addiu $sp, $sp, 16
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@ -86,24 +88,25 @@ define i16 @phi_i16(i1 %cnd, i16 %a, i16 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: .cfi_def_cfa_offset 16
; MIPS32-NEXT: sw $5, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB2_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB2_3
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_2: # %cond.true
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB2_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB2_3: # %cond.false
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB2_4: # %cond.end
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: addiu $sp, $sp, 16
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@ -126,24 +129,25 @@ define i32 @phi_i32(i1 %cnd, i32 %a, i32 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: .cfi_def_cfa_offset 16
; MIPS32-NEXT: sw $5, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB3_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB3_3
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_2: # %cond.true
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB3_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB3_3: # %cond.false
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB3_4: # %cond.end
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: addiu $sp, $sp, 16
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@ -166,35 +170,36 @@ define i64 @phi_i64(i1 %cnd, i64 %a, i64 %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 40
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: sw $1, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 44
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: addiu $2, $sp, 44
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: andi $3, $4, 1
; MIPS32-NEXT: sw $1, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: bnez $1, $BB4_2
; MIPS32-NEXT: sw $6, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $3, $BB4_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB4_3
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB4_2: # %cond.true
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $2, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB4_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB4_3: # %cond.false
; MIPS32-NEXT: lw $1, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $2, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB4_4: # %cond.end
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: move $3, $1
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
@ -217,12 +222,12 @@ define void @phi_ambiguous_i64_in_fpr(i1 %cnd, i64* %i64_ptr_a, i64* %i64_ptr_b,
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -32
; MIPS32-NEXT: .cfi_def_cfa_offset 32
; MIPS32-NEXT: sw $7, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ldc1 $f0, 0($5)
; MIPS32-NEXT: sdc1 $f0, 16($sp) # 8-byte Folded Spill
; MIPS32-NEXT: ldc1 $f0, 0($6)
; MIPS32-NEXT: sdc1 $f0, 24($sp) # 8-byte Folded Spill
; MIPS32-NEXT: ldc1 $f2, 0($6)
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: sw $7, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sdc1 $f0, 16($sp) # 8-byte Folded Spill
; MIPS32-NEXT: sdc1 $f2, 8($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB5_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
@ -234,11 +239,11 @@ define void @phi_ambiguous_i64_in_fpr(i1 %cnd, i64* %i64_ptr_a, i64* %i64_ptr_b,
; MIPS32-NEXT: j $BB5_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB5_3: # %cond.false
; MIPS32-NEXT: ldc1 $f0, 24($sp) # 8-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 8($sp) # 8-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
; MIPS32-NEXT: $BB5_4: # %cond.end
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 0($sp) # 8-byte Folded Reload
; MIPS32-NEXT: lw $1, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
@ -265,21 +270,21 @@ define float @phi_float(i1 %cnd, float %a, float %b) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: .cfi_def_cfa_offset 16
; MIPS32-NEXT: sw $5, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: sw $5, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB6_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB6_3
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB6_2: # %cond.true
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB6_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB6_3: # %cond.false
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB6_4: # %cond.end
; MIPS32-NEXT: lw $1, 4($sp) # 4-byte Folded Reload
@ -306,28 +311,28 @@ define void @phi_ambiguous_float_in_gpr(i1 %cnd, float* %f32_ptr_a, float* %f32_
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: .cfi_def_cfa_offset 16
; MIPS32-NEXT: sw $7, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 0($5)
; MIPS32-NEXT: sw $1, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: lw $1, 0($6)
; MIPS32-NEXT: lw $2, 0($6)
; MIPS32-NEXT: andi $3, $4, 1
; MIPS32-NEXT: sw $1, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: bnez $1, $BB7_2
; MIPS32-NEXT: sw $7, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $3, $BB7_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB7_3
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB7_2: # %cond.true
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: j $BB7_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB7_3: # %cond.false
; MIPS32-NEXT: lw $1, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: $BB7_4: # %cond.end
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $1, 0($2)
; MIPS32-NEXT: addiu $sp, $sp, 16
; MIPS32-NEXT: jr $ra
@ -354,23 +359,23 @@ define double @phi_double(double %a, double %b, i1 %cnd) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -24
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sdc1 $f12, 8($sp) # 8-byte Folded Spill
; MIPS32-NEXT: sdc1 $f14, 16($sp) # 8-byte Folded Spill
; MIPS32-NEXT: addiu $1, $sp, 40
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: sdc1 $f12, 16($sp) # 8-byte Folded Spill
; MIPS32-NEXT: sdc1 $f14, 8($sp) # 8-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB8_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1: # %entry
; MIPS32-NEXT: j $BB8_3
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB8_2: # %cond.true
; MIPS32-NEXT: ldc1 $f0, 8($sp) # 8-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 16($sp) # 8-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
; MIPS32-NEXT: j $BB8_4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB8_3: # %cond.false
; MIPS32-NEXT: ldc1 $f0, 16($sp) # 8-byte Folded Reload
; MIPS32-NEXT: ldc1 $f0, 8($sp) # 8-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($sp) # 8-byte Folded Spill
; MIPS32-NEXT: $BB8_4: # %cond.end
; MIPS32-NEXT: ldc1 $f0, 0($sp) # 8-byte Folded Reload

96
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/rem_and_div.ll
View File

@ -6,11 +6,11 @@ define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) {
; MIPS32-LABEL: sdiv_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sll $1, $5, 24
; MIPS32-NEXT: sra $2, $1, 24
; MIPS32-NEXT: sll $1, $4, 24
; MIPS32-NEXT: sra $1, $1, 24
; MIPS32-NEXT: div $zero, $2, $1
; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: sll $2, $4, 24
; MIPS32-NEXT: sra $2, $2, 24
; MIPS32-NEXT: div $zero, $1, $2
; MIPS32-NEXT: teq $2, $zero, 7
; MIPS32-NEXT: mflo $1
; MIPS32-NEXT: sll $1, $1, 24
; MIPS32-NEXT: sra $2, $1, 24
@ -25,11 +25,11 @@ define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) {
; MIPS32-LABEL: sdiv_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sll $1, $5, 16
; MIPS32-NEXT: sra $2, $1, 16
; MIPS32-NEXT: sll $1, $4, 16
; MIPS32-NEXT: sra $1, $1, 16
; MIPS32-NEXT: div $zero, $2, $1
; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: sll $2, $4, 16
; MIPS32-NEXT: sra $2, $2, 16
; MIPS32-NEXT: div $zero, $1, $2
; MIPS32-NEXT: teq $2, $zero, 7
; MIPS32-NEXT: mflo $1
; MIPS32-NEXT: sll $1, $1, 16
; MIPS32-NEXT: sra $2, $1, 16
@ -60,12 +60,12 @@ define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) {
; MIPS32-NEXT: .cfi_def_cfa_offset 32
; MIPS32-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: sw $4, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $4, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $4, $6
; MIPS32-NEXT: lw $6, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $5, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $5, $7
; MIPS32-NEXT: lw $7, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $6, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $7, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: jal __divdi3
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 28($sp) # 4-byte Folded Reload
@ -82,11 +82,11 @@ define signext i8 @srem_i8(i8 signext %a, i8 signext %b) {
; MIPS32-LABEL: srem_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sll $1, $5, 24
; MIPS32-NEXT: sra $2, $1, 24
; MIPS32-NEXT: sll $1, $4, 24
; MIPS32-NEXT: sra $1, $1, 24
; MIPS32-NEXT: div $zero, $2, $1
; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: sll $2, $4, 24
; MIPS32-NEXT: sra $2, $2, 24
; MIPS32-NEXT: div $zero, $1, $2
; MIPS32-NEXT: teq $2, $zero, 7
; MIPS32-NEXT: mflo $1
; MIPS32-NEXT: sll $1, $1, 24
; MIPS32-NEXT: sra $2, $1, 24
@ -101,11 +101,11 @@ define signext i16 @srem_i16(i16 signext %a, i16 signext %b) {
; MIPS32-LABEL: srem_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sll $1, $5, 16
; MIPS32-NEXT: sra $2, $1, 16
; MIPS32-NEXT: sll $1, $4, 16
; MIPS32-NEXT: sra $1, $1, 16
; MIPS32-NEXT: div $zero, $2, $1
; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: sll $2, $4, 16
; MIPS32-NEXT: sra $2, $2, 16
; MIPS32-NEXT: div $zero, $1, $2
; MIPS32-NEXT: teq $2, $zero, 7
; MIPS32-NEXT: mfhi $1
; MIPS32-NEXT: sll $1, $1, 16
; MIPS32-NEXT: sra $2, $1, 16
@ -136,12 +136,12 @@ define signext i64 @srem_i64(i64 signext %a, i64 signext %b) {
; MIPS32-NEXT: .cfi_def_cfa_offset 32
; MIPS32-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: sw $4, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $4, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $4, $6
; MIPS32-NEXT: lw $6, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $5, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $5, $7
; MIPS32-NEXT: lw $7, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $6, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $7, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: jal __moddi3
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 28($sp) # 4-byte Folded Reload
@ -157,10 +157,10 @@ entry:
define signext i8 @udiv_i8(i8 signext %a, i8 signext %b) {
; MIPS32-LABEL: udiv_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: andi $2, $5, 255
; MIPS32-NEXT: andi $1, $4, 255
; MIPS32-NEXT: divu $zero, $2, $1
; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: andi $1, $5, 255
; MIPS32-NEXT: andi $2, $4, 255
; MIPS32-NEXT: divu $zero, $1, $2
; MIPS32-NEXT: teq $2, $zero, 7
; MIPS32-NEXT: mflo $1
; MIPS32-NEXT: sll $1, $1, 24
; MIPS32-NEXT: sra $2, $1, 24
@ -174,10 +174,10 @@ entry:
define signext i16 @udiv_i16(i16 signext %a, i16 signext %b) {
; MIPS32-LABEL: udiv_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: andi $2, $5, 65535
; MIPS32-NEXT: andi $1, $4, 65535
; MIPS32-NEXT: divu $zero, $2, $1
; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: andi $1, $5, 65535
; MIPS32-NEXT: andi $2, $4, 65535
; MIPS32-NEXT: divu $zero, $1, $2
; MIPS32-NEXT: teq $2, $zero, 7
; MIPS32-NEXT: mflo $1
; MIPS32-NEXT: sll $1, $1, 16
; MIPS32-NEXT: sra $2, $1, 16
@ -208,12 +208,12 @@ define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) {
; MIPS32-NEXT: .cfi_def_cfa_offset 32
; MIPS32-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: sw $4, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $4, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $4, $6
; MIPS32-NEXT: lw $6, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $5, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $5, $7
; MIPS32-NEXT: lw $7, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $6, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $7, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: jal __udivdi3
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 28($sp) # 4-byte Folded Reload
@ -229,10 +229,10 @@ entry:
define signext i8 @urem_i8(i8 signext %a, i8 signext %b) {
; MIPS32-LABEL: urem_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: andi $2, $5, 255
; MIPS32-NEXT: andi $1, $4, 255
; MIPS32-NEXT: divu $zero, $2, $1
; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: andi $1, $5, 255
; MIPS32-NEXT: andi $2, $4, 255
; MIPS32-NEXT: divu $zero, $1, $2
; MIPS32-NEXT: teq $2, $zero, 7
; MIPS32-NEXT: mfhi $1
; MIPS32-NEXT: sll $1, $1, 24
; MIPS32-NEXT: sra $2, $1, 24
@ -246,10 +246,10 @@ entry:
define signext i16 @urem_i16(i16 signext %a, i16 signext %b) {
; MIPS32-LABEL: urem_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: andi $2, $5, 65535
; MIPS32-NEXT: andi $1, $4, 65535
; MIPS32-NEXT: divu $zero, $2, $1
; MIPS32-NEXT: teq $1, $zero, 7
; MIPS32-NEXT: andi $1, $5, 65535
; MIPS32-NEXT: andi $2, $4, 65535
; MIPS32-NEXT: divu $zero, $1, $2
; MIPS32-NEXT: teq $2, $zero, 7
; MIPS32-NEXT: mfhi $1
; MIPS32-NEXT: sll $1, $1, 16
; MIPS32-NEXT: sra $2, $1, 16
@ -280,12 +280,12 @@ define signext i64 @urem_i64(i64 signext %a, i64 signext %b) {
; MIPS32-NEXT: .cfi_def_cfa_offset 32
; MIPS32-NEXT: sw $ra, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: sw $4, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $4, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $4, $6
; MIPS32-NEXT: lw $6, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $5, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $5, $7
; MIPS32-NEXT: lw $7, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $6, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $7, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: jal __umoddi3
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 28($sp) # 4-byte Folded Reload

73
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/select.ll
View File

@ -4,9 +4,9 @@
define i8 @select_i8(i1 %test, i8 %a, i8 %b) {
; MIPS32-LABEL: select_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $2, $6
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: movn $2, $5, $1
; MIPS32-NEXT: movn $6, $5, $1
; MIPS32-NEXT: move $2, $6
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -17,9 +17,9 @@ entry:
define i16 @select_i16(i1 %test, i16 %a, i16 %b) {
; MIPS32-LABEL: select_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $2, $6
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: movn $2, $5, $1
; MIPS32-NEXT: movn $6, $5, $1
; MIPS32-NEXT: move $2, $6
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -30,9 +30,9 @@ entry:
define i32 @select_i32(i1 %test, i32 %a, i32 %b) {
; MIPS32-LABEL: select_i32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $2, $6
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: movn $2, $5, $1
; MIPS32-NEXT: movn $6, $5, $1
; MIPS32-NEXT: move $2, $6
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -43,9 +43,9 @@ entry:
define i32* @select_ptr(i1 %test, i32* %a, i32* %b) {
; MIPS32-LABEL: select_ptr:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $2, $6
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: movn $2, $5, $1
; MIPS32-NEXT: movn $6, $5, $1
; MIPS32-NEXT: move $2, $6
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -56,12 +56,12 @@ entry:
define i32 @select_with_negation(i32 %a, i32 %b, i32 %x, i32 %y) {
; MIPS32-LABEL: select_with_negation:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $2, $7
; MIPS32-NEXT: ori $3, $zero, 1
; MIPS32-NEXT: slt $1, $4, $5
; MIPS32-NEXT: xor $1, $1, $3
; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: slt $2, $4, $5
; MIPS32-NEXT: xor $1, $2, $1
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn $2, $6, $1
; MIPS32-NEXT: movn $7, $6, $1
; MIPS32-NEXT: move $2, $7
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -74,13 +74,19 @@ entry:
define i64 @select_i64(i1 %test, i64 %a, i64 %b) {
; MIPS32-LABEL: select_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $1, $sp, 16
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 20
; MIPS32-NEXT: lw $3, 0($1)
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: movn $2, $6, $1
; MIPS32-NEXT: movn $3, $7, $1
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: addiu $1, $sp, 24
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: addiu $2, $sp, 28
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: andi $3, $4, 1
; MIPS32-NEXT: movn $1, $6, $3
; MIPS32-NEXT: movn $2, $7, $3
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -91,11 +97,11 @@ entry:
define void @select_ambiguous_i64_in_fpr(i1 %test, i64* %i64_ptr_a, i64* %i64_ptr_b, i64* %i64_ptr_c) {
; MIPS32-LABEL: select_ambiguous_i64_in_fpr:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ldc1 $f2, 0($5)
; MIPS32-NEXT: ldc1 $f0, 0($6)
; MIPS32-NEXT: ldc1 $f0, 0($5)
; MIPS32-NEXT: ldc1 $f2, 0($6)
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: movn.d $f0, $f2, $1
; MIPS32-NEXT: sdc1 $f0, 0($7)
; MIPS32-NEXT: movn.d $f2, $f0, $1
; MIPS32-NEXT: sdc1 $f2, 0($7)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -110,9 +116,10 @@ define float @select_float(i1 %test, float %a, float %b) {
; MIPS32-LABEL: select_float:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: mtc1 $5, $f1
; MIPS32-NEXT: mtc1 $6, $f0
; MIPS32-NEXT: movn.s $f0, $f1, $1
; MIPS32-NEXT: mtc1 $5, $f0
; MIPS32-NEXT: mtc1 $6, $f1
; MIPS32-NEXT: movn.s $f1, $f0, $1
; MIPS32-NEXT: mov.s $f0, $f1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -123,11 +130,11 @@ entry:
define void @select_ambiguous_float_in_gpr(i1 %test, float* %f32_ptr_a, float* %f32_ptr_b, float* %f32_ptr_c) {
; MIPS32-LABEL: select_ambiguous_float_in_gpr:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lw $2, 0($5)
; MIPS32-NEXT: lw $1, 0($6)
; MIPS32-NEXT: lw $1, 0($5)
; MIPS32-NEXT: lw $2, 0($6)
; MIPS32-NEXT: andi $3, $4, 1
; MIPS32-NEXT: movn $1, $2, $3
; MIPS32-NEXT: sw $1, 0($7)
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: sw $2, 0($7)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -141,11 +148,11 @@ entry:
define double @select_double(double %a, double %b, i1 %test) {
; MIPS32-LABEL: select_double:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: mov.d $f0, $f14
; MIPS32-NEXT: addiu $1, $sp, 16
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn.d $f0, $f12, $1
; MIPS32-NEXT: movn.d $f14, $f12, $1
; MIPS32-NEXT: mov.d $f0, $f14
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:

96
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sitofp_and_uitofp.ll
View File

@ -143,10 +143,10 @@ define float @u32tof32(i32 zeroext %a) {
; FP32-NEXT: lui $1, 17200
; FP32-NEXT: mtc1 $4, $f0
; FP32-NEXT: mtc1 $1, $f1
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f2
; FP32-NEXT: mtc1 $2, $f3
; FP32-NEXT: lui $1, 17200
; FP32-NEXT: ori $2, $zero, 0
; FP32-NEXT: mtc1 $2, $f2
; FP32-NEXT: mtc1 $1, $f3
; FP32-NEXT: sub.d $f0, $f0, $f2
; FP32-NEXT: cvt.s.d $f0, $f0
; FP32-NEXT: jr $ra
@ -157,10 +157,10 @@ define float @u32tof32(i32 zeroext %a) {
; FP64-NEXT: lui $1, 17200
; FP64-NEXT: mtc1 $4, $f0
; FP64-NEXT: mthc1 $1, $f0
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f1
; FP64-NEXT: mthc1 $2, $f1
; FP64-NEXT: lui $1, 17200
; FP64-NEXT: ori $2, $zero, 0
; FP64-NEXT: mtc1 $2, $f1
; FP64-NEXT: mthc1 $1, $f1
; FP64-NEXT: sub.d $f0, $f0, $f1
; FP64-NEXT: cvt.s.d $f0, $f0
; FP64-NEXT: jr $ra
@ -177,10 +177,10 @@ define float @u16tof32(i16 zeroext %a) {
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: mtc1 $1, $f0
; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f2
; FP32-NEXT: mtc1 $2, $f3
; FP32-NEXT: lui $1, 17200
; FP32-NEXT: ori $2, $zero, 0
; FP32-NEXT: mtc1 $2, $f2
; FP32-NEXT: mtc1 $1, $f3
; FP32-NEXT: sub.d $f0, $f0, $f2
; FP32-NEXT: cvt.s.d $f0, $f0
; FP32-NEXT: jr $ra
@ -192,10 +192,10 @@ define float @u16tof32(i16 zeroext %a) {
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: mtc1 $1, $f0
; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f1
; FP64-NEXT: mthc1 $2, $f1
; FP64-NEXT: lui $1, 17200
; FP64-NEXT: ori $2, $zero, 0
; FP64-NEXT: mtc1 $2, $f1
; FP64-NEXT: mthc1 $1, $f1
; FP64-NEXT: sub.d $f0, $f0, $f1
; FP64-NEXT: cvt.s.d $f0, $f0
; FP64-NEXT: jr $ra
@ -212,10 +212,10 @@ define float @u8tof32(i8 zeroext %a) {
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: mtc1 $1, $f0
; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f2
; FP32-NEXT: mtc1 $2, $f3
; FP32-NEXT: lui $1, 17200
; FP32-NEXT: ori $2, $zero, 0
; FP32-NEXT: mtc1 $2, $f2
; FP32-NEXT: mtc1 $1, $f3
; FP32-NEXT: sub.d $f0, $f0, $f2
; FP32-NEXT: cvt.s.d $f0, $f0
; FP32-NEXT: jr $ra
@ -227,10 +227,10 @@ define float @u8tof32(i8 zeroext %a) {
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: mtc1 $1, $f0
; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f1
; FP64-NEXT: mthc1 $2, $f1
; FP64-NEXT: lui $1, 17200
; FP64-NEXT: ori $2, $zero, 0
; FP64-NEXT: mtc1 $2, $f1
; FP64-NEXT: mthc1 $1, $f1
; FP64-NEXT: sub.d $f0, $f0, $f1
; FP64-NEXT: cvt.s.d $f0, $f0
; FP64-NEXT: jr $ra
@ -264,10 +264,10 @@ define double @u32tof64(i32 zeroext %a) {
; FP32-NEXT: lui $1, 17200
; FP32-NEXT: mtc1 $4, $f0
; FP32-NEXT: mtc1 $1, $f1
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f2
; FP32-NEXT: mtc1 $2, $f3
; FP32-NEXT: lui $1, 17200
; FP32-NEXT: ori $2, $zero, 0
; FP32-NEXT: mtc1 $2, $f2
; FP32-NEXT: mtc1 $1, $f3
; FP32-NEXT: sub.d $f0, $f0, $f2
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
@ -277,10 +277,10 @@ define double @u32tof64(i32 zeroext %a) {
; FP64-NEXT: lui $1, 17200
; FP64-NEXT: mtc1 $4, $f0
; FP64-NEXT: mthc1 $1, $f0
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f1
; FP64-NEXT: mthc1 $2, $f1
; FP64-NEXT: lui $1, 17200
; FP64-NEXT: ori $2, $zero, 0
; FP64-NEXT: mtc1 $2, $f1
; FP64-NEXT: mthc1 $1, $f1
; FP64-NEXT: sub.d $f0, $f0, $f1
; FP64-NEXT: jr $ra
; FP64-NEXT: nop
@ -296,10 +296,10 @@ define double @u16tof64(i16 zeroext %a) {
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: mtc1 $1, $f0
; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f2
; FP32-NEXT: mtc1 $2, $f3
; FP32-NEXT: lui $1, 17200
; FP32-NEXT: ori $2, $zero, 0
; FP32-NEXT: mtc1 $2, $f2
; FP32-NEXT: mtc1 $1, $f3
; FP32-NEXT: sub.d $f0, $f0, $f2
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
@ -310,10 +310,10 @@ define double @u16tof64(i16 zeroext %a) {
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: mtc1 $1, $f0
; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f1
; FP64-NEXT: mthc1 $2, $f1
; FP64-NEXT: lui $1, 17200
; FP64-NEXT: ori $2, $zero, 0
; FP64-NEXT: mtc1 $2, $f1
; FP64-NEXT: mthc1 $1, $f1
; FP64-NEXT: sub.d $f0, $f0, $f1
; FP64-NEXT: jr $ra
; FP64-NEXT: nop
@ -329,10 +329,10 @@ define double @u8tof64(i8 zeroext %a) {
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: mtc1 $1, $f0
; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: lui $2, 17200
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f2
; FP32-NEXT: mtc1 $2, $f3
; FP32-NEXT: lui $1, 17200
; FP32-NEXT: ori $2, $zero, 0
; FP32-NEXT: mtc1 $2, $f2
; FP32-NEXT: mtc1 $1, $f3
; FP32-NEXT: sub.d $f0, $f0, $f2
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
@ -343,10 +343,10 @@ define double @u8tof64(i8 zeroext %a) {
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: mtc1 $1, $f0
; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: lui $2, 17200
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f1
; FP64-NEXT: mthc1 $2, $f1
; FP64-NEXT: lui $1, 17200
; FP64-NEXT: ori $2, $zero, 0
; FP64-NEXT: mtc1 $2, $f1
; FP64-NEXT: mthc1 $1, $f1
; FP64-NEXT: sub.d $f0, $f0, $f1
; FP64-NEXT: jr $ra
; FP64-NEXT: nop

16
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_4_unaligned.ll
View File

@ -15,10 +15,10 @@ define void @store_float_align1(float %a) {
; MIPS32-LABEL: store_float_align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align1)
; MIPS32-NEXT: addiu $2, $1, %lo(float_align1)
; MIPS32-NEXT: mfc1 $1, $f12
; MIPS32-NEXT: swl $1, 3($2)
; MIPS32-NEXT: swr $1, 0($2)
; MIPS32-NEXT: addiu $1, $1, %lo(float_align1)
; MIPS32-NEXT: mfc1 $2, $f12
; MIPS32-NEXT: swl $2, 3($1)
; MIPS32-NEXT: swr $2, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
@ -37,10 +37,10 @@ define void @store_float_align2(float %a) {
; MIPS32-LABEL: store_float_align2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align2)
; MIPS32-NEXT: addiu $2, $1, %lo(float_align2)
; MIPS32-NEXT: mfc1 $1, $f12
; MIPS32-NEXT: swl $1, 3($2)
; MIPS32-NEXT: swr $1, 0($2)
; MIPS32-NEXT: addiu $1, $1, %lo(float_align2)
; MIPS32-NEXT: mfc1 $2, $f12
; MIPS32-NEXT: swl $2, 3($1)
; MIPS32-NEXT: swr $2, 0($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;

96
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/store_split_because_of_memsize_or_align.ll
View File

@ -204,12 +204,12 @@ define void @store6align1(%struct.MemSize6_Align1* %S, i64 %a) {
; MIPS32-LABEL: store6align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 4
; MIPS32-NEXT: addu $2, $4, $1
; MIPS32-NEXT: addu $1, $4, $1
; MIPS32-NEXT: swl $6, 3($4)
; MIPS32-NEXT: swr $6, 0($4)
; MIPS32-NEXT: sb $7, 4($4)
; MIPS32-NEXT: srl $1, $7, 8
; MIPS32-NEXT: sb $1, 1($2)
; MIPS32-NEXT: srl $2, $7, 8
; MIPS32-NEXT: sb $2, 1($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
@ -290,25 +290,25 @@ define void @store7align1(%struct.MemSize7_Align1* %S, i64 %a) {
; MIPS32-LABEL: store7align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 4
; MIPS32-NEXT: addu $2, $4, $1
; MIPS32-NEXT: addu $1, $4, $1
; MIPS32-NEXT: swl $6, 3($4)
; MIPS32-NEXT: swr $6, 0($4)
; MIPS32-NEXT: sb $7, 4($4)
; MIPS32-NEXT: srl $1, $7, 8
; MIPS32-NEXT: sb $1, 1($2)
; MIPS32-NEXT: srl $1, $7, 16
; MIPS32-NEXT: sb $1, 2($2)
; MIPS32-NEXT: srl $2, $7, 8
; MIPS32-NEXT: sb $2, 1($1)
; MIPS32-NEXT: srl $2, $7, 16
; MIPS32-NEXT: sb $2, 2($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: store7align1:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: ori $1, $zero, 4
; MIPS32R6-NEXT: addu $2, $4, $1
; MIPS32R6-NEXT: addu $1, $4, $1
; MIPS32R6-NEXT: sw $6, 0($4)
; MIPS32R6-NEXT: sh $7, 4($4)
; MIPS32R6-NEXT: srl $1, $7, 16
; MIPS32R6-NEXT: sb $1, 2($2)
; MIPS32R6-NEXT: srl $2, $7, 16
; MIPS32R6-NEXT: sb $2, 2($1)
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize7_Align1* %S to i56*
@ -321,23 +321,23 @@ define void @store7align2(%struct.MemSize7_Align2* %S, i64 %a) {
; MIPS32-LABEL: store7align2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 4
; MIPS32-NEXT: addu $2, $4, $1
; MIPS32-NEXT: addu $1, $4, $1
; MIPS32-NEXT: swl $6, 3($4)
; MIPS32-NEXT: swr $6, 0($4)
; MIPS32-NEXT: sh $7, 4($4)
; MIPS32-NEXT: srl $1, $7, 16
; MIPS32-NEXT: sb $1, 2($2)
; MIPS32-NEXT: srl $2, $7, 16
; MIPS32-NEXT: sb $2, 2($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: store7align2:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: ori $1, $zero, 4
; MIPS32R6-NEXT: addu $2, $4, $1
; MIPS32R6-NEXT: addu $1, $4, $1
; MIPS32R6-NEXT: sw $6, 0($4)
; MIPS32R6-NEXT: sh $7, 4($4)
; MIPS32R6-NEXT: srl $1, $7, 16
; MIPS32R6-NEXT: sb $1, 2($2)
; MIPS32R6-NEXT: srl $2, $7, 16
; MIPS32R6-NEXT: sb $2, 2($1)
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize7_Align2* %S to i56*
@ -350,22 +350,22 @@ define void @store7align4(%struct.MemSize7_Align4* %S, i64 %a) {
; MIPS32-LABEL: store7align4:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 4
; MIPS32-NEXT: addu $2, $4, $1
; MIPS32-NEXT: addu $1, $4, $1
; MIPS32-NEXT: sw $6, 0($4)
; MIPS32-NEXT: sh $7, 4($4)
; MIPS32-NEXT: srl $1, $7, 16
; MIPS32-NEXT: sb $1, 2($2)
; MIPS32-NEXT: srl $2, $7, 16
; MIPS32-NEXT: sb $2, 2($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: store7align4:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: ori $1, $zero, 4
; MIPS32R6-NEXT: addu $2, $4, $1
; MIPS32R6-NEXT: addu $1, $4, $1
; MIPS32R6-NEXT: sw $6, 0($4)
; MIPS32R6-NEXT: sh $7, 4($4)
; MIPS32R6-NEXT: srl $1, $7, 16
; MIPS32R6-NEXT: sb $1, 2($2)
; MIPS32R6-NEXT: srl $2, $7, 16
; MIPS32R6-NEXT: sb $2, 2($1)
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize7_Align4* %S to i56*
@ -378,22 +378,22 @@ define void @store7align8(%struct.MemSize7_Align8* %S, i64 %a) {
; MIPS32-LABEL: store7align8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 4
; MIPS32-NEXT: addu $2, $4, $1
; MIPS32-NEXT: addu $1, $4, $1
; MIPS32-NEXT: sw $6, 0($4)
; MIPS32-NEXT: sh $7, 4($4)
; MIPS32-NEXT: srl $1, $7, 16
; MIPS32-NEXT: sb $1, 2($2)
; MIPS32-NEXT: srl $2, $7, 16
; MIPS32-NEXT: sb $2, 2($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R6-LABEL: store7align8:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: ori $1, $zero, 4
; MIPS32R6-NEXT: addu $2, $4, $1
; MIPS32R6-NEXT: addu $1, $4, $1
; MIPS32R6-NEXT: sw $6, 0($4)
; MIPS32R6-NEXT: sh $7, 4($4)
; MIPS32R6-NEXT: srl $1, $7, 16
; MIPS32R6-NEXT: sb $1, 2($2)
; MIPS32R6-NEXT: srl $2, $7, 16
; MIPS32R6-NEXT: sb $2, 2($1)
; MIPS32R6-NEXT: jrc $ra
entry:
%0 = bitcast %struct.MemSize7_Align8* %S to i56*
@ -406,13 +406,13 @@ define void @store_double_align1(double %a) {
; MIPS32-LABEL: store_double_align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(double_align1)
; MIPS32-NEXT: addiu $2, $1, %lo(double_align1)
; MIPS32-NEXT: mfc1 $3, $f12
; MIPS32-NEXT: mfc1 $1, $f13
; MIPS32-NEXT: swl $3, 3($2)
; MIPS32-NEXT: swr $3, 0($2)
; MIPS32-NEXT: swl $1, 7($2)
; MIPS32-NEXT: swr $1, 4($2)
; MIPS32-NEXT: addiu $1, $1, %lo(double_align1)
; MIPS32-NEXT: mfc1 $2, $f12
; MIPS32-NEXT: mfc1 $3, $f13
; MIPS32-NEXT: swl $2, 3($1)
; MIPS32-NEXT: swr $2, 0($1)
; MIPS32-NEXT: swl $3, 7($1)
; MIPS32-NEXT: swr $3, 4($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
@ -431,13 +431,13 @@ define void @store_double_align2(double %a) {
; MIPS32-LABEL: store_double_align2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(double_align2)
; MIPS32-NEXT: addiu $2, $1, %lo(double_align2)
; MIPS32-NEXT: mfc1 $3, $f12
; MIPS32-NEXT: mfc1 $1, $f13
; MIPS32-NEXT: swl $3, 3($2)
; MIPS32-NEXT: swr $3, 0($2)
; MIPS32-NEXT: swl $1, 7($2)
; MIPS32-NEXT: swr $1, 4($2)
; MIPS32-NEXT: addiu $1, $1, %lo(double_align2)
; MIPS32-NEXT: mfc1 $2, $f12
; MIPS32-NEXT: mfc1 $3, $f13
; MIPS32-NEXT: swl $2, 3($1)
; MIPS32-NEXT: swr $2, 0($1)
; MIPS32-NEXT: swl $3, 7($1)
; MIPS32-NEXT: swr $3, 4($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
@ -456,11 +456,11 @@ define void @store_double_align4(double %a) {
; MIPS32-LABEL: store_double_align4:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(double_align4)
; MIPS32-NEXT: addiu $2, $1, %lo(double_align4)
; MIPS32-NEXT: mfc1 $3, $f12
; MIPS32-NEXT: mfc1 $1, $f13
; MIPS32-NEXT: sw $3, 0($2)
; MIPS32-NEXT: sw $1, 4($2)
; MIPS32-NEXT: addiu $1, $1, %lo(double_align4)
; MIPS32-NEXT: mfc1 $2, $f12
; MIPS32-NEXT: mfc1 $3, $f13
; MIPS32-NEXT: sw $2, 0($1)
; MIPS32-NEXT: sw $3, 4($1)
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;

65
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub.ll
View File

@ -88,10 +88,10 @@ define i64 @sub_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: sub_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: subu $2, $6, $4
; MIPS32-NEXT: sltu $3, $6, $4
; MIPS32-NEXT: subu $1, $7, $5
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: subu $3, $1, $3
; MIPS32-NEXT: sltu $1, $6, $4
; MIPS32-NEXT: subu $3, $7, $5
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: subu $3, $3, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -102,37 +102,38 @@ entry:
define i128 @sub_i128(i128 %a, i128 %b) {
; MIPS32-LABEL: sub_i128:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $10, $5
; MIPS32-NEXT: move $9, $6
; MIPS32-NEXT: addiu $1, $sp, 16
; MIPS32-NEXT: lw $3, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 20
; MIPS32-NEXT: lw $6, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 24
; MIPS32-NEXT: lw $5, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 28
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: subu $2, $3, $4
; MIPS32-NEXT: sltu $4, $3, $4
; MIPS32-NEXT: subu $3, $6, $10
; MIPS32-NEXT: andi $8, $4, 1
; MIPS32-NEXT: subu $3, $3, $8
; MIPS32-NEXT: xor $8, $6, $10
; MIPS32-NEXT: sltiu $8, $8, 1
; MIPS32-NEXT: sltu $6, $6, $10
; MIPS32-NEXT: andi $8, $8, 1
; MIPS32-NEXT: movn $6, $4, $8
; MIPS32-NEXT: subu $4, $5, $9
; MIPS32-NEXT: andi $8, $6, 1
; MIPS32-NEXT: subu $4, $4, $8
; MIPS32-NEXT: xor $8, $5, $9
; MIPS32-NEXT: sltiu $8, $8, 1
; MIPS32-NEXT: sltu $5, $5, $9
; MIPS32-NEXT: andi $8, $8, 1
; MIPS32-NEXT: movn $5, $6, $8
; MIPS32-NEXT: subu $1, $1, $7
; MIPS32-NEXT: addiu $2, $sp, 20
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: addiu $3, $sp, 24
; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: addiu $8, $sp, 28
; MIPS32-NEXT: lw $8, 0($8)
; MIPS32-NEXT: subu $9, $1, $4
; MIPS32-NEXT: sltu $1, $1, $4
; MIPS32-NEXT: subu $4, $2, $5
; MIPS32-NEXT: andi $10, $1, 1
; MIPS32-NEXT: subu $4, $4, $10
; MIPS32-NEXT: xor $10, $2, $5
; MIPS32-NEXT: sltiu $10, $10, 1
; MIPS32-NEXT: sltu $2, $2, $5
; MIPS32-NEXT: andi $5, $10, 1
; MIPS32-NEXT: movn $2, $1, $5
; MIPS32-NEXT: subu $1, $3, $6
; MIPS32-NEXT: andi $5, $2, 1
; MIPS32-NEXT: subu $1, $1, $5
; MIPS32-NEXT: xor $5, $3, $6
; MIPS32-NEXT: sltiu $5, $5, 1
; MIPS32-NEXT: sltu $3, $3, $6
; MIPS32-NEXT: andi $5, $5, 1
; MIPS32-NEXT: subu $5, $1, $5
; MIPS32-NEXT: movn $3, $2, $5
; MIPS32-NEXT: subu $2, $8, $7
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: subu $5, $2, $3
; MIPS32-NEXT: move $2, $9
; MIPS32-NEXT: move $3, $4
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:

24
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/sub_vec.ll
View File

@ -4,9 +4,9 @@
define void @sub_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
; P5600-LABEL: sub_v16i8:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.b $w1, 0($4)
; P5600-NEXT: ld.b $w0, 0($5)
; P5600-NEXT: subv.b $w0, $w0, $w1
; P5600-NEXT: ld.b $w0, 0($4)
; P5600-NEXT: ld.b $w1, 0($5)
; P5600-NEXT: subv.b $w0, $w1, $w0
; P5600-NEXT: st.b $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
@ -21,9 +21,9 @@ entry:
define void @sub_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
; P5600-LABEL: sub_v8i16:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.h $w1, 0($4)
; P5600-NEXT: ld.h $w0, 0($5)
; P5600-NEXT: subv.h $w0, $w0, $w1
; P5600-NEXT: ld.h $w0, 0($4)
; P5600-NEXT: ld.h $w1, 0($5)
; P5600-NEXT: subv.h $w0, $w1, $w0
; P5600-NEXT: st.h $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
@ -38,9 +38,9 @@ entry:
define void @sub_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
; P5600-LABEL: sub_v4i32:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.w $w1, 0($4)
; P5600-NEXT: ld.w $w0, 0($5)
; P5600-NEXT: subv.w $w0, $w0, $w1
; P5600-NEXT: ld.w $w0, 0($4)
; P5600-NEXT: ld.w $w1, 0($5)
; P5600-NEXT: subv.w $w0, $w1, $w0
; P5600-NEXT: st.w $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
@ -55,9 +55,9 @@ entry:
define void @sub_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
; P5600-LABEL: sub_v2i64:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.d $w1, 0($4)
; P5600-NEXT: ld.d $w0, 0($5)
; P5600-NEXT: subv.d $w0, $w0, $w1
; P5600-NEXT: ld.d $w0, 0($4)
; P5600-NEXT: ld.d $w1, 0($5)
; P5600-NEXT: subv.d $w0, $w1, $w0
; P5600-NEXT: st.d $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop

25
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/test_TypeInfoforMF.ll
View File

@ -26,9 +26,9 @@ entry:
define i32 @outgoing_gpr_instr(i32* %i32_ptr1, i32* %i32_ptr2) {
; MIPS32-LABEL: outgoing_gpr_instr:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lw $2, 0($4)
; MIPS32-NEXT: lw $1, 0($5)
; MIPS32-NEXT: addu $2, $1, $2
; MIPS32-NEXT: lw $1, 0($4)
; MIPS32-NEXT: lw $2, 0($5)
; MIPS32-NEXT: addu $2, $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -56,10 +56,10 @@ entry:
define i32 @incoming_gpr(i32 %incoming_phys_reg, i1 %test, i32* %a) {
; MIPS32-LABEL: incoming_gpr:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $2, $4
; MIPS32-NEXT: lw $1, 0($6)
; MIPS32-NEXT: andi $3, $5, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: andi $2, $5, 1
; MIPS32-NEXT: movn $4, $1, $2
; MIPS32-NEXT: move $2, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -71,10 +71,10 @@ entry:
define float @incoming_fpr(float %incoming_phys_reg, i1 %test, float* %a) {
; MIPS32-LABEL: incoming_fpr:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: mov.s $f0, $f12
; MIPS32-NEXT: lwc1 $f1, 0($6)
; MIPS32-NEXT: lwc1 $f0, 0($6)
; MIPS32-NEXT: andi $1, $5, 1
; MIPS32-NEXT: movn.s $f0, $f1, $1
; MIPS32-NEXT: movn.s $f12, $f0, $1
; MIPS32-NEXT: mov.s $f0, $f12
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -103,10 +103,11 @@ entry:
define float @incoming_float_instr(float %val1, float %val2, float* %float_ptr, i1 %test) {
; MIPS32-LABEL: incoming_float_instr:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lwc1 $f1, 0($6)
; MIPS32-NEXT: add.s $f0, $f14, $f12
; MIPS32-NEXT: lwc1 $f0, 0($6)
; MIPS32-NEXT: add.s $f1, $f14, $f12
; MIPS32-NEXT: andi $1, $7, 1
; MIPS32-NEXT: movn.s $f0, $f1, $1
; MIPS32-NEXT: movn.s $f1, $f0, $1
; MIPS32-NEXT: mov.s $f0, $f1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:

22
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/var_arg.ll
View File

@ -13,7 +13,6 @@ define void @testVaCopyArg(i8* %fmt, ...) {
; MIPS32-NEXT: .cfi_def_cfa_offset 40
; MIPS32-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: move $3, $4
; MIPS32-NEXT: addiu $1, $sp, 44
; MIPS32-NEXT: sw $5, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 48
@ -21,23 +20,24 @@ define void @testVaCopyArg(i8* %fmt, ...) {
; MIPS32-NEXT: addiu $1, $sp, 52
; MIPS32-NEXT: sw $7, 0($1)
; MIPS32-NEXT: lui $1, %hi($.str)
; MIPS32-NEXT: addiu $4, $1, %lo($.str)
; MIPS32-NEXT: addiu $6, $sp, 32
; MIPS32-NEXT: addiu $2, $sp, 28
; MIPS32-NEXT: addiu $1, $1, %lo($.str)
; MIPS32-NEXT: addiu $2, $sp, 32
; MIPS32-NEXT: addiu $3, $sp, 28
; MIPS32-NEXT: addiu $5, $sp, 24
; MIPS32-NEXT: addiu $1, $sp, 20
; MIPS32-NEXT: sw $3, 0($6)
; MIPS32-NEXT: addiu $3, $sp, 44
; MIPS32-NEXT: sw $3, 0($2)
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: addiu $6, $sp, 20
; MIPS32-NEXT: sw $4, 0($2)
; MIPS32-NEXT: addiu $2, $sp, 44
; MIPS32-NEXT: sw $2, 0($3)
; MIPS32-NEXT: lw $2, 0($3)
; MIPS32-NEXT: sw $2, 0($5)
; MIPS32-NEXT: lw $2, 0($5)
; MIPS32-NEXT: ori $3, $zero, 4
; MIPS32-NEXT: addu $3, $2, $3
; MIPS32-NEXT: sw $3, 0($5)
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: sw $2, 0($1)
; MIPS32-NEXT: lw $5, 0($1)
; MIPS32-NEXT: sw $2, 0($6)
; MIPS32-NEXT: lw $5, 0($6)
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: jal printf
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload

5
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zextLoad_and_sextLoad.ll
View File

@ -113,8 +113,9 @@ entry:
define i64 @load4_s32_to_sextLoad4_s64(i32* %px) {
; MIPS32-LABEL: load4_s32_to_sextLoad4_s64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lw $2, 0($4)
; MIPS32-NEXT: sra $3, $2, 31
; MIPS32-NEXT: lw $1, 0($4)
; MIPS32-NEXT: sra $3, $1, 31
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:

4
llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll
View File

@ -4,8 +4,8 @@
define i64 @zext(i32 %x) {
; MIPS32-LABEL: zext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $2, $4
; MIPS32-NEXT: ori $3, $zero, 0
; MIPS32-NEXT: move $2, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
@ -16,8 +16,8 @@ entry:
define i64 @sext(i32 %x) {
; MIPS32-LABEL: sext:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sra $3, $4, 31
; MIPS32-NEXT: move $2, $4
; MIPS32-NEXT: sra $3, $2, 31
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:

4704
llvm/test/CodeGen/Mips/atomic-min-max.ll
View File

File diff suppressed because it is too large Load Diff

1537
llvm/test/CodeGen/Mips/atomic.ll
View File

File diff suppressed because it is too large Load Diff

90
llvm/test/CodeGen/Mips/atomic64.ll
View File

@ -95,13 +95,13 @@ define i64 @AtomicLoadAdd(i64 signext %incr) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadAdd)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAdd)))
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB0_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
; MIPS64R6O0-NEXT: lld $2, 0($3)
; MIPS64R6O0-NEXT: daddu $1, $2, $4
; MIPS64R6O0-NEXT: scd $1, 0($3)
; MIPS64R6O0-NEXT: beqzc $1, .LBB0_1
; MIPS64R6O0-NEXT: lld $2, 0($1)
; MIPS64R6O0-NEXT: daddu $3, $2, $4
; MIPS64R6O0-NEXT: scd $3, 0($1)
; MIPS64R6O0-NEXT: beqzc $3, .LBB0_1
; MIPS64R6O0-NEXT: nop
; MIPS64R6O0-NEXT: # %bb.2: # %entry
; MIPS64R6O0-NEXT: jrc $ra
@ -252,13 +252,13 @@ define i64 @AtomicLoadSub(i64 signext %incr) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadSub)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadSub)))
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB1_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
; MIPS64R6O0-NEXT: lld $2, 0($3)
; MIPS64R6O0-NEXT: dsubu $1, $2, $4
; MIPS64R6O0-NEXT: scd $1, 0($3)
; MIPS64R6O0-NEXT: beqzc $1, .LBB1_1
; MIPS64R6O0-NEXT: lld $2, 0($1)
; MIPS64R6O0-NEXT: dsubu $3, $2, $4
; MIPS64R6O0-NEXT: scd $3, 0($1)
; MIPS64R6O0-NEXT: beqzc $3, .LBB1_1
; MIPS64R6O0-NEXT: nop
; MIPS64R6O0-NEXT: # %bb.2: # %entry
; MIPS64R6O0-NEXT: jrc $ra
@ -409,13 +409,13 @@ define i64 @AtomicLoadAnd(i64 signext %incr) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadAnd)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadAnd)))
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB2_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
; MIPS64R6O0-NEXT: lld $2, 0($3)
; MIPS64R6O0-NEXT: and $1, $2, $4
; MIPS64R6O0-NEXT: scd $1, 0($3)
; MIPS64R6O0-NEXT: beqzc $1, .LBB2_1
; MIPS64R6O0-NEXT: lld $2, 0($1)
; MIPS64R6O0-NEXT: and $3, $2, $4
; MIPS64R6O0-NEXT: scd $3, 0($1)
; MIPS64R6O0-NEXT: beqzc $3, .LBB2_1
; MIPS64R6O0-NEXT: nop
; MIPS64R6O0-NEXT: # %bb.2: # %entry
; MIPS64R6O0-NEXT: jrc $ra
@ -566,13 +566,13 @@ define i64 @AtomicLoadOr(i64 signext %incr) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadOr)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadOr)))
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB3_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
; MIPS64R6O0-NEXT: lld $2, 0($3)
; MIPS64R6O0-NEXT: or $1, $2, $4
; MIPS64R6O0-NEXT: scd $1, 0($3)
; MIPS64R6O0-NEXT: beqzc $1, .LBB3_1
; MIPS64R6O0-NEXT: lld $2, 0($1)
; MIPS64R6O0-NEXT: or $3, $2, $4
; MIPS64R6O0-NEXT: scd $3, 0($1)
; MIPS64R6O0-NEXT: beqzc $3, .LBB3_1
; MIPS64R6O0-NEXT: nop
; MIPS64R6O0-NEXT: # %bb.2: # %entry
; MIPS64R6O0-NEXT: jrc $ra
@ -723,13 +723,13 @@ define i64 @AtomicLoadXor(i64 signext %incr) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadXor)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadXor)))
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB4_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
; MIPS64R6O0-NEXT: lld $2, 0($3)
; MIPS64R6O0-NEXT: xor $1, $2, $4
; MIPS64R6O0-NEXT: scd $1, 0($3)
; MIPS64R6O0-NEXT: beqzc $1, .LBB4_1
; MIPS64R6O0-NEXT: lld $2, 0($1)
; MIPS64R6O0-NEXT: xor $3, $2, $4
; MIPS64R6O0-NEXT: scd $3, 0($1)
; MIPS64R6O0-NEXT: beqzc $3, .LBB4_1
; MIPS64R6O0-NEXT: nop
; MIPS64R6O0-NEXT: # %bb.2: # %entry
; MIPS64R6O0-NEXT: jrc $ra
@ -884,14 +884,14 @@ define i64 @AtomicLoadNand(i64 signext %incr) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicLoadNand)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicLoadNand)))
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB5_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
; MIPS64R6O0-NEXT: lld $2, 0($3)
; MIPS64R6O0-NEXT: and $1, $2, $4
; MIPS64R6O0-NEXT: nor $1, $zero, $1
; MIPS64R6O0-NEXT: scd $1, 0($3)
; MIPS64R6O0-NEXT: beqzc $1, .LBB5_1
; MIPS64R6O0-NEXT: lld $2, 0($1)
; MIPS64R6O0-NEXT: and $3, $2, $4
; MIPS64R6O0-NEXT: nor $3, $zero, $3
; MIPS64R6O0-NEXT: scd $3, 0($1)
; MIPS64R6O0-NEXT: beqzc $3, .LBB5_1
; MIPS64R6O0-NEXT: nop
; MIPS64R6O0-NEXT: # %bb.2: # %entry
; MIPS64R6O0-NEXT: jrc $ra
@ -1057,15 +1057,16 @@ define i64 @AtomicSwap64(i64 signext %newval) nounwind {
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicSwap64)))
; MIPS64R6O0-NEXT: sd $4, 8($sp)
; MIPS64R6O0-NEXT: ld $4, 8($sp)
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: ld $2, 8($sp)
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB6_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
; MIPS64R6O0-NEXT: lld $2, 0($3)
; MIPS64R6O0-NEXT: move $1, $4
; MIPS64R6O0-NEXT: scd $1, 0($3)
; MIPS64R6O0-NEXT: beqzc $1, .LBB6_1
; MIPS64R6O0-NEXT: lld $3, 0($1)
; MIPS64R6O0-NEXT: move $4, $2
; MIPS64R6O0-NEXT: scd $4, 0($1)
; MIPS64R6O0-NEXT: beqzc $4, .LBB6_1
; MIPS64R6O0-NEXT: # %bb.2: # %entry
; MIPS64R6O0-NEXT: move $2, $3
; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16
; MIPS64R6O0-NEXT: jrc $ra
;
@ -1252,18 +1253,19 @@ define i64 @AtomicCmpSwap64(i64 signext %oldval, i64 signext %newval) nounwind {
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicCmpSwap64)))
; MIPS64R6O0-NEXT: sd $5, 8($sp)
; MIPS64R6O0-NEXT: ld $5, 8($sp)
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: ld $2, 8($sp)
; MIPS64R6O0-NEXT: ld $1, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB7_1: # %entry
; MIPS64R6O0-NEXT: # =>This Inner Loop Header: Depth=1
; MIPS64R6O0-NEXT: lld $2, 0($3)
; MIPS64R6O0-NEXT: bnec $2, $4, .LBB7_3
; MIPS64R6O0-NEXT: lld $3, 0($1)
; MIPS64R6O0-NEXT: bnec $3, $4, .LBB7_3
; MIPS64R6O0-NEXT: # %bb.2: # %entry
; MIPS64R6O0-NEXT: # in Loop: Header=BB7_1 Depth=1
; MIPS64R6O0-NEXT: move $1, $5
; MIPS64R6O0-NEXT: scd $1, 0($3)
; MIPS64R6O0-NEXT: beqzc $1, .LBB7_1
; MIPS64R6O0-NEXT: move $5, $2
; MIPS64R6O0-NEXT: scd $5, 0($1)
; MIPS64R6O0-NEXT: beqzc $5, .LBB7_1
; MIPS64R6O0-NEXT: .LBB7_3: # %entry
; MIPS64R6O0-NEXT: move $2, $3
; MIPS64R6O0-NEXT: daddiu $sp, $sp, 16
; MIPS64R6O0-NEXT: jrc $ra
;

64
llvm/test/CodeGen/Mips/atomicCmpSwapPW.ll
View File

@ -12,18 +12,18 @@ define void @foo(i32 %new, i32 %old) {
; O32-LABEL: foo:
; O32: # %bb.0: # %entry
; O32-NEXT: lui $1, %hi(sym)
; O32-NEXT: lw $3, %lo(sym)($1)
; O32-NEXT: lw $1, %lo(sym)($1)
; O32-NEXT: sync
; O32-NEXT: $BB0_1: # %entry
; O32-NEXT: # =>This Inner Loop Header: Depth=1
; O32-NEXT: ll $1, 0($3)
; O32-NEXT: bne $1, $4, $BB0_3
; O32-NEXT: ll $2, 0($1)
; O32-NEXT: bne $2, $4, $BB0_3
; O32-NEXT: nop
; O32-NEXT: # %bb.2: # %entry
; O32-NEXT: # in Loop: Header=BB0_1 Depth=1
; O32-NEXT: move $2, $5
; O32-NEXT: sc $2, 0($3)
; O32-NEXT: beqz $2, $BB0_1
; O32-NEXT: move $3, $5
; O32-NEXT: sc $3, 0($1)
; O32-NEXT: beqz $3, $BB0_1
; O32-NEXT: nop
; O32-NEXT: $BB0_3: # %entry
; O32-NEXT: sync
@ -32,23 +32,23 @@ define void @foo(i32 %new, i32 %old) {
;
; N32-LABEL: foo:
; N32: # %bb.0: # %entry
; N32-NEXT: move $1, $5
; N32-NEXT: sll $5, $1, 0
; N32-NEXT: move $1, $4
; N32-NEXT: sll $4, $1, 0
; N32-NEXT: lui $1, %hi(sym)
; N32-NEXT: lw $3, %lo(sym)($1)
; N32-NEXT: # kill: def $a1 killed $a1 killed $a1_64
; N32-NEXT: sll $1, $5, 0
; N32-NEXT: # kill: def $a0 killed $a0 killed $a0_64
; N32-NEXT: sll $2, $4, 0
; N32-NEXT: lui $3, %hi(sym)
; N32-NEXT: lw $3, %lo(sym)($3)
; N32-NEXT: sync
; N32-NEXT: .LBB0_1: # %entry
; N32-NEXT: # =>This Inner Loop Header: Depth=1
; N32-NEXT: ll $1, 0($3)
; N32-NEXT: bne $1, $4, .LBB0_3
; N32-NEXT: ll $4, 0($3)
; N32-NEXT: bne $4, $2, .LBB0_3
; N32-NEXT: nop
; N32-NEXT: # %bb.2: # %entry
; N32-NEXT: # in Loop: Header=BB0_1 Depth=1
; N32-NEXT: move $2, $5
; N32-NEXT: sc $2, 0($3)
; N32-NEXT: beqz $2, .LBB0_1
; N32-NEXT: move $5, $1
; N32-NEXT: sc $5, 0($3)
; N32-NEXT: beqz $5, .LBB0_1
; N32-NEXT: nop
; N32-NEXT: .LBB0_3: # %entry
; N32-NEXT: sync
@ -57,27 +57,27 @@ define void @foo(i32 %new, i32 %old) {
;
; N64-LABEL: foo:
; N64: # %bb.0: # %entry
; N64-NEXT: move $1, $5
; N64-NEXT: sll $5, $1, 0
; N64-NEXT: move $1, $4
; N64-NEXT: sll $4, $1, 0
; N64-NEXT: lui $1, %highest(sym)
; N64-NEXT: daddiu $1, $1, %higher(sym)
; N64-NEXT: dsll $1, $1, 16
; N64-NEXT: daddiu $1, $1, %hi(sym)
; N64-NEXT: dsll $1, $1, 16
; N64-NEXT: ld $3, %lo(sym)($1)
; N64-NEXT: # kill: def $a1 killed $a1 killed $a1_64
; N64-NEXT: sll $1, $5, 0
; N64-NEXT: # kill: def $a0 killed $a0 killed $a0_64
; N64-NEXT: sll $2, $4, 0
; N64-NEXT: lui $3, %highest(sym)
; N64-NEXT: daddiu $3, $3, %higher(sym)
; N64-NEXT: dsll $3, $3, 16
; N64-NEXT: daddiu $3, $3, %hi(sym)
; N64-NEXT: dsll $3, $3, 16
; N64-NEXT: ld $3, %lo(sym)($3)
; N64-NEXT: sync
; N64-NEXT: .LBB0_1: # %entry
; N64-NEXT: # =>This Inner Loop Header: Depth=1
; N64-NEXT: ll $1, 0($3)
; N64-NEXT: bne $1, $4, .LBB0_3
; N64-NEXT: ll $4, 0($3)
; N64-NEXT: bne $4, $2, .LBB0_3
; N64-NEXT: nop
; N64-NEXT: # %bb.2: # %entry
; N64-NEXT: # in Loop: Header=BB0_1 Depth=1
; N64-NEXT: move $2, $5
; N64-NEXT: sc $2, 0($3)
; N64-NEXT: beqz $2, .LBB0_1
; N64-NEXT: move $5, $1
; N64-NEXT: sc $5, 0($3)
; N64-NEXT: beqz $5, .LBB0_1
; N64-NEXT: nop
; N64-NEXT: .LBB0_3: # %entry
; N64-NEXT: sync

2
llvm/test/CodeGen/Mips/copy-fp64.ll
View File

@ -11,8 +11,8 @@ define double @foo(double %self) {
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $d12_64, $t9, $v0
; CHECK: renamable $at = ADDu killed $v0, killed $t9
; CHECK: renamable $d6_64 = COPY killed $d12_64
; CHECK: ADJCALLSTACKDOWN 16, 0, implicit-def $sp, implicit $sp
; CHECK: $d6_64 = COPY killed renamable $d12_64
; CHECK: renamable $t9 = LW killed renamable $at, target-flags(mips-got) @bar
; CHECK: dead $ra = JALR killed $t9, csr_o32_fp64, target-flags(mips-jalr) <mcsymbol bar>, implicit-def dead $ra, implicit killed $d6_64, implicit-def $d0_64
; CHECK: ADJCALLSTACKUP 16, 0, implicit-def $sp, implicit $sp

57
llvm/test/CodeGen/Mips/implicit-sret.ll
View File

@ -20,8 +20,9 @@ define internal void @test() unnamed_addr nounwind {
; CHECK-NEXT: ld $5, 16($sp)
; CHECK-NEXT: ld $7, 32($sp)
; CHECK-NEXT: lw $1, 8($sp)
; CHECK-NEXT: # implicit-def: $a0_64
; CHECK-NEXT: move $4, $1
; CHECK-NEXT: # implicit-def: $v0_64
; CHECK-NEXT: move $2, $1
; CHECK-NEXT: move $4, $2
; CHECK-NEXT: jal use_sret
; CHECK-NEXT: nop
; CHECK-NEXT: ld $ra, 40($sp) # 8-byte Folded Reload
@ -40,15 +41,15 @@ start:
define internal { i32, i128, i64 } @implicit_sret_impl() unnamed_addr nounwind {
; CHECK-LABEL: implicit_sret_impl:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $at_64 killed $a0_64
; CHECK-NEXT: daddiu $1, $zero, 20
; CHECK-NEXT: sd $1, 16($4)
; CHECK-NEXT: daddiu $1, $zero, 0
; CHECK-NEXT: move $1, $4
; CHECK-NEXT: daddiu $2, $zero, 20
; CHECK-NEXT: sd $2, 16($4)
; CHECK-NEXT: daddiu $2, $zero, 0
; CHECK-NEXT: sd $zero, 8($4)
; CHECK-NEXT: daddiu $1, $zero, 30
; CHECK-NEXT: sd $1, 24($4)
; CHECK-NEXT: addiu $1, $zero, 10
; CHECK-NEXT: sw $1, 0($4)
; CHECK-NEXT: daddiu $3, $zero, 30
; CHECK-NEXT: sd $3, 24($4)
; CHECK-NEXT: addiu $3, $zero, 10
; CHECK-NEXT: sw $3, 0($4)
; CHECK-NEXT: jr $ra
; CHECK-NEXT: nop
ret { i32, i128, i64 } { i32 10, i128 20, i64 30 }
@ -69,10 +70,12 @@ define internal void @test2() unnamed_addr nounwind {
; CHECK-NEXT: lw $3, 4($sp)
; CHECK-NEXT: # implicit-def: $a0_64
; CHECK-NEXT: move $4, $3
; CHECK-NEXT: # implicit-def: $a1_64
; CHECK-NEXT: move $5, $2
; CHECK-NEXT: # implicit-def: $a2_64
; CHECK-NEXT: move $6, $1
; CHECK-NEXT: # implicit-def: $v1_64
; CHECK-NEXT: move $3, $2
; CHECK-NEXT: # implicit-def: $v0_64
; CHECK-NEXT: move $2, $1
; CHECK-NEXT: move $5, $3
; CHECK-NEXT: move $6, $2
; CHECK-NEXT: jal use_sret2
; CHECK-NEXT: nop
; CHECK-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload
@ -92,19 +95,19 @@ start:
define internal { i32, i32, i32, i32, i32, i32 } @implicit_sret_impl2() unnamed_addr nounwind {
; CHECK-LABEL: implicit_sret_impl2:
; CHECK: # %bb.0:
; CHECK-NEXT: # kill: def $at_64 killed $a0_64
; CHECK-NEXT: addiu $1, $zero, 6
; CHECK-NEXT: sw $1, 20($4)
; CHECK-NEXT: addiu $1, $zero, 5
; CHECK-NEXT: sw $1, 16($4)
; CHECK-NEXT: addiu $1, $zero, 4
; CHECK-NEXT: sw $1, 12($4)
; CHECK-NEXT: addiu $1, $zero, 3
; CHECK-NEXT: sw $1, 8($4)
; CHECK-NEXT: addiu $1, $zero, 2
; CHECK-NEXT: sw $1, 4($4)
; CHECK-NEXT: addiu $1, $zero, 1
; CHECK-NEXT: sw $1, 0($4)
; CHECK-NEXT: move $1, $4
; CHECK-NEXT: addiu $2, $zero, 6
; CHECK-NEXT: sw $2, 20($4)
; CHECK-NEXT: addiu $2, $zero, 5
; CHECK-NEXT: sw $2, 16($4)
; CHECK-NEXT: addiu $2, $zero, 4
; CHECK-NEXT: sw $2, 12($4)
; CHECK-NEXT: addiu $2, $zero, 3
; CHECK-NEXT: sw $2, 8($4)
; CHECK-NEXT: addiu $2, $zero, 2
; CHECK-NEXT: sw $2, 4($4)
; CHECK-NEXT: addiu $2, $zero, 1
; CHECK-NEXT: sw $2, 0($4)
; CHECK-NEXT: jr $ra
; CHECK-NEXT: nop
ret { i32, i32, i32, i32, i32, i32 } { i32 1, i32 2, i32 3, i32 4, i32 5, i32 6 }

20
llvm/test/CodeGen/Mips/micromips-eva.mir
View File

@ -196,19 +196,19 @@ body: |
...
# CHECK: 60 22 60 05 lbue $1, 5($2)
# CHECK: 60 22 68 05 lbe $1, 5($2)
# CHECK: 60 22 a8 03 sbe $1, 3($2)
# CHECK: 60 41 60 05 lbue $2, 5($1)
# CHECK: 60 41 68 05 lbe $2, 5($1)
# CHECK: 60 41 a8 03 sbe $2, 3($1)
# CHECK: 60 22 62 0a lhue $1, 10($2)
# CHECK: 60 22 6a 0a lhe $1, 10($2)
# CHECK: 60 22 aa 06 she $1, 6($2)
# CHECK: 60 41 62 0a lhue $2, 10($1)
# CHECK: 60 41 6a 0a lhe $2, 10($1)
# CHECK: 60 41 aa 06 she $2, 6($1)
# CHECK: 60 22 6e 14 lwe $1, 20($2)
# CHECK: 60 22 ae 0c swe $1, 12($2)
# CHECK: 60 41 6e 14 lwe $2, 20($1)
# CHECK: 60 41 ae 0c swe $2, 12($1)
# CHECK: 60 22 6c 00 lle $1, 0($2)
# CHECK: 60 22 ac 00 sce $1, 0($2)
# CHECK: 60 41 6c 00 lle $2, 0($1)
# CHECK: 60 81 ac 00 sce $4, 0($1)
# CHECK: 60 41 a6 05 cachee 2, 5($1)
# CHECK: 60 41 a4 05 prefe 2, 5($1)

84
llvm/test/CodeGen/Mips/msa/ldr_str.ll
View File

@ -11,47 +11,47 @@
define void @llvm_mips_ldr_d_test(<2 x i64>* %val, i8* %ptr) nounwind {
; MIPS32R5-EB-LABEL: llvm_mips_ldr_d_test:
; MIPS32R5-EB: # %bb.0: # %entry
; MIPS32R5-EB-NEXT: # implicit-def: $v0
; MIPS32R5-EB-NEXT: lwr $2, 23($5)
; MIPS32R5-EB-NEXT: lwl $2, 20($5)
; MIPS32R5-EB-NEXT: # implicit-def: $at
; MIPS32R5-EB-NEXT: lwr $1, 19($5)
; MIPS32R5-EB-NEXT: lwl $1, 16($5)
; MIPS32R5-EB-NEXT: fill.w $w0, $2
; MIPS32R5-EB-NEXT: insert.w $w0[1], $1
; MIPS32R5-EB-NEXT: lwr $1, 23($5)
; MIPS32R5-EB-NEXT: lwl $1, 20($5)
; MIPS32R5-EB-NEXT: # implicit-def: $v0
; MIPS32R5-EB-NEXT: lwr $2, 19($5)
; MIPS32R5-EB-NEXT: lwl $2, 16($5)
; MIPS32R5-EB-NEXT: fill.w $w0, $1
; MIPS32R5-EB-NEXT: insert.w $w0[1], $2
; MIPS32R5-EB-NEXT: st.d $w0, 0($4)
; MIPS32R5-EB-NEXT: jr $ra
; MIPS32R5-EB-NEXT: nop
;
; MIPS32R5-EL-LABEL: llvm_mips_ldr_d_test:
; MIPS32R5-EL: # %bb.0: # %entry
; MIPS32R5-EL-NEXT: # implicit-def: $v0
; MIPS32R5-EL-NEXT: lwr $2, 16($5)
; MIPS32R5-EL-NEXT: lwl $2, 19($5)
; MIPS32R5-EL-NEXT: # implicit-def: $at
; MIPS32R5-EL-NEXT: lwr $1, 20($5)
; MIPS32R5-EL-NEXT: lwl $1, 23($5)
; MIPS32R5-EL-NEXT: fill.w $w0, $2
; MIPS32R5-EL-NEXT: insert.w $w0[1], $1
; MIPS32R5-EL-NEXT: lwr $1, 16($5)
; MIPS32R5-EL-NEXT: lwl $1, 19($5)
; MIPS32R5-EL-NEXT: # implicit-def: $v0
; MIPS32R5-EL-NEXT: lwr $2, 20($5)
; MIPS32R5-EL-NEXT: lwl $2, 23($5)
; MIPS32R5-EL-NEXT: fill.w $w0, $1
; MIPS32R5-EL-NEXT: insert.w $w0[1], $2
; MIPS32R5-EL-NEXT: st.d $w0, 0($4)
; MIPS32R5-EL-NEXT: jr $ra
; MIPS32R5-EL-NEXT: nop
;
; MIPS32R6-EB-LABEL: llvm_mips_ldr_d_test:
; MIPS32R6-EB: # %bb.0: # %entry
; MIPS32R6-EB-NEXT: lw $2, 20($5)
; MIPS32R6-EB-NEXT: lw $1, 16($5)
; MIPS32R6-EB-NEXT: fill.w $w0, $2
; MIPS32R6-EB-NEXT: insert.w $w0[1], $1
; MIPS32R6-EB-NEXT: lw $1, 20($5)
; MIPS32R6-EB-NEXT: lw $2, 16($5)
; MIPS32R6-EB-NEXT: fill.w $w0, $1
; MIPS32R6-EB-NEXT: insert.w $w0[1], $2
; MIPS32R6-EB-NEXT: st.d $w0, 0($4)
; MIPS32R6-EB-NEXT: jrc $ra
;
; MIPS32R6-EL-LABEL: llvm_mips_ldr_d_test:
; MIPS32R6-EL: # %bb.0: # %entry
; MIPS32R6-EL-NEXT: lw $2, 16($5)
; MIPS32R6-EL-NEXT: lw $1, 20($5)
; MIPS32R6-EL-NEXT: fill.w $w0, $2
; MIPS32R6-EL-NEXT: insert.w $w0[1], $1
; MIPS32R6-EL-NEXT: lw $1, 16($5)
; MIPS32R6-EL-NEXT: lw $2, 20($5)
; MIPS32R6-EL-NEXT: fill.w $w0, $1
; MIPS32R6-EL-NEXT: insert.w $w0[1], $2
; MIPS32R6-EL-NEXT: st.d $w0, 0($4)
; MIPS32R6-EL-NEXT: jrc $ra
;
@ -122,43 +122,43 @@ define void @llvm_mips_str_d_test(<2 x i64>* %val, i8* %ptr) nounwind {
; MIPS32R5-EB-LABEL: llvm_mips_str_d_test:
; MIPS32R5-EB: # %bb.0: # %entry
; MIPS32R5-EB-NEXT: ld.d $w0, 0($4)
; MIPS32R5-EB-NEXT: copy_s.w $2, $w0[0]
; MIPS32R5-EB-NEXT: copy_s.w $1, $w0[1]
; MIPS32R5-EB-NEXT: swr $2, 19($5)
; MIPS32R5-EB-NEXT: swl $2, 16($5)
; MIPS32R5-EB-NEXT: swr $1, 23($5)
; MIPS32R5-EB-NEXT: swl $1, 20($5)
; MIPS32R5-EB-NEXT: copy_s.w $1, $w0[0]
; MIPS32R5-EB-NEXT: copy_s.w $2, $w0[1]
; MIPS32R5-EB-NEXT: swr $1, 19($5)
; MIPS32R5-EB-NEXT: swl $1, 16($5)
; MIPS32R5-EB-NEXT: swr $2, 23($5)
; MIPS32R5-EB-NEXT: swl $2, 20($5)
; MIPS32R5-EB-NEXT: jr $ra
; MIPS32R5-EB-NEXT: nop
;
; MIPS32R5-EL-LABEL: llvm_mips_str_d_test:
; MIPS32R5-EL: # %bb.0: # %entry
; MIPS32R5-EL-NEXT: ld.d $w0, 0($4)
; MIPS32R5-EL-NEXT: copy_s.w $2, $w0[0]
; MIPS32R5-EL-NEXT: copy_s.w $1, $w0[1]
; MIPS32R5-EL-NEXT: swr $2, 16($5)
; MIPS32R5-EL-NEXT: swl $2, 19($5)
; MIPS32R5-EL-NEXT: swr $1, 20($5)
; MIPS32R5-EL-NEXT: swl $1, 23($5)
; MIPS32R5-EL-NEXT: copy_s.w $1, $w0[0]
; MIPS32R5-EL-NEXT: copy_s.w $2, $w0[1]
; MIPS32R5-EL-NEXT: swr $1, 16($5)
; MIPS32R5-EL-NEXT: swl $1, 19($5)
; MIPS32R5-EL-NEXT: swr $2, 20($5)
; MIPS32R5-EL-NEXT: swl $2, 23($5)
; MIPS32R5-EL-NEXT: jr $ra
; MIPS32R5-EL-NEXT: nop
;
; MIPS32R6-EB-LABEL: llvm_mips_str_d_test:
; MIPS32R6-EB: # %bb.0: # %entry
; MIPS32R6-EB-NEXT: ld.d $w0, 0($4)
; MIPS32R6-EB-NEXT: copy_s.w $2, $w0[0]
; MIPS32R6-EB-NEXT: copy_s.w $1, $w0[1]
; MIPS32R6-EB-NEXT: sw $2, 20($5)
; MIPS32R6-EB-NEXT: sw $1, 16($5)
; MIPS32R6-EB-NEXT: copy_s.w $1, $w0[0]
; MIPS32R6-EB-NEXT: copy_s.w $2, $w0[1]
; MIPS32R6-EB-NEXT: sw $1, 20($5)
; MIPS32R6-EB-NEXT: sw $2, 16($5)
; MIPS32R6-EB-NEXT: jrc $ra
;
; MIPS32R6-EL-LABEL: llvm_mips_str_d_test:
; MIPS32R6-EL: # %bb.0: # %entry
; MIPS32R6-EL-NEXT: ld.d $w0, 0($4)
; MIPS32R6-EL-NEXT: copy_s.w $2, $w0[0]
; MIPS32R6-EL-NEXT: copy_s.w $1, $w0[1]
; MIPS32R6-EL-NEXT: sw $2, 16($5)
; MIPS32R6-EL-NEXT: sw $1, 20($5)
; MIPS32R6-EL-NEXT: copy_s.w $1, $w0[0]
; MIPS32R6-EL-NEXT: copy_s.w $2, $w0[1]
; MIPS32R6-EL-NEXT: sw $1, 16($5)
; MIPS32R6-EL-NEXT: sw $2, 20($5)
; MIPS32R6-EL-NEXT: jrc $ra
;
; MIPS64R6-LABEL: llvm_mips_str_d_test:

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