forked from OSchip/llvm-project
[AMDGPU] Construct memory clauses before RA
Memory clauses are formed into bundles in presence of xnack. Their source operands are marked as early-clobber. This allows to allocate distinct source and destination registers within a clause and prevent breaking the clause with s_nop in the hazard recognizer. Clauses are undone before post-RA scheduler to allow some rescheduling, which will not break the clause since artificial edges are created in the dag to keep memory operations together. Yet this allows a better ILP in some cases. Differential Revision: https://reviews.llvm.org/D47511 llvm-svn: 333691
This commit is contained in:
Stanislav Mekhanoshin
parent
a6922415b1
commit
739174c4be
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@ -51,6 +51,7 @@ FunctionPass *createSIMemoryLegalizerPass();
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FunctionPass *createSIDebuggerInsertNopsPass();
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FunctionPass *createSIInsertWaitcntsPass();
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FunctionPass *createSIFixWWMLivenessPass();
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FunctionPass *createSIFormMemoryClausesPass();
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FunctionPass *createAMDGPUSimplifyLibCallsPass(const TargetOptions &);
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FunctionPass *createAMDGPUUseNativeCallsPass();
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FunctionPass *createAMDGPUCodeGenPreparePass();
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@ -177,6 +178,9 @@ extern char &SIDebuggerInsertNopsID;
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void initializeSIInsertWaitcntsPass(PassRegistry&);
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extern char &SIInsertWaitcntsID;
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void initializeSIFormMemoryClausesPass(PassRegistry&);
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extern char &SIFormMemoryClausesID;
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void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
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extern char &AMDGPUUnifyDivergentExitNodesID;
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@ -171,6 +171,7 @@ extern "C" void LLVMInitializeAMDGPUTarget() {
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initializeSIDebuggerInsertNopsPass(*PR);
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initializeSIOptimizeExecMaskingPass(*PR);
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initializeSIFixWWMLivenessPass(*PR);
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initializeSIFormMemoryClausesPass(*PR);
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initializeAMDGPUUnifyDivergentExitNodesPass(*PR);
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initializeAMDGPUAAWrapperPassPass(*PR);
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initializeAMDGPUUseNativeCallsPass(*PR);
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@ -847,6 +848,8 @@ void GCNPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
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void GCNPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
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insertPass(&MachineSchedulerID, &SIOptimizeExecMaskingPreRAID);
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insertPass(&SIOptimizeExecMaskingPreRAID, &SIFormMemoryClausesID);
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// This must be run immediately after phi elimination and before
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// TwoAddressInstructions, otherwise the processing of the tied operand of
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// SI_ELSE will introduce a copy of the tied operand source after the else.
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@ -85,6 +85,7 @@ add_llvm_target(AMDGPUCodeGen
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SIFixVGPRCopies.cpp
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SIFixWWMLiveness.cpp
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SIFoldOperands.cpp
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SIFormMemoryClauses.cpp
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SIFrameLowering.cpp
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SIInsertSkips.cpp
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SIInsertWaitcnts.cpp
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@ -0,0 +1,398 @@
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//===-- SIFormMemoryClauses.cpp -------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass creates bundles of SMEM and VMEM instructions forming memory
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/// clauses if XNACK is enabled. Def operands of clauses are marked as early
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/// clobber to make sure we will not override any source within a clause.
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///
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "GCNRegPressure.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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#define DEBUG_TYPE "si-form-memory-clauses"
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// Clauses longer then 15 instructions would overflow one of the counters
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// and stall. They can stall even earlier if there are outstanding counters.
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static cl::opt<unsigned>
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MaxClause("amdgpu-max-memory-clause", cl::Hidden, cl::init(15),
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cl::desc("Maximum length of a memory clause, instructions"));
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namespace {
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class SIFormMemoryClauses : public MachineFunctionPass {
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typedef DenseMap<unsigned, std::pair<unsigned, LaneBitmask>> RegUse;
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public:
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static char ID;
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public:
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SIFormMemoryClauses() : MachineFunctionPass(ID) {
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initializeSIFormMemoryClausesPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "SI Form memory clauses";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<LiveIntervals>();
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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template <typename Callable>
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void forAllLanes(unsigned Reg, LaneBitmask LaneMask, Callable Func) const;
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bool canBundle(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
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bool checkPressure(const MachineInstr &MI, GCNDownwardRPTracker &RPT);
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void collectRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
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bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses,
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GCNDownwardRPTracker &RPT);
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const SISubtarget *ST;
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const SIRegisterInfo *TRI;
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const MachineRegisterInfo *MRI;
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SIMachineFunctionInfo *MFI;
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unsigned LastRecordedOccupancy;
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unsigned MaxVGPRs;
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unsigned MaxSGPRs;
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(SIFormMemoryClauses, DEBUG_TYPE,
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"SI Form memory clauses", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_END(SIFormMemoryClauses, DEBUG_TYPE,
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"SI Form memory clauses", false, false)
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char SIFormMemoryClauses::ID = 0;
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char &llvm::SIFormMemoryClausesID = SIFormMemoryClauses::ID;
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FunctionPass *llvm::createSIFormMemoryClausesPass() {
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return new SIFormMemoryClauses();
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}
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static bool isVMEMClauseInst(const MachineInstr &MI) {
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return SIInstrInfo::isFLAT(MI) || SIInstrInfo::isVMEM(MI);
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}
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static bool isSMEMClauseInst(const MachineInstr &MI) {
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return SIInstrInfo::isSMRD(MI);
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}
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// There no sense to create store clauses, they do not define anything,
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// thus there is nothing to set early-clobber.
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static bool isValidClauseInst(const MachineInstr &MI, bool IsVMEMClause) {
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if (MI.isDebugValue() || MI.isBundled())
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return false;
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if (!MI.mayLoad() || MI.mayStore())
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return false;
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if (AMDGPU::getAtomicNoRetOp(MI.getOpcode()) != -1 ||
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AMDGPU::getAtomicRetOp(MI.getOpcode()) != -1)
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return false;
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if (IsVMEMClause && !isVMEMClauseInst(MI))
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return false;
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if (!IsVMEMClause && !isSMEMClauseInst(MI))
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return false;
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return true;
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}
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static unsigned getMopState(const MachineOperand &MO) {
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unsigned S = 0;
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if (MO.isImplicit())
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S |= RegState::Implicit;
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if (MO.isDead())
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S |= RegState::Dead;
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if (MO.isUndef())
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S |= RegState::Undef;
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if (MO.isKill())
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S |= RegState::Kill;
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if (MO.isEarlyClobber())
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S |= RegState::EarlyClobber;
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if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && MO.isRenamable())
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S |= RegState::Renamable;
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return S;
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}
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template <typename Callable>
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void SIFormMemoryClauses::forAllLanes(unsigned Reg, LaneBitmask LaneMask,
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Callable Func) const {
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if (LaneMask.all() || TargetRegisterInfo::isPhysicalRegister(Reg) ||
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LaneMask == MRI->getMaxLaneMaskForVReg(Reg)) {
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Func(0);
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return;
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}
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const TargetRegisterClass *RC = MRI->getRegClass(Reg);
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unsigned E = TRI->getNumSubRegIndices();
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SmallVector<unsigned, AMDGPU::NUM_TARGET_SUBREGS> CoveringSubregs;
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for (unsigned Idx = 1; Idx < E; ++Idx) {
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// Is this index even compatible with the given class?
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if (TRI->getSubClassWithSubReg(RC, Idx) != RC)
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continue;
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LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(Idx);
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// Early exit if we found a perfect match.
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if (SubRegMask == LaneMask) {
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Func(Idx);
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return;
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}
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if ((SubRegMask & ~LaneMask).any() || (SubRegMask & LaneMask).none())
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continue;
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CoveringSubregs.push_back(Idx);
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}
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llvm::sort(CoveringSubregs.begin(), CoveringSubregs.end(),
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[this](unsigned A, unsigned B) {
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LaneBitmask MaskA = TRI->getSubRegIndexLaneMask(A);
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LaneBitmask MaskB = TRI->getSubRegIndexLaneMask(B);
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unsigned NA = MaskA.getNumLanes();
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unsigned NB = MaskB.getNumLanes();
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if (NA != NB)
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return NA > NB;
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return MaskA.getHighestLane() > MaskB.getHighestLane();
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});
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for (unsigned Idx : CoveringSubregs) {
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LaneBitmask SubRegMask = TRI->getSubRegIndexLaneMask(Idx);
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if ((SubRegMask & ~LaneMask).any() || (SubRegMask & LaneMask).none())
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continue;
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Func(Idx);
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LaneMask &= ~SubRegMask;
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if (LaneMask.none())
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return;
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}
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llvm_unreachable("Failed to find all subregs to cover lane mask");
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}
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// Returns false if there is a use of a def already in the map.
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// In this case we must break the clause.
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bool SIFormMemoryClauses::canBundle(const MachineInstr &MI,
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RegUse &Defs, RegUse &Uses) const {
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// Check interference with defs.
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for (const MachineOperand &MO : MI.operands()) {
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// TODO: Prologue/Epilogue Insertion pass does not process bundled
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// instructions.
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if (MO.isFI())
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return false;
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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// If it is tied we will need to write same register as we read.
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if (MO.isTied())
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return false;
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RegUse &Map = MO.isDef() ? Uses : Defs;
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auto Conflict = Map.find(Reg);
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if (Conflict == Map.end())
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continue;
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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return false;
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LaneBitmask Mask = TRI->getSubRegIndexLaneMask(MO.getSubReg());
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if ((Conflict->second.second & Mask).any())
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return false;
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}
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return true;
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}
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// Since all defs in the clause are early clobber we can run out of registers.
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// Function returns false if pressure would hit the limit if instruction is
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// bundled into a memory clause.
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bool SIFormMemoryClauses::checkPressure(const MachineInstr &MI,
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GCNDownwardRPTracker &RPT) {
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// NB: skip advanceBeforeNext() call. Since all defs will be marked
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// early-clobber they will all stay alive at least to the end of the
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// clause. Therefor we should not decrease pressure even if load
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// pointer becomes dead and could otherwise be reused for destination.
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RPT.advanceToNext();
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GCNRegPressure MaxPressure = RPT.moveMaxPressure();
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unsigned Occupancy = MaxPressure.getOccupancy(*ST);
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if (Occupancy >= MFI->getMinAllowedOccupancy() &&
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MaxPressure.getVGPRNum() <= MaxVGPRs &&
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MaxPressure.getSGPRNum() <= MaxSGPRs) {
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LastRecordedOccupancy = Occupancy;
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return true;
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}
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return false;
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}
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// Collect register defs and uses along with their lane masks and states.
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void SIFormMemoryClauses::collectRegUses(const MachineInstr &MI,
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RegUse &Defs, RegUse &Uses) const {
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for (const MachineOperand &MO : MI.operands()) {
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if (!MO.isReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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continue;
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LaneBitmask Mask = TargetRegisterInfo::isVirtualRegister(Reg) ?
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TRI->getSubRegIndexLaneMask(MO.getSubReg()) :
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LaneBitmask::getAll();
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RegUse &Map = MO.isDef() ? Defs : Uses;
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auto Loc = Map.find(Reg);
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unsigned State = getMopState(MO);
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if (Loc == Map.end()) {
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Map[Reg] = std::make_pair(State, Mask);
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} else {
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Loc->second.first |= State;
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Loc->second.second |= Mask;
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}
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}
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}
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// Check register def/use conflicts, occupancy limits and collect def/use maps.
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// Return true if instruction can be bundled with previous. It it cannot
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// def/use maps are not updated.
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bool SIFormMemoryClauses::processRegUses(const MachineInstr &MI,
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RegUse &Defs, RegUse &Uses,
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GCNDownwardRPTracker &RPT) {
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if (!canBundle(MI, Defs, Uses))
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return false;
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if (!checkPressure(MI, RPT))
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return false;
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collectRegUses(MI, Defs, Uses);
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return true;
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}
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bool SIFormMemoryClauses::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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ST = &MF.getSubtarget<SISubtarget>();
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if (!ST->isXNACKEnabled())
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return false;
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const SIInstrInfo *TII = ST->getInstrInfo();
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TRI = ST->getRegisterInfo();
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MRI = &MF.getRegInfo();
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MFI = MF.getInfo<SIMachineFunctionInfo>();
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LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
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SlotIndexes *Ind = LIS->getSlotIndexes();
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bool Changed = false;
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MaxVGPRs = TRI->getAllocatableSet(MF, &AMDGPU::VGPR_32RegClass).count();
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MaxSGPRs = TRI->getAllocatableSet(MF, &AMDGPU::SGPR_32RegClass).count();
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for (MachineBasicBlock &MBB : MF) {
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MachineBasicBlock::instr_iterator Next;
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for (auto I = MBB.instr_begin(), E = MBB.instr_end(); I != E; I = Next) {
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MachineInstr &MI = *I;
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Next = std::next(I);
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bool IsVMEM = isVMEMClauseInst(MI);
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if (!isValidClauseInst(MI, IsVMEM))
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continue;
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RegUse Defs, Uses;
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GCNDownwardRPTracker RPT(*LIS);
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RPT.reset(MI);
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if (!processRegUses(MI, Defs, Uses, RPT))
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continue;
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unsigned Length = 1;
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for ( ; Next != E && Length < MaxClause; ++Next) {
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if (!isValidClauseInst(*Next, IsVMEM))
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break;
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// A load from pointer which was loaded inside the same bundle is an
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// impossible clause because we will need to write and read the same
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// register inside. In this case processRegUses will return false.
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if (!processRegUses(*Next, Defs, Uses, RPT))
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break;
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++Length;
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}
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if (Length < 2)
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continue;
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Changed = true;
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MFI->limitOccupancy(LastRecordedOccupancy);
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auto B = BuildMI(MBB, I, DebugLoc(), TII->get(TargetOpcode::BUNDLE));
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Ind->insertMachineInstrInMaps(*B);
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for (auto BI = I; BI != Next; ++BI) {
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BI->bundleWithPred();
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Ind->removeSingleMachineInstrFromMaps(*BI);
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for (MachineOperand &MO : BI->defs())
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if (MO.readsReg())
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MO.setIsInternalRead(true);
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}
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for (auto &&R : Defs) {
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forAllLanes(R.first, R.second.second, [&R, &B](unsigned SubReg) {
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unsigned S = R.second.first | RegState::EarlyClobber;
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if (!SubReg)
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S &= ~(RegState::Undef | RegState::Dead);
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B.addDef(R.first, S, SubReg);
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});
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}
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for (auto &&R : Uses) {
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forAllLanes(R.first, R.second.second, [&R, &B](unsigned SubReg) {
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B.addUse(R.first, R.second.first & ~RegState::Kill, SubReg);
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});
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}
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for (auto &&R : Defs) {
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unsigned Reg = R.first;
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Uses.erase(Reg);
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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LIS->removeInterval(Reg);
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LIS->createAndComputeVirtRegInterval(Reg);
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}
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for (auto &&R : Uses) {
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unsigned Reg = R.first;
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if (TargetRegisterInfo::isPhysicalRegister(Reg))
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continue;
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LIS->removeInterval(Reg);
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LIS->createAndComputeVirtRegInterval(Reg);
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}
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}
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}
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return Changed;
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}
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@ -1266,6 +1266,22 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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MI.setDesc(get(AMDGPU::S_MOV_B64));
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break;
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}
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case TargetOpcode::BUNDLE: {
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if (!MI.mayLoad())
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return false;
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// If it is a load it must be a memory clause
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for (MachineBasicBlock::instr_iterator I = MI.getIterator();
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||||
I->isBundledWithSucc(); ++I) {
|
||||
I->unbundleFromSucc();
|
||||
for (MachineOperand &MO : I->operands())
|
||||
if (MO.isReg())
|
||||
MO.setIsInternalRead(false);
|
||||
}
|
||||
|
||||
MI.eraseFromParent();
|
||||
break;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,166 @@
|
|||
; RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
|
||||
|
||||
; GCN-LABEL: {{^}}vector_clause:
|
||||
; GCN: global_load_dwordx4
|
||||
; GCN-NEXT: global_load_dwordx4
|
||||
; GCN-NEXT: global_load_dwordx4
|
||||
; GCN-NEXT: global_load_dwordx4
|
||||
; GCN-NEXT: s_nop
|
||||
define amdgpu_kernel void @vector_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) {
|
||||
bb:
|
||||
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tmp2 = zext i32 %tmp to i64
|
||||
%tmp3 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp2
|
||||
%tmp4 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp3, align 16
|
||||
%tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp2
|
||||
%tmp6 = add nuw nsw i64 %tmp2, 1
|
||||
%tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp6
|
||||
%tmp8 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp7, align 16
|
||||
%tmp9 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp6
|
||||
%tmp10 = add nuw nsw i64 %tmp2, 2
|
||||
%tmp11 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp10
|
||||
%tmp12 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp11, align 16
|
||||
%tmp13 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp10
|
||||
%tmp14 = add nuw nsw i64 %tmp2, 3
|
||||
%tmp15 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 %tmp14
|
||||
%tmp16 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp15, align 16
|
||||
%tmp17 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 %tmp14
|
||||
store <4 x i32> %tmp4, <4 x i32> addrspace(1)* %tmp5, align 16
|
||||
store <4 x i32> %tmp8, <4 x i32> addrspace(1)* %tmp9, align 16
|
||||
store <4 x i32> %tmp12, <4 x i32> addrspace(1)* %tmp13, align 16
|
||||
store <4 x i32> %tmp16, <4 x i32> addrspace(1)* %tmp17, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}scalar_clause:
|
||||
; GCN: s_load_dwordx2
|
||||
; GCN-NEXT: s_load_dwordx2
|
||||
; GCN-NEXT: s_nop
|
||||
; GCN-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; GCN-NEXT: s_load_dwordx4
|
||||
; GCN-NEXT: s_load_dwordx4
|
||||
; GCN-NEXT: s_load_dwordx4
|
||||
; GCN-NEXT: s_load_dwordx4
|
||||
define amdgpu_kernel void @scalar_clause(<4 x i32> addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture %arg1) {
|
||||
bb:
|
||||
%tmp = load <4 x i32>, <4 x i32> addrspace(1)* %arg, align 16
|
||||
%tmp2 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 1
|
||||
%tmp3 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp2, align 16
|
||||
%tmp4 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 1
|
||||
%tmp5 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 2
|
||||
%tmp6 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp5, align 16
|
||||
%tmp7 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 2
|
||||
%tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg, i64 3
|
||||
%tmp9 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp8, align 16
|
||||
%tmp10 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg1, i64 3
|
||||
store <4 x i32> %tmp, <4 x i32> addrspace(1)* %arg1, align 16
|
||||
store <4 x i32> %tmp3, <4 x i32> addrspace(1)* %tmp4, align 16
|
||||
store <4 x i32> %tmp6, <4 x i32> addrspace(1)* %tmp7, align 16
|
||||
store <4 x i32> %tmp9, <4 x i32> addrspace(1)* %tmp10, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}mubuf_clause:
|
||||
; GCN: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
; GCN-NEXT: s_nop
|
||||
; GCN-NEXT: buffer_load_dword
|
||||
define void @mubuf_clause(<4 x i32> addrspace(5)* noalias nocapture readonly %arg, <4 x i32> addrspace(5)* noalias nocapture %arg1) {
|
||||
bb:
|
||||
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tmp2 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg, i32 %tmp
|
||||
%tmp3 = load <4 x i32>, <4 x i32> addrspace(5)* %tmp2, align 16
|
||||
%tmp4 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg1, i32 %tmp
|
||||
%tmp5 = add nuw nsw i32 %tmp, 1
|
||||
%tmp6 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg, i32 %tmp5
|
||||
%tmp7 = load <4 x i32>, <4 x i32> addrspace(5)* %tmp6, align 16
|
||||
%tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg1, i32 %tmp5
|
||||
%tmp9 = add nuw nsw i32 %tmp, 2
|
||||
%tmp10 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg, i32 %tmp9
|
||||
%tmp11 = load <4 x i32>, <4 x i32> addrspace(5)* %tmp10, align 16
|
||||
%tmp12 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg1, i32 %tmp9
|
||||
%tmp13 = add nuw nsw i32 %tmp, 3
|
||||
%tmp14 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg, i32 %tmp13
|
||||
%tmp15 = load <4 x i32>, <4 x i32> addrspace(5)* %tmp14, align 16
|
||||
%tmp16 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %arg1, i32 %tmp13
|
||||
store <4 x i32> %tmp3, <4 x i32> addrspace(5)* %tmp4, align 16
|
||||
store <4 x i32> %tmp7, <4 x i32> addrspace(5)* %tmp8, align 16
|
||||
store <4 x i32> %tmp11, <4 x i32> addrspace(5)* %tmp12, align 16
|
||||
store <4 x i32> %tmp15, <4 x i32> addrspace(5)* %tmp16, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}vector_clause_indirect:
|
||||
; GCN: global_load_dwordx2 [[ADDR:v\[[0-9:]+\]]], v[{{[0-9:]+}}], off
|
||||
; GCN-NEXT: s_nop
|
||||
; GCN-NEXT: s_waitcnt vmcnt(0)
|
||||
; GCN-NEXT: global_load_dwordx4 v[{{[0-9:]+}}], [[ADDR]], off
|
||||
; GCN-NEXT: global_load_dwordx4 v[{{[0-9:]+}}], [[ADDR]], off offset:16
|
||||
define amdgpu_kernel void @vector_clause_indirect(i64 addrspace(1)* noalias nocapture readonly %arg, <4 x i32> addrspace(1)* noalias nocapture readnone %arg1, <4 x i32> addrspace(1)* noalias nocapture %arg2) {
|
||||
bb:
|
||||
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
|
||||
%tmp3 = zext i32 %tmp to i64
|
||||
%tmp4 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 %tmp3
|
||||
%tmp5 = bitcast i64 addrspace(1)* %tmp4 to <4 x i32> addrspace(1)* addrspace(1)*
|
||||
%tmp6 = load <4 x i32> addrspace(1)*, <4 x i32> addrspace(1)* addrspace(1)* %tmp5, align 8
|
||||
%tmp7 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp6, align 16
|
||||
%tmp8 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %tmp6, i64 1
|
||||
%tmp9 = load <4 x i32>, <4 x i32> addrspace(1)* %tmp8, align 16
|
||||
store <4 x i32> %tmp7, <4 x i32> addrspace(1)* %arg2, align 16
|
||||
%tmp10 = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(1)* %arg2, i64 1
|
||||
store <4 x i32> %tmp9, <4 x i32> addrspace(1)* %tmp10, align 16
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_global_d16_hi:
|
||||
; GCN: global_load_short_d16_hi v
|
||||
; GCN-NEXT: s_nop
|
||||
; GCN-NEXT: global_load_short_d16_hi v
|
||||
define void @load_global_d16_hi(i16 addrspace(1)* %in, i16 %reg, <2 x i16> addrspace(1)* %out) {
|
||||
entry:
|
||||
%gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 32
|
||||
%load1 = load i16, i16 addrspace(1)* %in
|
||||
%load2 = load i16, i16 addrspace(1)* %gep
|
||||
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
|
||||
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* %out
|
||||
%build2 = insertelement <2 x i16> undef, i16 %reg, i32 0
|
||||
%build3 = insertelement <2 x i16> %build2, i16 %load2, i32 1
|
||||
%gep2 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 32
|
||||
store <2 x i16> %build3, <2 x i16> addrspace(1)* %gep2
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}load_global_d16_lo:
|
||||
; GCN: global_load_short_d16 v
|
||||
; GCN-NEXT: s_nop
|
||||
; GCN-NEXT: global_load_short_d16 v
|
||||
define void @load_global_d16_lo(i16 addrspace(1)* %in, i32 %reg, <2 x i16> addrspace(1)* %out) {
|
||||
entry:
|
||||
%gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 32
|
||||
%reg.bc1 = bitcast i32 %reg to <2 x i16>
|
||||
%reg.bc2 = bitcast i32 %reg to <2 x i16>
|
||||
%load1 = load i16, i16 addrspace(1)* %in
|
||||
%load2 = load i16, i16 addrspace(1)* %gep
|
||||
%build1 = insertelement <2 x i16> %reg.bc1, i16 %load1, i32 0
|
||||
%build2 = insertelement <2 x i16> %reg.bc2, i16 %load2, i32 0
|
||||
%gep2 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i64 32
|
||||
store <2 x i16> %build1, <2 x i16> addrspace(1)* %out
|
||||
store <2 x i16> %build2, <2 x i16> addrspace(1)* %gep2
|
||||
ret void
|
||||
}
|
||||
|
||||
declare i32 @llvm.amdgcn.workitem.id.x()
|
||||
|
|
@ -0,0 +1,388 @@
|
|||
# RUN: llc -march=amdgcn -mcpu=gfx902 -verify-machineinstrs -run-pass=phi-node-elimination,si-form-memory-clauses %s -o - | FileCheck -check-prefix=GCN %s
|
||||
|
||||
# GCN-LABEL: {{^}}name: vector_clause{{$}}
|
||||
# GCN: early-clobber %2:vreg_128, early-clobber %4:vreg_128, early-clobber %1:vreg_128, early-clobber %3:vreg_128 = BUNDLE %0, implicit $exec {
|
||||
# GCN-NEXT: %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, implicit $exec
|
||||
# GCN-NEXT: %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, implicit $exec
|
||||
# GCN-NEXT: %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
# GCN-NEXT: GLOBAL_STORE_DWORDX4 %0, %1, 0, 0, 0, implicit $exec
|
||||
|
||||
---
|
||||
name: vector_clause
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vreg_128 }
|
||||
- { id: 2, class: vreg_128 }
|
||||
- { id: 3, class: vreg_128 }
|
||||
- { id: 4, class: vreg_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec
|
||||
%2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, implicit $exec
|
||||
%3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, implicit $exec
|
||||
%4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, implicit $exec
|
||||
GLOBAL_STORE_DWORDX4 %0, %1, 0, 0, 0, implicit $exec
|
||||
GLOBAL_STORE_DWORDX4 %0, %2, 16, 0, 0, implicit $exec
|
||||
GLOBAL_STORE_DWORDX4 %0, %3, 32, 0, 0, implicit $exec
|
||||
GLOBAL_STORE_DWORDX4 %0, %4, 48, 0, 0, implicit $exec
|
||||
...
|
||||
|
||||
# GCN-LABEL: {{^}}name: subreg_full{{$}}
|
||||
# GCN: early-clobber %1:vreg_128 = BUNDLE %0, implicit $exec {
|
||||
# GCN-NEXT: undef %1.sub0:vreg_128 = GLOBAL_LOAD_DWORD %0.sub0_sub1, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: internal %1.sub1:vreg_128 = GLOBAL_LOAD_DWORD %0.sub1_sub2, 16, 0, 0, implicit $exec
|
||||
# GCN-NEXT: internal %1.sub2:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, implicit $exec
|
||||
# GCN-NEXT: internal %1.sub3:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
# GCN-NEXT: GLOBAL_STORE_DWORDX4 %0.sub0_sub1, %1, 0, 0, 0, implicit $exec
|
||||
|
||||
---
|
||||
name: subreg_full
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_128 }
|
||||
- { id: 1, class: vreg_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
undef %1.sub0:vreg_128 = GLOBAL_LOAD_DWORD %0.sub0_sub1, 0, 0, 0, implicit $exec
|
||||
%1.sub1:vreg_128 = GLOBAL_LOAD_DWORD %0.sub1_sub2, 16, 0, 0, implicit $exec
|
||||
%1.sub2:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, implicit $exec
|
||||
%1.sub3:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, implicit $exec
|
||||
GLOBAL_STORE_DWORDX4 %0.sub0_sub1, %1, 0, 0, 0, implicit $exec
|
||||
...
|
||||
|
||||
# GCN-LABEL: {{^}}name: subreg_part{{$}}
|
||||
# GCN: undef early-clobber %1.sub0_sub1:vreg_128, undef early-clobber %1.sub3:vreg_128 = BUNDLE %0, implicit $exec {
|
||||
# GCN-NEXT: undef %1.sub0:vreg_128 = GLOBAL_LOAD_DWORD %0.sub0_sub1, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: internal %1.sub1:vreg_128 = GLOBAL_LOAD_DWORD %0.sub1_sub2, 16, 0, 0, implicit $exec
|
||||
# GCN-NEXT: internal %1.sub3:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
# GCN-NEXT: GLOBAL_STORE_DWORDX4 %0.sub0_sub1, %1, 0, 0, 0, implicit $exec
|
||||
|
||||
---
|
||||
name: subreg_part
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_128 }
|
||||
- { id: 1, class: vreg_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
undef %1.sub0:vreg_128 = GLOBAL_LOAD_DWORD %0.sub0_sub1, 0, 0, 0, implicit $exec
|
||||
%1.sub1:vreg_128 = GLOBAL_LOAD_DWORD %0.sub1_sub2, 16, 0, 0, implicit $exec
|
||||
%1.sub3:vreg_128 = GLOBAL_LOAD_DWORD %0.sub2_sub3, 32, 0, 0, implicit $exec
|
||||
GLOBAL_STORE_DWORDX4 %0.sub0_sub1, %1, 0, 0, 0, implicit $exec
|
||||
...
|
||||
|
||||
# GCN-LABEL: {{^}}name: dead{{$}}
|
||||
# GCN: dead early-clobber %2:vreg_128, dead early-clobber %4:vreg_128, dead early-clobber %1:vreg_128, dead early-clobber %3:vreg_128 = BUNDLE %0, implicit $exec {
|
||||
# GCN-NEXT: dead %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
|
||||
---
|
||||
name: dead
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vreg_128 }
|
||||
- { id: 2, class: vreg_128 }
|
||||
- { id: 3, class: vreg_128 }
|
||||
- { id: 4, class: vreg_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
dead %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec
|
||||
dead %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, implicit $exec
|
||||
dead %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, implicit $exec
|
||||
dead %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, implicit $exec
|
||||
...
|
||||
|
||||
# GCN-LABEL: {{^}}name: subreg_dead{{$}}
|
||||
# GCN: early-clobber %1:vreg_64 = BUNDLE %0, implicit $exec {
|
||||
# GCN-NEXT: %1.sub0:vreg_64 = GLOBAL_LOAD_DWORD %0, 16, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %1.sub1:vreg_64 = GLOBAL_LOAD_DWORD %0, 32, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
# GCN-NEXT: GLOBAL_STORE_DWORD %0, %1.sub0, 0, 0, 0, implicit $exec
|
||||
|
||||
---
|
||||
name: subreg_dead
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vreg_64 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
undef %1.sub0:vreg_64 = GLOBAL_LOAD_DWORD %0, 16, 0, 0, implicit $exec
|
||||
dead %1.sub1:vreg_64 = GLOBAL_LOAD_DWORD %0, 32, 0, 0, implicit $exec
|
||||
GLOBAL_STORE_DWORD %0, %1.sub0, 0, 0, 0, implicit $exec
|
||||
...
|
||||
|
||||
# GCN-LABEL: {{^}}name: kill{{$}}
|
||||
# GCN: early-clobber %2:vreg_128, early-clobber %3:vreg_128 = BUNDLE %0, %1, implicit $exec {
|
||||
# GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 16, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
|
||||
---
|
||||
name: kill
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vreg_64 }
|
||||
- { id: 2, class: vreg_128 }
|
||||
- { id: 3, class: vreg_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec
|
||||
%3:vreg_128 = GLOBAL_LOAD_DWORDX4 killed %1, 16, 0, 0, implicit $exec
|
||||
GLOBAL_STORE_DWORDX4 %0, %2, 0, 0, 0, implicit $exec
|
||||
GLOBAL_STORE_DWORDX4 %0, %3, 16, 0, 0, implicit $exec
|
||||
...
|
||||
|
||||
# GCN-LABEL: {{^}}name: indirect{{$}}
|
||||
# GCN: %1:vreg_64 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: early-clobber %2:vreg_128, early-clobber %3:vreg_128 = BUNDLE %1, implicit $exec {
|
||||
# GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 16, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
|
||||
---
|
||||
name: indirect
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vreg_64 }
|
||||
- { id: 2, class: vreg_128 }
|
||||
- { id: 3, class: vreg_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1:vreg_64 = GLOBAL_LOAD_DWORDX2 %0, 0, 0, 0, implicit $exec
|
||||
%2:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 0, 0, 0, implicit $exec
|
||||
%3:vreg_128 = GLOBAL_LOAD_DWORDX4 %1, 16, 0, 0, implicit $exec
|
||||
GLOBAL_STORE_DWORDX4 %0, %2, 0, 0, 0, implicit $exec
|
||||
GLOBAL_STORE_DWORDX4 %0, %3, 16, 0, 0, implicit $exec
|
||||
...
|
||||
|
||||
# GCN-LABEL: {{^}}name: stack{{$}}
|
||||
# GCN: %0:vreg_64 = IMPLICIT_DEF
|
||||
# GCN-NEXT: %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %stack.0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %stack.0, 16, 0, 0, implicit $exec
|
||||
# GCN-NEXT: GLOBAL_STORE_DWORDX4 %0, %1, 0, 0, 0, implicit $exec
|
||||
|
||||
---
|
||||
name: stack
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vreg_128 }
|
||||
- { id: 2, class: vreg_128 }
|
||||
stack:
|
||||
- { id: 0, type: default, offset: 0, size: 64, alignment: 8 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1:vreg_128 = GLOBAL_LOAD_DWORDX4 %stack.0, 0, 0, 0, implicit $exec
|
||||
%2:vreg_128 = GLOBAL_LOAD_DWORDX4 %stack.0, 16, 0, 0, implicit $exec
|
||||
GLOBAL_STORE_DWORDX4 %0, %1, 0, 0, 0, implicit $exec
|
||||
GLOBAL_STORE_DWORDX4 %0, %2, 16, 0, 0, implicit $exec
|
||||
...
|
||||
|
||||
# GCN-LABEL: {{^}}name: overflow_counter{{$}}
|
||||
# GCN: dead early-clobber %7:vgpr_32, dead early-clobber %14:vgpr_32, dead early-clobber %2:vgpr_32, dead early-clobber %9:vgpr_32, dead early-clobber %4:vgpr_32, dead early-clobber %11:vgpr_32, dead early-clobber %6:vgpr_32, dead early-clobber %13:vgpr_32, dead early-clobber %1:vgpr_32, dead early-clobber %8:vgpr_32, dead early-clobber %15:vgpr_32, dead early-clobber %3:vgpr_32, dead early-clobber %10:vgpr_32, dead early-clobber %5:vgpr_32, dead early-clobber %12:vgpr_32 = BUNDLE %0, implicit $exec {
|
||||
# GCN-NEXT: dead %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %4:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %5:vgpr_32 = GLOBAL_LOAD_DWORD %0, 16, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %6:vgpr_32 = GLOBAL_LOAD_DWORD %0, 20, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %7:vgpr_32 = GLOBAL_LOAD_DWORD %0, 24, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %8:vgpr_32 = GLOBAL_LOAD_DWORD %0, 28, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %9:vgpr_32 = GLOBAL_LOAD_DWORD %0, 32, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %10:vgpr_32 = GLOBAL_LOAD_DWORD %0, 36, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %11:vgpr_32 = GLOBAL_LOAD_DWORD %0, 40, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %12:vgpr_32 = GLOBAL_LOAD_DWORD %0, 44, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %13:vgpr_32 = GLOBAL_LOAD_DWORD %0, 48, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %14:vgpr_32 = GLOBAL_LOAD_DWORD %0, 52, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %15:vgpr_32 = GLOBAL_LOAD_DWORD %0, 56, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
# GCN-NEXT: dead early-clobber %16:vgpr_32, dead early-clobber %17:vgpr_32 = BUNDLE %0, implicit $exec {
|
||||
# GCN-NEXT: dead %16:vgpr_32 = GLOBAL_LOAD_DWORD %0, 60, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %17:vgpr_32 = GLOBAL_LOAD_DWORD %0, 64, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
|
||||
---
|
||||
name: overflow_counter
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
- { id: 3, class: vgpr_32 }
|
||||
- { id: 4, class: vgpr_32 }
|
||||
- { id: 5, class: vgpr_32 }
|
||||
- { id: 6, class: vgpr_32 }
|
||||
- { id: 7, class: vgpr_32 }
|
||||
- { id: 8, class: vgpr_32 }
|
||||
- { id: 9, class: vgpr_32 }
|
||||
- { id: 10, class: vgpr_32 }
|
||||
- { id: 11, class: vgpr_32 }
|
||||
- { id: 12, class: vgpr_32 }
|
||||
- { id: 13, class: vgpr_32 }
|
||||
- { id: 14, class: vgpr_32 }
|
||||
- { id: 15, class: vgpr_32 }
|
||||
- { id: 16, class: vgpr_32 }
|
||||
- { id: 17, class: vgpr_32 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, 0, implicit $exec
|
||||
%2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 4, 0, 0, implicit $exec
|
||||
%3:vgpr_32 = GLOBAL_LOAD_DWORD %0, 8, 0, 0, implicit $exec
|
||||
%4:vgpr_32 = GLOBAL_LOAD_DWORD %0, 12, 0, 0, implicit $exec
|
||||
%5:vgpr_32 = GLOBAL_LOAD_DWORD %0, 16, 0, 0, implicit $exec
|
||||
%6:vgpr_32 = GLOBAL_LOAD_DWORD %0, 20, 0, 0, implicit $exec
|
||||
%7:vgpr_32 = GLOBAL_LOAD_DWORD %0, 24, 0, 0, implicit $exec
|
||||
%8:vgpr_32 = GLOBAL_LOAD_DWORD %0, 28, 0, 0, implicit $exec
|
||||
%9:vgpr_32 = GLOBAL_LOAD_DWORD %0, 32, 0, 0, implicit $exec
|
||||
%10:vgpr_32 = GLOBAL_LOAD_DWORD %0, 36, 0, 0, implicit $exec
|
||||
%11:vgpr_32 = GLOBAL_LOAD_DWORD %0, 40, 0, 0, implicit $exec
|
||||
%12:vgpr_32 = GLOBAL_LOAD_DWORD %0, 44, 0, 0, implicit $exec
|
||||
%13:vgpr_32 = GLOBAL_LOAD_DWORD %0, 48, 0, 0, implicit $exec
|
||||
%14:vgpr_32 = GLOBAL_LOAD_DWORD %0, 52, 0, 0, implicit $exec
|
||||
%15:vgpr_32 = GLOBAL_LOAD_DWORD %0, 56, 0, 0, implicit $exec
|
||||
%16:vgpr_32 = GLOBAL_LOAD_DWORD %0, 60, 0, 0, implicit $exec
|
||||
%17:vgpr_32 = GLOBAL_LOAD_DWORD %0, 64, 0, 0, implicit $exec
|
||||
...
|
||||
|
||||
# GCN-LABEL: {{^}}name: reg_pressure{{$}}
|
||||
# GCN: dead early-clobber %2:vreg_128, dead early-clobber %4:vreg_128, dead early-clobber %1:vreg_128, dead early-clobber %3:vreg_128, dead early-clobber %5:vreg_128 = BUNDLE %0, implicit $exec {
|
||||
# GCN-NEXT: dead %1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %5:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 64, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
# GCN-NEXT: dead early-clobber %7:vreg_128, dead early-clobber %6:vreg_128 = BUNDLE %0, implicit $exec {
|
||||
# GCN-NEXT: dead %6:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 80, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %7:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 96, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
|
||||
---
|
||||
name: reg_pressure
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vreg_128 }
|
||||
- { id: 2, class: vreg_128 }
|
||||
- { id: 3, class: vreg_128 }
|
||||
- { id: 4, class: vreg_128 }
|
||||
- { id: 5, class: vreg_128 }
|
||||
- { id: 6, class: vreg_128 }
|
||||
- { id: 7, class: vreg_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec
|
||||
%2:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 16, 0, 0, implicit $exec
|
||||
%3:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 32, 0, 0, implicit $exec
|
||||
%4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 48, 0, 0, implicit $exec
|
||||
%5:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 64, 0, 0, implicit $exec
|
||||
%6:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 80, 0, 0, implicit $exec
|
||||
%7:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 96, 0, 0, implicit $exec
|
||||
...
|
||||
|
||||
# GCN-LABEL: {{^}}name: image_clause{{$}}
|
||||
# GCN: early-clobber %4:vreg_128, early-clobber %3:vreg_128, early-clobber %5:vreg_128 = BUNDLE %0, undef %2:sreg_128, %1, implicit $exec {
|
||||
# GCN-NEXT: %3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: %4:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: %5:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
# GCN-NEXT: IMAGE_STORE_V4_V2 %3, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
|
||||
---
|
||||
name: image_clause
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: sreg_256 }
|
||||
- { id: 2, class: sreg_128 }
|
||||
- { id: 3, class: vreg_128 }
|
||||
- { id: 4, class: vreg_128 }
|
||||
- { id: 5, class: vreg_128 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%4:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%5:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, undef %2:sreg_128, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
IMAGE_STORE_V4_V2 %3, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
IMAGE_STORE_V4_V2 %4, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
IMAGE_STORE_V4_V2 %5, %0, %1, 15, -1, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
...
|
||||
|
||||
# GCN-LABEL: {{^}}name: mixed_clause{{$}}
|
||||
# GCN: dead early-clobber %4:vreg_128, dead early-clobber %3:vreg_128, dead early-clobber %5:vgpr_32 = BUNDLE %0, %2, %1, implicit $exec {
|
||||
# GCN-NEXT: dead %3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, %2, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: dead %5:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 %0, %2, 0, 0, 0, 0, 0, implicit $exec
|
||||
# GCN-NEXT: }
|
||||
|
||||
---
|
||||
name: mixed_clause
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: sreg_256 }
|
||||
- { id: 2, class: sreg_128 }
|
||||
- { id: 3, class: vreg_128 }
|
||||
- { id: 4, class: vreg_128 }
|
||||
- { id: 5, class: vgpr_32 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2 = IMPLICIT_DEF
|
||||
%3:vreg_128 = IMAGE_SAMPLE_LZ_V4_V2 %0, %1, %2, 15, 0, 0, 0, 0, 0, 0, 0, implicit $exec
|
||||
%4:vreg_128 = GLOBAL_LOAD_DWORDX4 %0, 0, 0, 0, implicit $exec
|
||||
%5:vgpr_32 = BUFFER_LOAD_DWORD_ADDR64 %0, %2, 0, 0, 0, 0, 0, implicit $exec
|
||||
...
|
||||
|
||||
# GCN-LABEL: {{^}}name: atomic{{$}}
|
||||
# GCN: %1:vgpr_32 = IMPLICIT_DEF
|
||||
# GCN-NEXT: dead %2:vgpr_32 = FLAT_ATOMIC_ADD_RTN %0, %1, 0, 0, implicit $exec, implicit $flat_scr
|
||||
# GCN-NEXT: dead %3:vgpr_32 = FLAT_ATOMIC_ADD_RTN %0, %1, 0, 0, implicit $exec, implicit $flat_scr
|
||||
# GCN-NEXT: FLAT_ATOMIC_ADD %0, %1, 0, 0, implicit $exec, implicit $flat_scr
|
||||
# GCN-NEXT: FLAT_ATOMIC_ADD %0, %1, 0, 0, implicit $exec, implicit $flat_scr
|
||||
# GCN-NEXT: S_ENDPGM
|
||||
|
||||
---
|
||||
name: atomic
|
||||
tracksRegLiveness: true
|
||||
registers:
|
||||
- { id: 0, class: vreg_64 }
|
||||
- { id: 1, class: vgpr_32 }
|
||||
- { id: 2, class: vgpr_32 }
|
||||
- { id: 3, class: vgpr_32 }
|
||||
body: |
|
||||
bb.0:
|
||||
%0 = IMPLICIT_DEF
|
||||
%1 = IMPLICIT_DEF
|
||||
%2:vgpr_32 = FLAT_ATOMIC_ADD_RTN %0, %1, 0, 0, implicit $exec, implicit $flat_scr
|
||||
%3:vgpr_32 = FLAT_ATOMIC_ADD_RTN %0, %1, 0, 0, implicit $exec, implicit $flat_scr
|
||||
FLAT_ATOMIC_ADD %0, %1, 0, 0, implicit $exec, implicit $flat_scr
|
||||
FLAT_ATOMIC_ADD %0, %1, 0, 0, implicit $exec, implicit $flat_scr
|
||||
S_ENDPGM
|
||||
...
|
||||
Loading…
Reference in New Issue