forked from OSchip/llvm-project
MIR: Freeze reserved regs after parsing everything
The AMDGPU implementation of getReservedRegs depends on MachineFunctionInfo fields that are parsed from the YAML section. This was reserving the wrong register since it was setting the reserved regs before parsing the correct one. Some tests were relying on the default reserved set for the assumed default calling convention. llvm-svn: 357083
This commit is contained in:
Matt Arsenault
parent
566fba03de
commit
733b8571b4
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@ -426,6 +426,14 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
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}
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}
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// Set the reserved registers after parsing MachineFuncInfo. The target may
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// have been recording information used to select the reserved registers
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// there.
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// FIXME: This is a temporary workaround until the reserved registers can be
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// serialized.
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MachineRegisterInfo &MRI = MF.getRegInfo();
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MRI.freezeReservedRegs(MF);
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computeFunctionProperties(MF);
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MF.getSubtarget().mirFileLoaded(MF);
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@ -564,9 +572,6 @@ bool MIRParserImpl::setupRegisterInfo(const PerFunctionMIParsingState &PFS,
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}
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}
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// FIXME: This is a temporary workaround until the reserved registers can be
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// serialized.
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MRI.freezeReservedRegs(MF);
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return Error;
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}
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@ -1075,7 +1075,7 @@ body: |
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; CHECK: liveins: $vgpr0, $vgpr1, $sgpr0
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; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; CHECK: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
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; CHECK: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
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; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[C]]
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@ -1097,7 +1097,7 @@ body: |
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $sgpr0
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%3:_(s32) = G_CONSTANT i32 0
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%4:_(s1) = G_TRUNC %0
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%5:_(s1) = G_ICMP intpred(eq), %2, %3
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@ -112,6 +112,7 @@ name: call
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr2_sgpr3
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$vcc = IMPLICIT_DEF
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$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
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$sgpr4_sgpr5 = S_SWAPPC_B64 $sgpr2_sgpr3
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@ -3,9 +3,13 @@
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---
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name: func0
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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scratchWaveOffsetReg: '$sgpr7'
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frameOffsetReg: '$sgpr7'
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body: |
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bb.0:
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liveins: $sgpr7, $sgpr0_sgpr1_sgpr2_sgpr3
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$sgpr33 = S_MOV_B32 $sgpr7
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$sgpr32 = S_MOV_B32 $sgpr33
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@ -29,7 +33,7 @@ body: |
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# CHECK-DAG: $sgpr10 = S_MOV_B32 5
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# CHECK-DAG: $sgpr9 = S_MOV_B32 4
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# CHECK-DAG: $sgpr8 = S_MOV_B32 3
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# CHECK-DAG: $sgpr33 = S_MOV_B32 killed $sgpr7
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# CHECK-DAG: $sgpr33 = S_MOV_B32 $sgpr7
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# CHECK: $vgpr0 = V_MOV_B32_e32 $sgpr8, implicit $exec, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit $sgpr8_sgpr9_sgpr10_sgpr11
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# CHECK: $sgpr32 = S_MOV_B32 $sgpr33
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# CHECK: BUNDLE implicit-def $sgpr6_sgpr7, implicit-def $sgpr6, implicit-def $sgpr7, implicit-def $scc {
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@ -41,5 +45,5 @@ body: |
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# CHECK: $vgpr1 = V_MOV_B32_e32 $sgpr9, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
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# CHECK: $vgpr2 = V_MOV_B32_e32 $sgpr10, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11
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# CHECK: $vgpr3 = V_MOV_B32_e32 killed $sgpr11, implicit $exec, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec
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# CHECK: S_NOP 0, implicit killed $sgpr6_sgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3
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# CHECK: S_NOP 0, implicit $sgpr6_sgpr7, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit killed $sgpr4, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3
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# CHECK: S_ENDPGM 0
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@ -11,6 +11,11 @@ legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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scratchWaveOffsetReg: '$sgpr4'
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frameOffsetReg: '$sgpr4'
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registers:
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- { id: 0, class: vreg_128 }
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- { id: 1, class: vreg_128 }
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@ -92,6 +97,10 @@ legalized: false
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regBankSelected: false
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selected: false
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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scratchWaveOffsetReg: '$sgpr4'
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frameOffsetReg: '$sgpr4'
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registers:
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- { id: 0, class: vgpr_32, preferred-register: '' }
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- { id: 1, class: vgpr_32, preferred-register: '' }
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@ -130,8 +139,7 @@ body: |
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BUFFER_STORE_DWORD_OFFEN %6.sub1, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, 0, implicit $exec
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BUFFER_STORE_DWORD_OFFEN %6.sub0, %0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, 0, implicit $exec
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$sgpr30_sgpr31 = COPY %5
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$sgpr5 = COPY $sgpr5
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S_SETPC_B64_return $sgpr30_sgpr31, implicit $sgpr5
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S_SETPC_B64_return $sgpr30_sgpr31
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...
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@ -0,0 +1,29 @@
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# RUN: llc -march=amdgcn -run-pass=none -verify-machineinstrs -o - %s | FileCheck %s
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# Previously getReservedRegs was called before parsing
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# machineFunctionInfo, but the AMDGPU implementation depends on
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# setting register fields to reserve there. $sgpr50 would then not be
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# reserved, resulting in a verifier error from an undefined register.
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---
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# CHECK: machineFunctionInfo:
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# CHECK: isEntryFunction: true
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# CHECK: scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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# CHECK: scratchWaveOffsetReg: '$sgpr50'
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# CHECK: frameOffsetReg: '$sgpr50'
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# CHECK: renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50, 4, 0, 0, 0, implicit $exec :: (load 4, addrspace 5)
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name: reserve_correct_register
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tracksRegLiveness: true
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machineFunctionInfo:
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isEntryFunction: true
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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scratchWaveOffsetReg: '$sgpr50'
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frameOffsetReg: '$sgpr50'
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stack:
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- { id: 0, type: default, offset: 0, size: 4, alignment: 4 }
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body: |
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bb.0:
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renamable $vgpr0 = BUFFER_LOAD_DWORD_OFFEN %stack.0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr50, 4, 0, 0, 0, implicit $exec :: (load 4, addrspace 5)
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S_ENDPGM 0
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...
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