forked from OSchip/llvm-project
[PowerPC][Power10] Add Vector Splat Imm/Permute/Blend/Shift Double Bit Imm Definitions and MC Tests
This patch adds the td definitions and asm/disasm tests for the following instructions: XXSPLTIW XXSPLTIDP XXSPLTI32DX XXPERMX XXBLENDVB XXBLENDVH XXBLENDVW XXBLENDVD VSLDBI VSRDBI Differential Revision: https://reviews.llvm.org/D82896
This commit is contained in:
Amy Kwan
parent
89a0c4066b
commit
73377c4597
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@ -225,6 +225,137 @@ class VXForm_RD5_N3_VB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
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let Inst{21-31} = xo;
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}
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// VN-Form: [PO VRT VRA VRB PS SD XO]
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// SD is "Shift Direction"
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class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr,
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InstrItinClass itin, list<dag> pattern>
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: I<4, OOL, IOL, asmstr, itin> {
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bits<5> VRT;
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bits<5> VRA;
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bits<5> VRB;
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bits<3> SD;
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let Pattern = pattern;
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let Inst{6-10} = VRT;
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let Inst{11-15} = VRA;
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let Inst{16-20} = VRB;
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let Inst{21-22} = ps;
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let Inst{23-25} = SD;
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let Inst{26-31} = xo;
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}
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// 8RR:D-Form: [ 1 1 0 // // imm0
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// PO T XO TX imm1 ].
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class 8RR_DForm_IMM32_XT6<bits<6> opcode, bits<4> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: PI<1, opcode, OOL, IOL, asmstr, itin> {
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bits<6> XT;
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bits<32> IMM32;
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let Pattern = pattern;
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// The prefix.
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let Inst{6-7} = 1;
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let Inst{8-11} = 0;
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let Inst{12-13} = 0; // reserved
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let Inst{14-15} = 0; // reserved
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let Inst{16-31} = IMM32{31-16};
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// The instruction.
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let Inst{38-42} = XT{4-0};
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let Inst{43-46} = xo;
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let Inst{47} = XT{5};
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let Inst{48-63} = IMM32{15-0};
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}
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// 8RR:D-Form: [ 1 1 0 // // imm0
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// PO T XO IX TX imm1 ].
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class 8RR_DForm_IMM32_XT6_IX<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: PI<1, opcode, OOL, IOL, asmstr, itin> {
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bits<6> XT;
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bit IX;
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bits<32> IMM32;
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let Pattern = pattern;
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// The prefix.
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let Inst{6-7} = 1;
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let Inst{8-11} = 0;
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let Inst{12-13} = 0; // reserved
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let Inst{14-15} = 0; // reserved
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let Inst{16-31} = IMM32{31-16};
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// The instruction.
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let Inst{38-42} = XT{4-0};
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let Inst{43-45} = xo;
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let Inst{46} = IX;
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let Inst{47} = XT{5};
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let Inst{48-63} = IMM32{15-0};
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}
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class 8RR_XX4Form_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin, list<dag> pattern>
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: PI<1, opcode, OOL, IOL, asmstr, itin> {
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bits<6> XT;
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bits<6> XA;
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bits<6> XB;
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bits<6> XC;
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let Pattern = pattern;
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// The prefix.
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let Inst{6-7} = 1;
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let Inst{8-11} = 0;
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let Inst{12-13} = 0;
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let Inst{14-31} = 0;
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// The instruction.
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let Inst{38-42} = XT{4-0};
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let Inst{43-47} = XA{4-0};
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let Inst{48-52} = XB{4-0};
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let Inst{53-57} = XC{4-0};
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let Inst{58-59} = xo;
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let Inst{60} = XC{5};
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let Inst{61} = XA{5};
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let Inst{62} = XB{5};
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let Inst{63} = XT{5};
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}
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class 8RR_XX4Form_IMM3_XTABC6<bits<6> opcode, bits<2> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: PI<1, opcode, OOL, IOL, asmstr, itin> {
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bits<6> XT;
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bits<6> XA;
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bits<6> XB;
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bits<6> XC;
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bits<3> IMM;
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let Pattern = pattern;
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// The prefix.
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let Inst{6-7} = 1;
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let Inst{8-11} = 0;
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let Inst{12-13} = 0;
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let Inst{14-28} = 0;
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let Inst{29-31} = IMM;
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// The instruction.
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let Inst{38-42} = XT{4-0};
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let Inst{43-47} = XA{4-0};
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let Inst{48-52} = XB{4-0};
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let Inst{53-57} = XC{4-0};
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let Inst{58-59} = xo;
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let Inst{60} = XC{5};
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let Inst{61} = XA{5};
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let Inst{62} = XB{5};
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let Inst{63} = XT{5};
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}
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multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
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dag PCRel_IOL, string asmstr,
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InstrItinClass itin> {
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@ -565,7 +696,52 @@ let Predicates = [PCRelativeMemops], AddedComplexity = 500 in {
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def : Pat<(PPCmatpcreladdr pcreladdr:$addr), (PADDI8pc 0, $addr)>;
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}
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let Predicates = [PrefixInstrs] in {
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def XXSPLTIW : 8RR_DForm_IMM32_XT6<32, 3, (outs vsrc:$XT),
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(ins i32imm:$IMM32),
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"xxspltiw $XT, $IMM32", IIC_VecGeneral,
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[]>;
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def XXSPLTIDP : 8RR_DForm_IMM32_XT6<32, 2, (outs vsrc:$XT),
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(ins i32imm:$IMM32),
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"xxspltidp $XT, $IMM32", IIC_VecGeneral,
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[]>;
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def XXSPLTI32DX :
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8RR_DForm_IMM32_XT6_IX<32, 0, (outs vsrc:$XT),
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(ins vsrc:$XTi, i1imm:$IX, i32imm:$IMM32),
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"xxsplti32dx $XT, $IX, $IMM32", IIC_VecGeneral, []>,
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RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">;
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def XXPERMX :
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8RR_XX4Form_IMM3_XTABC6<34, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
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vsrc:$XC, u3imm:$UIM),
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"xxpermx $XT, $XA, $XB, $XC, $UIM",
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IIC_VecPerm, []>;
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def XXBLENDVB :
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8RR_XX4Form_XTABC6<33, 0, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
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vsrc:$XC), "xxblendvb $XT, $XA, $XB, $XC",
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IIC_VecGeneral, []>;
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def XXBLENDVH :
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8RR_XX4Form_XTABC6<33, 1, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
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vsrc:$XC), "xxblendvh $XT, $XA, $XB, $XC",
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IIC_VecGeneral, []>;
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def XXBLENDVW :
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8RR_XX4Form_XTABC6<33, 2, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
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vsrc:$XC), "xxblendvw $XT, $XA, $XB, $XC",
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IIC_VecGeneral, []>;
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def XXBLENDVD :
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8RR_XX4Form_XTABC6<33, 3, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB,
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vsrc:$XC), "xxblendvd $XT, $XA, $XB, $XC",
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IIC_VecGeneral, []>;
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}
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let Predicates = [IsISA3_1] in {
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def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
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(ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
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"vsldbi $VRT, $VRA, $VRB, $SH",
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IIC_VecGeneral, []>;
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def VSRDBI : VNForm_VTAB5_SD3<22, 1, (outs vrrc:$VRT),
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(ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
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"vsrdbi $VRT, $VRA, $VRB, $SH",
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IIC_VecGeneral, []>;
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def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
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"vpdepd $vD, $vA, $vB", IIC_VecGeneral,
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[(set v2i64:$vD,
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@ -186,3 +186,47 @@
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# CHECK: vclrrb 1, 4, 3
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0x10 0x24 0x19 0xcd
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# Boundary conditions of 8RR_DForm_IMM32_XT6's immediates
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# CHECK: xxspltiw 63, 4294901760
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0x05 0x00 0xff 0xff 0x83 0xe7 0x00 0x00
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# CHECK: xxspltiw 63, 65535
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0x05 0x00 0x00 0x00 0x83 0xe7 0xff 0xff
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# CHECK: xxspltiw 63, 4294967295
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0x05 0x00 0xff 0xff 0x83 0xe7 0xff 0xff
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# CHECK: xxspltidp 63, 4294967295
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0x05 0x00 0xff 0xff 0x83 0xe5 0xff 0xff
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# Boundary conditions of 8RR_DForm_IMM32_XT6_IX's immediates
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# CHECK: xxsplti32dx 63, 1, 4294901760
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0x05 0x00 0xff 0xff 0x83 0xe3 0x00 0x00
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# CHECK: xxsplti32dx 63, 1, 65535
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0x05 0x00 0x00 0x00 0x83 0xe3 0xff 0xff
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# CHECK: xxsplti32dx 63, 1, 4294967295
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0x05 0x00 0xff 0xff 0x83 0xe3 0xff 0xff
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# CHECK: xxpermx 6, 63, 21, 34, 2
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0x05 0x00 0x00 0x02 0x88 0xdf 0xa8 0x8c
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# CHECK: xxblendvb 6, 63, 21, 34
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0x05 0x00 0x00 0x00 0x84 0xdf 0xa8 0x8c
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# CHECK: xxblendvh 6, 63, 21, 34
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0x05 0x00 0x00 0x00 0x84 0xdf 0xa8 0x9c
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# CHECK: xxblendvw 6, 63, 21, 34
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0x05 0x00 0x00 0x00 0x84 0xdf 0xa8 0xac
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# CHECK: xxblendvd 6, 63, 21, 34
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0x05 0x00 0x00 0x00 0x84 0xdf 0xa8 0xbc
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# CHECK: vsldbi 2, 3, 4, 5
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0x10 0x43 0x21 0x56
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# CHECK: vsrdbi 2, 3, 4, 5
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0x10 0x43 0x23 0x56
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@ -279,3 +279,81 @@
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# CHECK-BE: vclrrb 1, 4, 3 # encoding: [0x10,0x24,0x19,0xcd]
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# CHECK-LE: vclrrb 1, 4, 3 # encoding: [0xcd,0x19,0x24,0x10]
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vclrrb 1, 4, 3
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# Boundary conditions of 8RR_DForm_IMM32_XT6's immediates
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# CHECK-BE: xxspltiw 63, 4294901760 # encoding: [0x05,0x00,0xff,0xff,
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# CHECK-BE-SAME: 0x83,0xe7,0x00,0x00]
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# CHECK-LE: xxspltiw 63, 4294901760 # encoding: [0xff,0xff,0x00,0x05,
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# CHECK-LE-SAME: 0x00,0x00,0xe7,0x83]
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xxspltiw 63, 4294901760
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# CHECK-BE: xxspltiw 63, 65535 # encoding: [0x05,0x00,0x00,0x00,
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# CHECK-BE-SAME: 0x83,0xe7,0xff,0xff]
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# CHECK-LE: xxspltiw 63, 65535 # encoding: [0x00,0x00,0x00,0x05,
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# CHECK-LE-SAME: 0xff,0xff,0xe7,0x83]
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xxspltiw 63, 65535
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# CHECK-BE: xxspltiw 63, 4294967295 # encoding: [0x05,0x00,0xff,0xff,
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# CHECK-BE-SAME: 0x83,0xe7,0xff,0xff]
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# CHECK-LE: xxspltiw 63, 4294967295 # encoding: [0xff,0xff,0x00,0x05,
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# CHECK-LE-SAME: 0xff,0xff,0xe7,0x83]
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xxspltiw 63, 4294967295
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# CHECK-BE: xxspltiw 63, -1 # encoding: [0x05,0x00,0xff,0xff,
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# CHECK-BE-SAME: 0x83,0xe7,0xff,0xff]
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# CHECK-LE: xxspltiw 63, -1 # encoding: [0xff,0xff,0x00,0x05,
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# CHECK-LE-SAME: 0xff,0xff,0xe7,0x83]
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xxspltiw 63, -1
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# CHECK-BE: xxspltidp 63, 4294967295 # encoding: [0x05,0x00,0xff,0xff,
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# CHECK-BE-SAME: 0x83,0xe5,0xff,0xff]
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# CHECK-LE: xxspltidp 63, 4294967295 # encoding: [0xff,0xff,0x00,0x05,
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# CHECK-LE-SAME: 0xff,0xff,0xe5,0x83]
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xxspltidp 63, 4294967295
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# Boundary conditions of 8RR_DForm_IMM32_XT6_IX's immediates
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# CHECK-BE: xxsplti32dx 63, 1, 4294901760 # encoding: [0x05,0x00,0xff,0xff,
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# CHECK-BE-SAME: 0x83,0xe3,0x00,0x00]
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# CHECK-LE: xxsplti32dx 63, 1, 4294901760 # encoding: [0xff,0xff,0x00,0x05,
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# CHECK-LE-SAME: 0x00,0x00,0xe3,0x83]
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xxsplti32dx 63, 1, 4294901760
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# CHECK-BE: xxsplti32dx 63, 1, 65535 # encoding: [0x05,0x00,0x00,0x00,
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# CHECK-BE-SAME: 0x83,0xe3,0xff,0xff]
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# CHECK-LE: xxsplti32dx 63, 1, 65535 # encoding: [0x00,0x00,0x00,0x05,
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# CHECK-LE-SAME: 0xff,0xff,0xe3,0x83]
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xxsplti32dx 63, 1, 65535
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# CHECK-BE: xxsplti32dx 63, 1, 4294967295 # encoding: [0x05,0x00,0xff,0xff,
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# CHECK-BE-SAME: 0x83,0xe3,0xff,0xff]
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# CHECK-LE: xxsplti32dx 63, 1, 4294967295 # encoding: [0xff,0xff,0x00,0x05,
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# CHECK-LE-SAME: 0xff,0xff,0xe3,0x83]
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xxsplti32dx 63, 1, 4294967295
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# CHECK-BE: xxsplti32dx 63, 1, -1 # encoding: [0x05,0x00,0xff,0xff,
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# CHECK-BE-SAME: 0x83,0xe3,0xff,0xff]
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# CHECK-LE: xxsplti32dx 63, 1, -1 # encoding: [0xff,0xff,0x00,0x05,
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# CHECK-LE-SAME: 0xff,0xff,0xe3,0x83]
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xxsplti32dx 63, 1, -1
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# CHECK-BE: xxpermx 6, 63, 21, 34, 2 # encoding: [0x05,0x00,0x00,0x02,
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# CHECK-BE-SAME: 0x88,0xdf,0xa8,0x8c]
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# CHECK-LE: xxpermx 6, 63, 21, 34, 2 # encoding: [0x02,0x00,0x00,0x05,
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# CHECK-LE-SAME: 0x8c,0xa8,0xdf,0x88]
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xxpermx 6, 63, 21, 34, 2
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# CHECK-BE: xxblendvb 6, 63, 21, 34 # encoding: [0x05,0x00,0x00,0x00,
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# CHECK-BE-SAME: 0x84,0xdf,0xa8,0x8c]
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# CHECK-LE: xxblendvb 6, 63, 21, 34 # encoding: [0x00,0x00,0x00,0x05,
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# CHECK-LE-SAME: 0x8c,0xa8,0xdf,0x84]
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xxblendvb 6, 63, 21, 34
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# CHECK-BE: xxblendvh 6, 63, 21, 34 # encoding: [0x05,0x00,0x00,0x00,
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# CHECK-BE-SAME: 0x84,0xdf,0xa8,0x9c]
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# CHECK-LE: xxblendvh 6, 63, 21, 34 # encoding: [0x00,0x00,0x00,0x05,
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# CHECK-LE-SAME: 0x9c,0xa8,0xdf,0x84]
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xxblendvh 6, 63, 21, 34
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# CHECK-BE: xxblendvw 6, 63, 21, 34 # encoding: [0x05,0x00,0x00,0x00,
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# CHECK-BE-SAME: 0x84,0xdf,0xa8,0xac]
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# CHECK-LE: xxblendvw 6, 63, 21, 34 # encoding: [0x00,0x00,0x00,0x05,
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# CHECK-LE-SAME: 0xac,0xa8,0xdf,0x84]
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xxblendvw 6, 63, 21, 34
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# CHECK-BE: xxblendvd 6, 63, 21, 34 # encoding: [0x05,0x00,0x00,0x00,
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# CHECK-BE-SAME: 0x84,0xdf,0xa8,0xbc]
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# CHECK-LE: xxblendvd 6, 63, 21, 34 # encoding: [0x00,0x00,0x00,0x05,
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# CHECK-LE-SAME: 0xbc,0xa8,0xdf,0x84]
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xxblendvd 6, 63, 21, 34
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# CHECK-BE: vsldbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x56]
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# CHECK-LE: vsldbi 2, 3, 4, 5 # encoding: [0x56,0x21,0x43,0x10]
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vsldbi 2, 3, 4, 5
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# CHECK-BE: vsrdbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x23,0x56]
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# CHECK-LE: vsrdbi 2, 3, 4, 5 # encoding: [0x56,0x23,0x43,0x10]
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vsrdbi 2, 3, 4, 5
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