forked from OSchip/llvm-project
[X86] Remove patterns and ISD nodes for the old scalar FMA intrinsic lowering.
We now use llvm.fma.f32/f64 or llvm.x86.fmadd.f32/f64 intrinsics that use scalar types rather than vector types. So we don't these special ISD nodes that operate on the lowest element of a vector. llvm-svn: 336883
This commit is contained in:
Craig Topper
parent
e2ce2a5c86
commit
73347ec081
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@ -26055,22 +26055,6 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::FNMSUB_RND: return "X86ISD::FNMSUB_RND";
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case X86ISD::FMADDSUB_RND: return "X86ISD::FMADDSUB_RND";
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case X86ISD::FMSUBADD_RND: return "X86ISD::FMSUBADD_RND";
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case X86ISD::FMADDS1: return "X86ISD::FMADDS1";
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case X86ISD::FNMADDS1: return "X86ISD::FNMADDS1";
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case X86ISD::FMSUBS1: return "X86ISD::FMSUBS1";
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case X86ISD::FNMSUBS1: return "X86ISD::FNMSUBS1";
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case X86ISD::FMADDS1_RND: return "X86ISD::FMADDS1_RND";
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case X86ISD::FNMADDS1_RND: return "X86ISD::FNMADDS1_RND";
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case X86ISD::FMSUBS1_RND: return "X86ISD::FMSUBS1_RND";
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case X86ISD::FNMSUBS1_RND: return "X86ISD::FNMSUBS1_RND";
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case X86ISD::FMADDS3: return "X86ISD::FMADDS3";
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case X86ISD::FNMADDS3: return "X86ISD::FNMADDS3";
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case X86ISD::FMSUBS3: return "X86ISD::FMSUBS3";
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case X86ISD::FNMSUBS3: return "X86ISD::FNMSUBS3";
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case X86ISD::FMADDS3_RND: return "X86ISD::FMADDS3_RND";
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case X86ISD::FNMADDS3_RND: return "X86ISD::FNMADDS3_RND";
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case X86ISD::FMSUBS3_RND: return "X86ISD::FMSUBS3_RND";
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case X86ISD::FNMSUBS3_RND: return "X86ISD::FNMSUBS3_RND";
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case X86ISD::VPMADD52H: return "X86ISD::VPMADD52H";
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case X86ISD::VPMADD52L: return "X86ISD::VPMADD52L";
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case X86ISD::VRNDSCALE: return "X86ISD::VRNDSCALE";
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@ -37707,28 +37691,12 @@ static unsigned negateFMAOpcode(unsigned Opcode, bool NegMul, bool NegAcc) {
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default: llvm_unreachable("Unexpected opcode");
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case ISD::FMA: Opcode = X86ISD::FNMADD; break;
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case X86ISD::FMADD_RND: Opcode = X86ISD::FNMADD_RND; break;
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case X86ISD::FMADDS1: Opcode = X86ISD::FNMADDS1; break;
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case X86ISD::FMADDS3: Opcode = X86ISD::FNMADDS3; break;
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case X86ISD::FMADDS1_RND: Opcode = X86ISD::FNMADDS1_RND; break;
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case X86ISD::FMADDS3_RND: Opcode = X86ISD::FNMADDS3_RND; break;
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case X86ISD::FMSUB: Opcode = X86ISD::FNMSUB; break;
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case X86ISD::FMSUB_RND: Opcode = X86ISD::FNMSUB_RND; break;
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case X86ISD::FMSUBS1: Opcode = X86ISD::FNMSUBS1; break;
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case X86ISD::FMSUBS3: Opcode = X86ISD::FNMSUBS3; break;
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case X86ISD::FMSUBS1_RND: Opcode = X86ISD::FNMSUBS1_RND; break;
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case X86ISD::FMSUBS3_RND: Opcode = X86ISD::FNMSUBS3_RND; break;
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case X86ISD::FNMADD: Opcode = ISD::FMA; break;
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case X86ISD::FNMADD_RND: Opcode = X86ISD::FMADD_RND; break;
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case X86ISD::FNMADDS1: Opcode = X86ISD::FMADDS1; break;
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case X86ISD::FNMADDS3: Opcode = X86ISD::FMADDS3; break;
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case X86ISD::FNMADDS1_RND: Opcode = X86ISD::FMADDS1_RND; break;
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case X86ISD::FNMADDS3_RND: Opcode = X86ISD::FMADDS3_RND; break;
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case X86ISD::FNMSUB: Opcode = X86ISD::FMSUB; break;
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case X86ISD::FNMSUB_RND: Opcode = X86ISD::FMSUB_RND; break;
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case X86ISD::FNMSUBS1: Opcode = X86ISD::FMSUBS1; break;
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case X86ISD::FNMSUBS3: Opcode = X86ISD::FMSUBS3; break;
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case X86ISD::FNMSUBS1_RND: Opcode = X86ISD::FMSUBS1_RND; break;
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case X86ISD::FNMSUBS3_RND: Opcode = X86ISD::FMSUBS3_RND; break;
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}
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}
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@ -37737,28 +37705,12 @@ static unsigned negateFMAOpcode(unsigned Opcode, bool NegMul, bool NegAcc) {
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default: llvm_unreachable("Unexpected opcode");
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case ISD::FMA: Opcode = X86ISD::FMSUB; break;
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case X86ISD::FMADD_RND: Opcode = X86ISD::FMSUB_RND; break;
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case X86ISD::FMADDS1: Opcode = X86ISD::FMSUBS1; break;
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case X86ISD::FMADDS3: Opcode = X86ISD::FMSUBS3; break;
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case X86ISD::FMADDS1_RND: Opcode = X86ISD::FMSUBS1_RND; break;
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case X86ISD::FMADDS3_RND: Opcode = X86ISD::FMSUBS3_RND; break;
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case X86ISD::FMSUB: Opcode = ISD::FMA; break;
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case X86ISD::FMSUB_RND: Opcode = X86ISD::FMADD_RND; break;
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case X86ISD::FMSUBS1: Opcode = X86ISD::FMADDS1; break;
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case X86ISD::FMSUBS3: Opcode = X86ISD::FMADDS3; break;
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case X86ISD::FMSUBS1_RND: Opcode = X86ISD::FMADDS1_RND; break;
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case X86ISD::FMSUBS3_RND: Opcode = X86ISD::FMADDS3_RND; break;
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case X86ISD::FNMADD: Opcode = X86ISD::FNMSUB; break;
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case X86ISD::FNMADD_RND: Opcode = X86ISD::FNMSUB_RND; break;
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case X86ISD::FNMADDS1: Opcode = X86ISD::FNMSUBS1; break;
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case X86ISD::FNMADDS3: Opcode = X86ISD::FNMSUBS3; break;
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case X86ISD::FNMADDS1_RND: Opcode = X86ISD::FNMSUBS1_RND; break;
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case X86ISD::FNMADDS3_RND: Opcode = X86ISD::FNMSUBS3_RND; break;
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case X86ISD::FNMSUB: Opcode = X86ISD::FNMADD; break;
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case X86ISD::FNMSUB_RND: Opcode = X86ISD::FNMADD_RND; break;
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case X86ISD::FNMSUBS1: Opcode = X86ISD::FNMADDS1; break;
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case X86ISD::FNMSUBS3: Opcode = X86ISD::FNMADDS3; break;
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case X86ISD::FNMSUBS1_RND: Opcode = X86ISD::FNMADDS1_RND; break;
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case X86ISD::FNMSUBS3_RND: Opcode = X86ISD::FNMADDS3_RND; break;
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}
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}
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@ -37803,28 +37755,11 @@ static SDValue combineFMA(SDNode *N, SelectionDAG &DAG,
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return false;
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};
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bool IsScalarS1 = N->getOpcode() == X86ISD::FMADDS1 ||
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N->getOpcode() == X86ISD::FMSUBS1 ||
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N->getOpcode() == X86ISD::FNMADDS1 ||
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N->getOpcode() == X86ISD::FNMSUBS1 ||
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N->getOpcode() == X86ISD::FMADDS1_RND ||
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N->getOpcode() == X86ISD::FMSUBS1_RND ||
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N->getOpcode() == X86ISD::FNMADDS1_RND ||
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N->getOpcode() == X86ISD::FNMSUBS1_RND;
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bool IsScalarS3 = N->getOpcode() == X86ISD::FMADDS3 ||
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N->getOpcode() == X86ISD::FMSUBS3 ||
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N->getOpcode() == X86ISD::FNMADDS3 ||
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N->getOpcode() == X86ISD::FNMSUBS3 ||
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N->getOpcode() == X86ISD::FMADDS3_RND ||
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N->getOpcode() == X86ISD::FMSUBS3_RND ||
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N->getOpcode() == X86ISD::FNMADDS3_RND ||
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N->getOpcode() == X86ISD::FNMSUBS3_RND;
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// Do not convert the passthru input of scalar intrinsics.
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// FIXME: We could allow negations of the lower element only.
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bool NegA = !IsScalarS1 && invertIfNegative(A);
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bool NegA = invertIfNegative(A);
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bool NegB = invertIfNegative(B);
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bool NegC = !IsScalarS3 && invertIfNegative(C);
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bool NegC = invertIfNegative(C);
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if (!NegA && !NegB && !NegC)
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return SDValue();
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@ -39450,28 +39385,12 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::VZEXT_MOVL:
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case ISD::VECTOR_SHUFFLE: return combineShuffle(N, DAG, DCI,Subtarget);
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case X86ISD::FMADD_RND:
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case X86ISD::FMADDS1_RND:
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case X86ISD::FMADDS3_RND:
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case X86ISD::FMADDS1:
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case X86ISD::FMADDS3:
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case X86ISD::FMSUB:
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case X86ISD::FMSUB_RND:
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case X86ISD::FMSUBS1_RND:
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case X86ISD::FMSUBS3_RND:
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case X86ISD::FMSUBS1:
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case X86ISD::FMSUBS3:
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case X86ISD::FNMADD:
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case X86ISD::FNMADD_RND:
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case X86ISD::FNMADDS1_RND:
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case X86ISD::FNMADDS3_RND:
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case X86ISD::FNMADDS1:
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case X86ISD::FNMADDS3:
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case X86ISD::FNMSUB:
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case X86ISD::FNMSUB_RND:
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case X86ISD::FNMSUBS1_RND:
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case X86ISD::FNMSUBS3_RND:
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case X86ISD::FNMSUBS1:
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case X86ISD::FNMSUBS3:
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case ISD::FMA: return combineFMA(N, DAG, Subtarget);
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case X86ISD::FMADDSUB_RND:
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case X86ISD::FMSUBADD_RND:
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@ -499,19 +499,6 @@ namespace llvm {
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FMADDSUB_RND,
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FMSUBADD_RND,
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// Scalar intrinsic FMA.
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FMADDS1, FMADDS3,
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FNMADDS1, FNMADDS3,
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FMSUBS1, FMSUBS3,
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FNMSUBS1, FNMSUBS3,
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// Scalar intrinsic FMA with rounding mode.
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// Two versions, passthru bits on op1 or op3.
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FMADDS1_RND, FMADDS3_RND,
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FNMADDS1_RND, FNMADDS3_RND,
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FMSUBS1_RND, FMSUBS3_RND,
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FNMSUBS1_RND, FNMSUBS3_RND,
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// Compress and expand.
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COMPRESS,
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EXPAND,
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@ -6702,22 +6702,22 @@ defm VFNMSUB132 : avx512_fma3p_132_f<0x9E, "vfnmsub132", X86Fnmsub, X86FnmsubR
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// Scalar FMA
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multiclass avx512_fma3s_common<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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dag RHS_VEC_r, dag RHS_VEC_m, dag RHS_VEC_rb,
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dag RHS_r, dag RHS_m, dag RHS_b, bit MaskOnlyReg> {
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let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
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defm r_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3), OpcodeStr,
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"$src3, $src2", "$src2, $src3", RHS_VEC_r, 1, 1>,
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"$src3, $src2", "$src2, $src3", (null_frag), 1, 1>,
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AVX512FMA3Base, Sched<[SchedWriteFMA.Scl]>;
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let mayLoad = 1 in
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defm m_Int: AVX512_maskable_3src_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.IntScalarMemOp:$src3), OpcodeStr,
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"$src3, $src2", "$src2, $src3", RHS_VEC_m, 1, 1>,
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"$src3, $src2", "$src2, $src3", (null_frag), 1, 1>,
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AVX512FMA3Base, Sched<[SchedWriteFMA.Scl.Folded, ReadAfterLd]>;
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defm rb_Int: AVX512_maskable_3src_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3, AVX512RC:$rc),
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OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", RHS_VEC_rb, 1, 1>,
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OpcodeStr, "$rc, $src3, $src2", "$src2, $src3, $rc", (null_frag), 1, 1>,
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AVX512FMA3Base, EVEX_B, EVEX_RC, Sched<[SchedWriteFMA.Scl]>;
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let isCodeGenOnly = 1, isCommutable = 1 in {
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@ -6744,18 +6744,11 @@ let Constraints = "$src1 = $dst", hasSideEffects = 0 in {
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multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd,
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SDNode OpNodes1, SDNode OpNodeRnds1, SDNode OpNodes3,
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SDNode OpNodeRnds3, X86VectorVTInfo _,
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string SUFF> {
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X86VectorVTInfo _, string SUFF> {
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let ExeDomain = _.ExeDomain in {
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defm NAME#213#SUFF#Z: avx512_fma3s_common<opc213, OpcodeStr#"213"#_.Suffix, _,
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// Operands for intrinsic are in 123 order to preserve passthu
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// semantics.
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(_.VT (OpNodes1 _.RC:$src1, _.RC:$src2, _.RC:$src3)),
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(_.VT (OpNodes1 _.RC:$src1, _.RC:$src2,
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_.ScalarIntMemCPat:$src3)),
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(_.VT (OpNodeRnds1 _.RC:$src1, _.RC:$src2, _.RC:$src3,
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(i32 imm:$rc))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
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_.FRC:$src3))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src1,
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@ -6764,11 +6757,6 @@ multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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_.FRC:$src3, (i32 imm:$rc)))), 0>;
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defm NAME#231#SUFF#Z: avx512_fma3s_common<opc231, OpcodeStr#"231"#_.Suffix, _,
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(_.VT (OpNodes3 _.RC:$src2, _.RC:$src3, _.RC:$src1)),
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(_.VT (OpNodes3 _.RC:$src2, _.ScalarIntMemCPat:$src3,
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_.RC:$src1)),
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(_.VT ( OpNodeRnds3 _.RC:$src2, _.RC:$src3, _.RC:$src1,
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(i32 imm:$rc))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2, _.FRC:$src3,
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_.FRC:$src1))),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src2,
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@ -6779,10 +6767,6 @@ multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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// One pattern is 312 order so that the load is in a different place from the
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// 213 and 231 patterns this helps tablegen's duplicate pattern detection.
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defm NAME#132#SUFF#Z: avx512_fma3s_common<opc132, OpcodeStr#"132"#_.Suffix, _,
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(null_frag),
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(_.VT (OpNodes1 _.RC:$src1, _.ScalarIntMemCPat:$src3,
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_.RC:$src2)),
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(null_frag),
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(set _.FRC:$dst, (_.EltVT (OpNode _.FRC:$src1, _.FRC:$src3,
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_.FRC:$src2))),
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(set _.FRC:$dst, (_.EltVT (OpNode (_.ScalarLdFrag addr:$src3),
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@ -6793,33 +6777,21 @@ multiclass avx512_fma3s_all<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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}
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multiclass avx512_fma3s<bits<8> opc213, bits<8> opc231, bits<8> opc132,
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string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd,
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SDNode OpNodes1, SDNode OpNodeRnds1, SDNode OpNodes3,
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SDNode OpNodeRnds3> {
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string OpcodeStr, SDNode OpNode, SDNode OpNodeRnd> {
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let Predicates = [HasAVX512] in {
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defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
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OpNodeRnd, OpNodes1, OpNodeRnds1, OpNodes3,
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OpNodeRnds3, f32x_info, "SS">,
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OpNodeRnd, f32x_info, "SS">,
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EVEX_CD8<32, CD8VT1>, VEX_LIG;
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defm NAME : avx512_fma3s_all<opc213, opc231, opc132, OpcodeStr, OpNode,
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OpNodeRnd, OpNodes1, OpNodeRnds1, OpNodes3,
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OpNodeRnds3, f64x_info, "SD">,
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OpNodeRnd, f64x_info, "SD">,
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EVEX_CD8<64, CD8VT1>, VEX_LIG, VEX_W;
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}
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}
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defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd,
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X86Fmadds1, X86FmaddRnds1, X86Fmadds3,
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X86FmaddRnds3>;
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defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd,
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X86Fmsubs1, X86FmsubRnds1, X86Fmsubs3,
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X86FmsubRnds3>;
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defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd,
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X86Fnmadds1, X86FnmaddRnds1, X86Fnmadds3,
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X86FnmaddRnds3>;
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defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd,
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X86Fnmsubs1, X86FnmsubRnds1, X86Fnmsubs3,
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X86FnmsubRnds3>;
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defm VFMADD : avx512_fma3s<0xA9, 0xB9, 0x99, "vfmadd", X86Fmadd, X86FmaddRnd>;
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defm VFMSUB : avx512_fma3s<0xAB, 0xBB, 0x9B, "vfmsub", X86Fmsub, X86FmsubRnd>;
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defm VFNMADD : avx512_fma3s<0xAD, 0xBD, 0x9D, "vfnmadd", X86Fnmadd, X86FnmaddRnd>;
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defm VFNMSUB : avx512_fma3s<0xAF, 0xBF, 0x9F, "vfnmsub", X86Fnmsub, X86FnmsubRnd>;
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multiclass avx512_scalar_fma_patterns<SDNode Op, SDNode RndOp, string Prefix,
|
||||
string Suffix, SDNode Move,
|
||||
|
|
|
|||
|
|
@ -304,8 +304,7 @@ multiclass fma3s_int_forms<bits<8> opc132, bits<8> opc213, bits<8> opc231,
|
|||
}
|
||||
|
||||
multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
|
||||
string OpStr, SDNode OpNodeIntrin, SDNode OpNode,
|
||||
X86FoldableSchedWrite sched> {
|
||||
string OpStr, SDNode OpNode, X86FoldableSchedWrite sched> {
|
||||
let ExeDomain = SSEPackedSingle in
|
||||
defm NAME : fma3s_forms<opc132, opc213, opc231, OpStr, "ss", "SS", OpNode,
|
||||
FR32, f32mem, sched>,
|
||||
|
|
@ -319,14 +318,14 @@ multiclass fma3s<bits<8> opc132, bits<8> opc213, bits<8> opc231,
|
|||
VR128, sdmem, sched>, VEX_W;
|
||||
}
|
||||
|
||||
defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", X86Fmadds1, X86Fmadd,
|
||||
defm VFMADD : fma3s<0x99, 0xA9, 0xB9, "vfmadd", X86Fmadd,
|
||||
SchedWriteFMA.Scl>, VEX_LIG;
|
||||
defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", X86Fmsubs1, X86Fmsub,
|
||||
defm VFMSUB : fma3s<0x9B, 0xAB, 0xBB, "vfmsub", X86Fmsub,
|
||||
SchedWriteFMA.Scl>, VEX_LIG;
|
||||
|
||||
defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", X86Fnmadds1, X86Fnmadd,
|
||||
defm VFNMADD : fma3s<0x9D, 0xAD, 0xBD, "vfnmadd", X86Fnmadd,
|
||||
SchedWriteFMA.Scl>, VEX_LIG;
|
||||
defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", X86Fnmsubs1, X86Fnmsub,
|
||||
defm VFNMSUB : fma3s<0x9F, 0xAF, 0xBF, "vfnmsub", X86Fnmsub,
|
||||
SchedWriteFMA.Scl>, VEX_LIG;
|
||||
|
||||
multiclass scalar_fma_patterns<SDNode Op, string Prefix, string Suffix,
|
||||
|
|
|
|||
|
|
@ -479,29 +479,6 @@ def X86FnmsubRnd : SDNode<"X86ISD::FNMSUB_RND", SDTFmaRound, [SDNPCommutat
|
|||
def X86FmaddsubRnd : SDNode<"X86ISD::FMADDSUB_RND", SDTFmaRound, [SDNPCommutative]>;
|
||||
def X86FmsubaddRnd : SDNode<"X86ISD::FMSUBADD_RND", SDTFmaRound, [SDNPCommutative]>;
|
||||
|
||||
// Scalar FMA intrinsics with passthru bits in operand 1.
|
||||
def X86Fmadds1 : SDNode<"X86ISD::FMADDS1", SDTFPTernaryOp>;
|
||||
def X86Fnmadds1 : SDNode<"X86ISD::FNMADDS1", SDTFPTernaryOp>;
|
||||
def X86Fmsubs1 : SDNode<"X86ISD::FMSUBS1", SDTFPTernaryOp>;
|
||||
def X86Fnmsubs1 : SDNode<"X86ISD::FNMSUBS1", SDTFPTernaryOp>;
|
||||
|
||||
// Scalar FMA intrinsics with passthru bits in operand 1.
|
||||
def X86FmaddRnds1 : SDNode<"X86ISD::FMADDS1_RND", SDTFmaRound>;
|
||||
def X86FnmaddRnds1 : SDNode<"X86ISD::FNMADDS1_RND", SDTFmaRound>;
|
||||
def X86FmsubRnds1 : SDNode<"X86ISD::FMSUBS1_RND", SDTFmaRound>;
|
||||
def X86FnmsubRnds1 : SDNode<"X86ISD::FNMSUBS1_RND", SDTFmaRound>;
|
||||
|
||||
def X86Fmadds3 : SDNode<"X86ISD::FMADDS3", SDTFPTernaryOp, [SDNPCommutative]>;
|
||||
def X86Fnmadds3 : SDNode<"X86ISD::FNMADDS3", SDTFPTernaryOp, [SDNPCommutative]>;
|
||||
def X86Fmsubs3 : SDNode<"X86ISD::FMSUBS3", SDTFPTernaryOp, [SDNPCommutative]>;
|
||||
def X86Fnmsubs3 : SDNode<"X86ISD::FNMSUBS3", SDTFPTernaryOp, [SDNPCommutative]>;
|
||||
|
||||
// Scalar FMA intrinsics with passthru bits in operand 3.
|
||||
def X86FmaddRnds3 : SDNode<"X86ISD::FMADDS3_RND", SDTFmaRound, [SDNPCommutative]>;
|
||||
def X86FnmaddRnds3 : SDNode<"X86ISD::FNMADDS3_RND", SDTFmaRound, [SDNPCommutative]>;
|
||||
def X86FmsubRnds3 : SDNode<"X86ISD::FMSUBS3_RND", SDTFmaRound, [SDNPCommutative]>;
|
||||
def X86FnmsubRnds3 : SDNode<"X86ISD::FNMSUBS3_RND", SDTFmaRound, [SDNPCommutative]>;
|
||||
|
||||
def SDTIFma : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0,1>,
|
||||
SDTCisSameAs<1,2>, SDTCisSameAs<1,3>]>;
|
||||
def x86vpmadd52l : SDNode<"X86ISD::VPMADD52L", SDTIFma, [SDNPCommutative]>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue