forked from OSchip/llvm-project
[PowerPC] Avoid scalarization of vector truncate
The PowerPC code generator currently scalarizes vector truncates that would fit in a vector register, resulting in vector extracts, scalar operations, and vector merges. This patch custom lowers a vector truncate that would fit in a register to a vector shuffle instead. Differential Revision: https://reviews.llvm.org/D56507 llvm-svn: 353724
This commit is contained in:
Roland Froese
parent
ebdb021031
commit
732fe22454
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@ -118,6 +118,8 @@ STATISTIC(NumSiblingCalls, "Number of sibling calls");
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static bool isNByteElemShuffleMask(ShuffleVectorSDNode *, unsigned, int);
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static SDValue widenVec(SelectionDAG &DAG, SDValue Vec, const SDLoc &dl);
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// FIXME: Remove this once the bug has been fixed!
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extern cl::opt<bool> ANDIGlueBug;
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@ -639,6 +641,14 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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// with merges, splats, etc.
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setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
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// Vector truncates to sub-word integer that fit in an Altivec/VSX register
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// are cheap, so handle them before they get expanded to scalar.
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setOperationAction(ISD::TRUNCATE, MVT::v8i8, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v4i8, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v2i8, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom);
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setOperationAction(ISD::TRUNCATE, MVT::v2i16, Custom);
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setOperationAction(ISD::AND , MVT::v4i32, Legal);
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setOperationAction(ISD::OR , MVT::v4i32, Legal);
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setOperationAction(ISD::XOR , MVT::v4i32, Legal);
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@ -6794,6 +6804,61 @@ SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
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Op.getOperand(0));
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}
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SDValue PPCTargetLowering::LowerTRUNCATEVector(SDValue Op,
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SelectionDAG &DAG) const {
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// Implements a vector truncate that fits in a vector register as a shuffle.
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// We want to legalize vector truncates down to where the source fits in
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// a vector register (and target is therefore smaller than vector register
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// size). At that point legalization will try to custom lower the sub-legal
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// result and get here - where we can contain the truncate as a single target
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// operation.
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// For example a trunc <2 x i16> to <2 x i8> could be visualized as follows:
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// <MSB1|LSB1, MSB2|LSB2> to <LSB1, LSB2>
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//
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// We will implement it for big-endian ordering as this (where x denotes
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// undefined):
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// < MSB1|LSB1, MSB2|LSB2, uu, uu, uu, uu, uu, uu> to
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// < LSB1, LSB2, u, u, u, u, u, u, u, u, u, u, u, u, u, u>
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//
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// The same operation in little-endian ordering will be:
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// <uu, uu, uu, uu, uu, uu, LSB2|MSB2, LSB1|MSB1> to
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// <u, u, u, u, u, u, u, u, u, u, u, u, u, u, LSB2, LSB1>
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assert(Op.getValueType().isVector() && "Vector type expected.");
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SDLoc DL(Op);
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SDValue N1 = Op.getOperand(0);
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unsigned SrcSize = N1.getValueType().getSizeInBits();
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assert(SrcSize <= 128 && "Source must fit in an Altivec/VSX vector");
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SDValue WideSrc = SrcSize == 128 ? N1 : widenVec(DAG, N1, DL);
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EVT TrgVT = Op.getValueType();
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unsigned TrgNumElts = TrgVT.getVectorNumElements();
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EVT EltVT = TrgVT.getVectorElementType();
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unsigned WideNumElts = 128 / EltVT.getSizeInBits();
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EVT WideVT = EVT::getVectorVT(*DAG.getContext(), EltVT, WideNumElts);
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// First list the elements we want to keep.
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unsigned SizeMult = SrcSize / TrgVT.getSizeInBits();
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SmallVector<int, 16> ShuffV;
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if (Subtarget.isLittleEndian())
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for (unsigned i = 0; i < TrgNumElts; ++i)
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ShuffV.push_back(i * SizeMult);
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else
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for (unsigned i = 1; i <= TrgNumElts; ++i)
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ShuffV.push_back(i * SizeMult - 1);
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// Populate the remaining elements with undefs.
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for (unsigned i = TrgNumElts; i < WideNumElts; ++i)
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// ShuffV.push_back(i + WideNumElts);
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ShuffV.push_back(WideNumElts + 1);
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SDValue Conv = DAG.getNode(ISD::BITCAST, DL, WideVT, WideSrc);
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return DAG.getVectorShuffle(WideVT, DL, Conv, DAG.getUNDEF(WideVT), ShuffV);
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}
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/// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
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/// possible.
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SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
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@ -9641,6 +9706,14 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
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return;
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Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
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return;
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case ISD::TRUNCATE: {
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EVT TrgVT = N->getValueType(0);
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if (TrgVT.isVector() &&
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isOperationCustom(N->getOpcode(), TrgVT) &&
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N->getOperand(0).getValueType().getSizeInBits() <= 128)
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Results.push_back(LowerTRUNCATEVector(SDValue(N, 0), DAG));
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return;
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}
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case ISD::BITCAST:
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// Don't handle bitcast here.
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return;
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@ -952,6 +952,8 @@ namespace llvm {
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SDValue LowerINT_TO_FPVector(SDValue Op, SelectionDAG &DAG,
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const SDLoc &dl) const;
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SDValue LowerTRUNCATEVector(SDValue Op, SelectionDAG &DAG) const;
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SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
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SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
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@ -10,90 +10,17 @@ define void @test8i8(<8 x i8>* nocapture %Sink, <8 x i16>* nocapture readonly %S
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; CHECK-LABEL: test8i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lvx v2, 0, r4
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; CHECK-NEXT: mfvsrd r4, v2
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; CHECK-NEXT: xxswapd vs0, v2
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; CHECK-NEXT: clrldi r5, r4, 48
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; CHECK-NEXT: mtvsrd f1, r5
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; CHECK-NEXT: rldicl r5, r4, 48, 48
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; CHECK-NEXT: mtvsrd f2, r5
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; CHECK-NEXT: rldicl r5, r4, 32, 48
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; CHECK-NEXT: rldicl r4, r4, 16, 48
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; CHECK-NEXT: mtvsrd f3, r5
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; CHECK-NEXT: xxswapd v2, vs1
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; CHECK-NEXT: mfvsrd r5, f0
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; CHECK-NEXT: xxswapd v3, vs2
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; CHECK-NEXT: mtvsrd f0, r4
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; CHECK-NEXT: clrldi r4, r5, 48
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; CHECK-NEXT: mtvsrd f1, r4
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; CHECK-NEXT: rldicl r4, r5, 48, 48
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; CHECK-NEXT: xxswapd v4, vs0
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; CHECK-NEXT: mtvsrd f2, r4
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; CHECK-NEXT: rldicl r4, r5, 32, 48
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; CHECK-NEXT: rldicl r5, r5, 16, 48
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; CHECK-NEXT: vmrglb v2, v3, v2
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; CHECK-NEXT: xxswapd v3, vs3
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; CHECK-NEXT: mtvsrd f3, r4
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; CHECK-NEXT: xxswapd v5, vs1
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; CHECK-NEXT: mtvsrd f0, r5
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; CHECK-NEXT: xxswapd v0, vs2
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; CHECK-NEXT: xxswapd v1, vs3
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; CHECK-NEXT: vmrglb v3, v4, v3
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; CHECK-NEXT: xxswapd v6, vs0
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; CHECK-NEXT: vmrglb v4, v0, v5
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; CHECK-NEXT: vmrglb v5, v6, v1
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; CHECK-NEXT: vmrglh v2, v3, v2
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; CHECK-NEXT: vmrglh v3, v5, v4
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; CHECK-NEXT: vmrglw v2, v2, v3
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; CHECK-NEXT: vpkuhum v2, v2, v2
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; CHECK-NEXT: xxswapd vs0, v2
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; CHECK-NEXT: stfdx f0, 0, r3
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test8i8:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxvw4x vs0, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -32
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; CHECK-BE-NEXT: stxvw4x vs0, 0, r4
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; CHECK-BE-NEXT: lhz r4, -18(r1)
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; CHECK-BE-NEXT: stb r4, -48(r1)
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; CHECK-BE-NEXT: lhz r4, -20(r1)
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; CHECK-BE-NEXT: stb r4, -64(r1)
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; CHECK-BE-NEXT: lhz r4, -22(r1)
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; CHECK-BE-NEXT: stb r4, -80(r1)
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; CHECK-BE-NEXT: lhz r4, -24(r1)
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; CHECK-BE-NEXT: stb r4, -96(r1)
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; CHECK-BE-NEXT: lhz r4, -26(r1)
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; CHECK-BE-NEXT: stb r4, -112(r1)
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; CHECK-BE-NEXT: lhz r4, -28(r1)
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; CHECK-BE-NEXT: stb r4, -128(r1)
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; CHECK-BE-NEXT: lhz r4, -30(r1)
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; CHECK-BE-NEXT: stb r4, -144(r1)
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; CHECK-BE-NEXT: lhz r4, -32(r1)
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; CHECK-BE-NEXT: stb r4, -160(r1)
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; CHECK-BE-NEXT: addi r4, r1, -48
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; CHECK-BE-NEXT: lxvw4x v2, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -64
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; CHECK-BE-NEXT: lxvw4x v3, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -80
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; CHECK-BE-NEXT: lxvw4x v4, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -96
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; CHECK-BE-NEXT: lxvw4x v5, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -112
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; CHECK-BE-NEXT: lxvw4x v0, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -128
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; CHECK-BE-NEXT: lxvw4x v1, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -144
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; CHECK-BE-NEXT: lxvw4x v6, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -160
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; CHECK-BE-NEXT: lxvw4x v7, 0, r4
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; CHECK-BE-NEXT: vmrghb v2, v3, v2
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; CHECK-BE-NEXT: vmrghb v3, v5, v4
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; CHECK-BE-NEXT: vmrghb v4, v1, v0
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; CHECK-BE-NEXT: addi r4, r1, -16
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; CHECK-BE-NEXT: vmrghh v2, v3, v2
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; CHECK-BE-NEXT: vmrghb v5, v7, v6
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; CHECK-BE-NEXT: vmrghh v3, v5, v4
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; CHECK-BE-NEXT: vmrghw v2, v3, v2
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; CHECK-BE-NEXT: stxvd2x v2, 0, r4
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; CHECK-BE-NEXT: addi r5, r1, -16
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; CHECK-BE-NEXT: vpkuhum v2, v2, v2
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; CHECK-BE-NEXT: stxvd2x v2, 0, r5
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; CHECK-BE-NEXT: ld r4, -16(r1)
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; CHECK-BE-NEXT: std r4, 0(r3)
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; CHECK-BE-NEXT: blr
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@ -108,53 +35,17 @@ define void @test4i8(<4 x i8>* nocapture %Sink, <4 x i16>* nocapture readonly %S
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; CHECK-LABEL: test4i8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lvx v2, 0, r4
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; CHECK-NEXT: xxswapd vs0, v2
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; CHECK-NEXT: mfvsrd r4, f0
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; CHECK-NEXT: clrldi r5, r4, 48
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; CHECK-NEXT: mtvsrd f0, r5
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; CHECK-NEXT: rldicl r5, r4, 48, 48
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; CHECK-NEXT: mtvsrd f1, r5
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; CHECK-NEXT: rldicl r5, r4, 32, 48
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; CHECK-NEXT: rldicl r4, r4, 16, 48
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; CHECK-NEXT: mtvsrd f2, r5
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; CHECK-NEXT: xxswapd v2, vs0
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; CHECK-NEXT: mtvsrd f3, r4
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; CHECK-NEXT: xxswapd v3, vs1
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; CHECK-NEXT: xxswapd v4, vs2
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; CHECK-NEXT: xxswapd v5, vs3
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; CHECK-NEXT: vmrglb v2, v3, v2
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; CHECK-NEXT: vmrglb v3, v5, v4
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; CHECK-NEXT: vmrglh v2, v3, v2
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; CHECK-NEXT: vpkuhum v2, v2, v2
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; CHECK-NEXT: xxsldwi vs0, v2, v2, 2
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; CHECK-NEXT: stfiwx f0, 0, r3
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test4i8:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxvw4x vs0, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -32
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; CHECK-BE-NEXT: stxvw4x vs0, 0, r4
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; CHECK-BE-NEXT: lhz r4, -26(r1)
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; CHECK-BE-NEXT: stb r4, -48(r1)
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; CHECK-BE-NEXT: lhz r4, -28(r1)
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; CHECK-BE-NEXT: stb r4, -64(r1)
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; CHECK-BE-NEXT: lhz r4, -30(r1)
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; CHECK-BE-NEXT: stb r4, -80(r1)
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; CHECK-BE-NEXT: lhz r4, -32(r1)
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; CHECK-BE-NEXT: stb r4, -96(r1)
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; CHECK-BE-NEXT: addi r4, r1, -48
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; CHECK-BE-NEXT: lxvw4x v2, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -64
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; CHECK-BE-NEXT: lxvw4x v3, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -80
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; CHECK-BE-NEXT: lxvw4x v4, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -96
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; CHECK-BE-NEXT: lxvw4x v5, 0, r4
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; CHECK-BE-NEXT: vmrghb v2, v3, v2
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; CHECK-BE-NEXT: addi r4, r1, -16
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; CHECK-BE-NEXT: vmrghb v3, v5, v4
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; CHECK-BE-NEXT: vmrghh v2, v3, v2
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; CHECK-BE-NEXT: stxvw4x v2, 0, r4
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; CHECK-BE-NEXT: addi r5, r1, -16
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; CHECK-BE-NEXT: vpkuhum v2, v2, v2
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; CHECK-BE-NEXT: stxvw4x v2, 0, r5
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; CHECK-BE-NEXT: lwz r4, -16(r1)
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; CHECK-BE-NEXT: stw r4, 0(r3)
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; CHECK-BE-NEXT: blr
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@ -168,54 +59,23 @@ entry:
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define void @test4i8w(<4 x i8>* nocapture %Sink, <4 x i32>* nocapture readonly %SrcPtr) {
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; CHECK-LABEL: test4i8w:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lvx v2, 0, r4
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; CHECK-NEXT: xxswapd vs0, v2
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; CHECK-NEXT: mfvsrwz r4, v2
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; CHECK-NEXT: xxsldwi vs1, v2, v2, 1
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; CHECK-NEXT: xxsldwi vs3, v2, v2, 3
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; CHECK-NEXT: mtvsrd f2, r4
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; CHECK-NEXT: mfvsrwz r4, f0
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; CHECK-NEXT: mfvsrwz r5, f1
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; CHECK-NEXT: xxswapd v4, vs2
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; CHECK-NEXT: mtvsrd f0, r4
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; CHECK-NEXT: mfvsrwz r4, f3
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; CHECK-NEXT: mtvsrd f1, r5
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; CHECK-NEXT: xxswapd v2, vs0
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; CHECK-NEXT: mtvsrd f3, r4
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; CHECK-NEXT: xxswapd v3, vs1
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; CHECK-NEXT: xxswapd v5, vs3
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; CHECK-NEXT: vmrglb v2, v3, v2
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; CHECK-NEXT: vmrglb v3, v5, v4
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; CHECK-NEXT: vmrglh v2, v3, v2
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; CHECK-NEXT: addis r5, r2, .LCPI2_0@toc@ha
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; CHECK-NEXT: lvx v3, 0, r4
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; CHECK-NEXT: addi r5, r5, .LCPI2_0@toc@l
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; CHECK-NEXT: lvx v2, 0, r5
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; CHECK-NEXT: vperm v2, v3, v3, v2
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; CHECK-NEXT: xxsldwi vs0, v2, v2, 2
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; CHECK-NEXT: stfiwx f0, 0, r3
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test4i8w:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxvw4x vs0, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -32
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; CHECK-BE-NEXT: stxvw4x vs0, 0, r4
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; CHECK-BE-NEXT: lwz r4, -20(r1)
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; CHECK-BE-NEXT: stb r4, -48(r1)
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; CHECK-BE-NEXT: lwz r4, -24(r1)
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; CHECK-BE-NEXT: stb r4, -64(r1)
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; CHECK-BE-NEXT: lwz r4, -28(r1)
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; CHECK-BE-NEXT: stb r4, -80(r1)
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; CHECK-BE-NEXT: lwz r4, -32(r1)
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; CHECK-BE-NEXT: stb r4, -96(r1)
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; CHECK-BE-NEXT: addi r4, r1, -48
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; CHECK-BE-NEXT: addis r5, r2, .LCPI2_0@toc@ha
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; CHECK-BE-NEXT: lxvw4x v2, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -64
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; CHECK-BE-NEXT: addi r4, r5, .LCPI2_0@toc@l
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; CHECK-BE-NEXT: lxvw4x v3, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -80
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; CHECK-BE-NEXT: lxvw4x v4, 0, r4
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; CHECK-BE-NEXT: addi r4, r1, -96
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; CHECK-BE-NEXT: lxvw4x v5, 0, r4
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; CHECK-BE-NEXT: vmrghb v2, v3, v2
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; CHECK-BE-NEXT: addi r4, r1, -16
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; CHECK-BE-NEXT: vmrghb v3, v5, v4
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; CHECK-BE-NEXT: vmrghh v2, v3, v2
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; CHECK-BE-NEXT: vperm v2, v2, v2, v3
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; CHECK-BE-NEXT: stxvw4x v2, 0, r4
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; CHECK-BE-NEXT: lwz r4, -16(r1)
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; CHECK-BE-NEXT: stw r4, 0(r3)
|
||||
|
|
@ -231,15 +91,7 @@ define void @test2i8(<2 x i8>* nocapture %Sink, <2 x i16>* nocapture readonly %S
|
|||
; CHECK-LABEL: test2i8:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: lvx v2, 0, r4
|
||||
; CHECK-NEXT: xxswapd vs0, v2
|
||||
; CHECK-NEXT: mfvsrd r4, f0
|
||||
; CHECK-NEXT: clrldi r5, r4, 48
|
||||
; CHECK-NEXT: rldicl r4, r4, 48, 48
|
||||
; CHECK-NEXT: mtvsrd f0, r5
|
||||
; CHECK-NEXT: mtvsrd f1, r4
|
||||
; CHECK-NEXT: xxswapd v2, vs0
|
||||
; CHECK-NEXT: xxswapd v3, vs1
|
||||
; CHECK-NEXT: vmrglb v2, v3, v2
|
||||
; CHECK-NEXT: vpkuhum v2, v2, v2
|
||||
; CHECK-NEXT: xxswapd vs0, v2
|
||||
; CHECK-NEXT: mfvsrd r4, f0
|
||||
; CHECK-NEXT: clrldi r4, r4, 48
|
||||
|
|
@ -248,20 +100,10 @@ define void @test2i8(<2 x i8>* nocapture %Sink, <2 x i16>* nocapture readonly %S
|
|||
;
|
||||
; CHECK-BE-LABEL: test2i8:
|
||||
; CHECK-BE: # %bb.0: # %entry
|
||||
; CHECK-BE-NEXT: lxvw4x vs0, 0, r4
|
||||
; CHECK-BE-NEXT: addi r4, r1, -32
|
||||
; CHECK-BE-NEXT: stxvw4x vs0, 0, r4
|
||||
; CHECK-BE-NEXT: lhz r4, -30(r1)
|
||||
; CHECK-BE-NEXT: stb r4, -48(r1)
|
||||
; CHECK-BE-NEXT: lhz r4, -32(r1)
|
||||
; CHECK-BE-NEXT: stb r4, -64(r1)
|
||||
; CHECK-BE-NEXT: addi r4, r1, -48
|
||||
; CHECK-BE-NEXT: lxvw4x v2, 0, r4
|
||||
; CHECK-BE-NEXT: addi r4, r1, -64
|
||||
; CHECK-BE-NEXT: lxvw4x v3, 0, r4
|
||||
; CHECK-BE-NEXT: addi r4, r1, -16
|
||||
; CHECK-BE-NEXT: vmrghb v2, v3, v2
|
||||
; CHECK-BE-NEXT: stxvw4x v2, 0, r4
|
||||
; CHECK-BE-NEXT: addi r5, r1, -16
|
||||
; CHECK-BE-NEXT: vpkuhum v2, v2, v2
|
||||
; CHECK-BE-NEXT: stxvw4x v2, 0, r5
|
||||
; CHECK-BE-NEXT: lhz r4, -16(r1)
|
||||
; CHECK-BE-NEXT: sth r4, 0(r3)
|
||||
; CHECK-BE-NEXT: blr
|
||||
|
|
@ -276,54 +118,17 @@ define void @test4i16(<4 x i16>* nocapture %Sink, <4 x i32>* nocapture readonly
|
|||
; CHECK-LABEL: test4i16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: lvx v2, 0, r4
|
||||
; CHECK-NEXT: xxswapd vs0, v2
|
||||
; CHECK-NEXT: mfvsrwz r4, v2
|
||||
; CHECK-NEXT: xxsldwi vs1, v2, v2, 1
|
||||
; CHECK-NEXT: xxsldwi vs3, v2, v2, 3
|
||||
; CHECK-NEXT: mtvsrd f2, r4
|
||||
; CHECK-NEXT: mfvsrwz r4, f0
|
||||
; CHECK-NEXT: mfvsrwz r5, f1
|
||||
; CHECK-NEXT: xxswapd v4, vs2
|
||||
; CHECK-NEXT: mtvsrd f0, r4
|
||||
; CHECK-NEXT: mfvsrwz r4, f3
|
||||
; CHECK-NEXT: mtvsrd f1, r5
|
||||
; CHECK-NEXT: xxswapd v2, vs0
|
||||
; CHECK-NEXT: mtvsrd f3, r4
|
||||
; CHECK-NEXT: xxswapd v3, vs1
|
||||
; CHECK-NEXT: xxswapd v5, vs3
|
||||
; CHECK-NEXT: vmrglh v2, v3, v2
|
||||
; CHECK-NEXT: vmrglh v3, v5, v4
|
||||
; CHECK-NEXT: vmrglw v2, v3, v2
|
||||
; CHECK-NEXT: vpkuwum v2, v2, v2
|
||||
; CHECK-NEXT: xxswapd vs0, v2
|
||||
; CHECK-NEXT: stfdx f0, 0, r3
|
||||
; CHECK-NEXT: blr
|
||||
;
|
||||
; CHECK-BE-LABEL: test4i16:
|
||||
; CHECK-BE: # %bb.0: # %entry
|
||||
; CHECK-BE-NEXT: lxvw4x vs0, 0, r4
|
||||
; CHECK-BE-NEXT: addi r4, r1, -32
|
||||
; CHECK-BE-NEXT: stxvw4x vs0, 0, r4
|
||||
; CHECK-BE-NEXT: lwz r4, -20(r1)
|
||||
; CHECK-BE-NEXT: sth r4, -48(r1)
|
||||
; CHECK-BE-NEXT: lwz r4, -24(r1)
|
||||
; CHECK-BE-NEXT: sth r4, -64(r1)
|
||||
; CHECK-BE-NEXT: lwz r4, -28(r1)
|
||||
; CHECK-BE-NEXT: sth r4, -80(r1)
|
||||
; CHECK-BE-NEXT: lwz r4, -32(r1)
|
||||
; CHECK-BE-NEXT: sth r4, -96(r1)
|
||||
; CHECK-BE-NEXT: addi r4, r1, -48
|
||||
; CHECK-BE-NEXT: lxvw4x v2, 0, r4
|
||||
; CHECK-BE-NEXT: addi r4, r1, -64
|
||||
; CHECK-BE-NEXT: lxvw4x v3, 0, r4
|
||||
; CHECK-BE-NEXT: addi r4, r1, -80
|
||||
; CHECK-BE-NEXT: lxvw4x v4, 0, r4
|
||||
; CHECK-BE-NEXT: addi r4, r1, -96
|
||||
; CHECK-BE-NEXT: lxvw4x v5, 0, r4
|
||||
; CHECK-BE-NEXT: vmrghh v2, v3, v2
|
||||
; CHECK-BE-NEXT: addi r4, r1, -16
|
||||
; CHECK-BE-NEXT: vmrghh v3, v5, v4
|
||||
; CHECK-BE-NEXT: vmrghw v2, v3, v2
|
||||
; CHECK-BE-NEXT: stxvd2x v2, 0, r4
|
||||
; CHECK-BE-NEXT: addi r5, r1, -16
|
||||
; CHECK-BE-NEXT: vpkuwum v2, v2, v2
|
||||
; CHECK-BE-NEXT: stxvd2x v2, 0, r5
|
||||
; CHECK-BE-NEXT: ld r4, -16(r1)
|
||||
; CHECK-BE-NEXT: std r4, 0(r3)
|
||||
; CHECK-BE-NEXT: blr
|
||||
|
|
@ -338,35 +143,17 @@ define void @test2i16(<2 x i16>* nocapture %Sink, <2 x i32>* nocapture readonly
|
|||
; CHECK-LABEL: test2i16:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: lvx v2, 0, r4
|
||||
; CHECK-NEXT: xxswapd vs0, v2
|
||||
; CHECK-NEXT: xxsldwi vs1, v2, v2, 1
|
||||
; CHECK-NEXT: mfvsrwz r4, f0
|
||||
; CHECK-NEXT: mfvsrwz r5, f1
|
||||
; CHECK-NEXT: mtvsrd f0, r4
|
||||
; CHECK-NEXT: mtvsrd f1, r5
|
||||
; CHECK-NEXT: xxswapd v2, vs0
|
||||
; CHECK-NEXT: xxswapd v3, vs1
|
||||
; CHECK-NEXT: vmrglh v2, v3, v2
|
||||
; CHECK-NEXT: vpkuwum v2, v2, v2
|
||||
; CHECK-NEXT: xxsldwi vs0, v2, v2, 2
|
||||
; CHECK-NEXT: stfiwx f0, 0, r3
|
||||
; CHECK-NEXT: blr
|
||||
;
|
||||
; CHECK-BE-LABEL: test2i16:
|
||||
; CHECK-BE: # %bb.0: # %entry
|
||||
; CHECK-BE-NEXT: lxvw4x vs0, 0, r4
|
||||
; CHECK-BE-NEXT: addi r4, r1, -32
|
||||
; CHECK-BE-NEXT: stxvw4x vs0, 0, r4
|
||||
; CHECK-BE-NEXT: lwz r4, -28(r1)
|
||||
; CHECK-BE-NEXT: sth r4, -48(r1)
|
||||
; CHECK-BE-NEXT: lwz r4, -32(r1)
|
||||
; CHECK-BE-NEXT: sth r4, -64(r1)
|
||||
; CHECK-BE-NEXT: addi r4, r1, -48
|
||||
; CHECK-BE-NEXT: lxvw4x v2, 0, r4
|
||||
; CHECK-BE-NEXT: addi r4, r1, -64
|
||||
; CHECK-BE-NEXT: lxvw4x v3, 0, r4
|
||||
; CHECK-BE-NEXT: addi r4, r1, -16
|
||||
; CHECK-BE-NEXT: vmrghh v2, v3, v2
|
||||
; CHECK-BE-NEXT: stxvw4x v2, 0, r4
|
||||
; CHECK-BE-NEXT: addi r5, r1, -16
|
||||
; CHECK-BE-NEXT: vpkuwum v2, v2, v2
|
||||
; CHECK-BE-NEXT: stxvw4x v2, 0, r5
|
||||
; CHECK-BE-NEXT: lwz r4, -16(r1)
|
||||
; CHECK-BE-NEXT: stw r4, 0(r3)
|
||||
; CHECK-BE-NEXT: blr
|
||||
|
|
@ -381,33 +168,23 @@ define void @test2i16d(<2 x i16>* nocapture %Sink, <2 x i64>* nocapture readonly
|
|||
; CHECK-LABEL: test2i16d:
|
||||
; CHECK: # %bb.0: # %entry
|
||||
; CHECK-NEXT: lxvd2x vs0, 0, r4
|
||||
; CHECK-NEXT: xxswapd vs1, vs0
|
||||
; CHECK-NEXT: mfvsrwz r4, f0
|
||||
; CHECK-NEXT: mtvsrd f0, r4
|
||||
; CHECK-NEXT: mfvsrwz r5, f1
|
||||
; CHECK-NEXT: addis r5, r2, .LCPI6_0@toc@ha
|
||||
; CHECK-NEXT: addi r4, r5, .LCPI6_0@toc@l
|
||||
; CHECK-NEXT: lvx v3, 0, r4
|
||||
; CHECK-NEXT: xxswapd v2, vs0
|
||||
; CHECK-NEXT: mtvsrd f1, r5
|
||||
; CHECK-NEXT: xxswapd v3, vs1
|
||||
; CHECK-NEXT: vmrglh v2, v3, v2
|
||||
; CHECK-NEXT: vperm v2, v2, v2, v3
|
||||
; CHECK-NEXT: xxsldwi vs0, v2, v2, 2
|
||||
; CHECK-NEXT: stfiwx f0, 0, r3
|
||||
; CHECK-NEXT: blr
|
||||
;
|
||||
; CHECK-BE-LABEL: test2i16d:
|
||||
; CHECK-BE: # %bb.0: # %entry
|
||||
; CHECK-BE-NEXT: lxvd2x vs0, 0, r4
|
||||
; CHECK-BE-NEXT: addi r4, r1, -32
|
||||
; CHECK-BE-NEXT: stxvd2x vs0, 0, r4
|
||||
; CHECK-BE-NEXT: lwz r4, -20(r1)
|
||||
; CHECK-BE-NEXT: sth r4, -48(r1)
|
||||
; CHECK-BE-NEXT: lwz r4, -28(r1)
|
||||
; CHECK-BE-NEXT: sth r4, -64(r1)
|
||||
; CHECK-BE-NEXT: addi r4, r1, -48
|
||||
; CHECK-BE-NEXT: addis r5, r2, .LCPI6_0@toc@ha
|
||||
; CHECK-BE-NEXT: lxvw4x v2, 0, r4
|
||||
; CHECK-BE-NEXT: addi r4, r1, -64
|
||||
; CHECK-BE-NEXT: addi r4, r5, .LCPI6_0@toc@l
|
||||
; CHECK-BE-NEXT: lxvw4x v3, 0, r4
|
||||
; CHECK-BE-NEXT: addi r4, r1, -16
|
||||
; CHECK-BE-NEXT: vmrghh v2, v3, v2
|
||||
; CHECK-BE-NEXT: vperm v2, v2, v2, v3
|
||||
; CHECK-BE-NEXT: stxvw4x v2, 0, r4
|
||||
; CHECK-BE-NEXT: lwz r4, -16(r1)
|
||||
; CHECK-BE-NEXT: stw r4, 0(r3)
|
||||
|
|
|
|||
Loading…
Reference in New Issue