forked from OSchip/llvm-project
parent
4339b3ff35
commit
73275a2951
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@ -329,8 +329,8 @@ static raw_ostream &operator<<(raw_ostream &OS,
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if (SVI.KillsSource)
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OS << " kill";
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OS << " deps[";
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for (unsigned i = 0, e = SVI.Deps.size(); i != e; ++i)
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OS << ' ' << SVI.Deps[i]->id << '@' << SVI.Deps[i]->def;
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for (VNInfo *Dep : SVI.Deps)
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OS << ' ' << Dep->id << '@' << Dep->def;
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OS << " ]";
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if (SVI.DefMI)
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OS << " def: " << *SVI.DefMI;
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@ -383,9 +383,8 @@ void InlineSpiller::propagateSiblingValue(SibValueMap::iterator SVIIter,
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bool PropSpill = !DisableHoisting && !isRegToSpill(SV.SpillReg);
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unsigned SpillDepth = ~0u;
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for (TinyPtrVector<VNInfo*>::iterator DepI = Deps->begin(),
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DepE = Deps->end(); DepI != DepE; ++DepI) {
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SibValueMap::iterator DepSVI = SibValues.find(*DepI);
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for (VNInfo *Dep : *Deps) {
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SibValueMap::iterator DepSVI = SibValues.find(Dep);
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assert(DepSVI != SibValues.end() && "Dependent value not in SibValues");
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SibValueInfo &DepSV = DepSVI->second;
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if (!DepSV.SpillMBB)
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@ -566,12 +565,11 @@ MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI,
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// Create entries for all the PHIs. Don't add them to the worklist, we
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// are processing all of them in one go here.
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for (unsigned i = 0, e = PHIs.size(); i != e; ++i)
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SibValues.insert(std::make_pair(PHIs[i], SibValueInfo(Reg, PHIs[i])));
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for (VNInfo *PHI : PHIs)
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SibValues.insert(std::make_pair(PHI, SibValueInfo(Reg, PHI)));
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// Add every PHI as a dependent of all the non-PHIs.
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for (unsigned i = 0, e = NonPHIs.size(); i != e; ++i) {
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VNInfo *NonPHI = NonPHIs[i];
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for (VNInfo *NonPHI : NonPHIs) {
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// Known value? Try an insertion.
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std::tie(SVI, Inserted) =
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SibValues.insert(std::make_pair(NonPHI, SibValueInfo(Reg, NonPHI)));
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@ -654,8 +652,7 @@ void InlineSpiller::analyzeSiblingValues() {
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return;
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LiveInterval &OrigLI = LIS.getInterval(Original);
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for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
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unsigned Reg = RegsToSpill[i];
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for (unsigned Reg : RegsToSpill) {
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LiveInterval &LI = LIS.getInterval(Reg);
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for (LiveInterval::const_vni_iterator VI = LI.vni_begin(),
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VE = LI.vni_end(); VI != VE; ++VI) {
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@ -831,9 +828,8 @@ void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) {
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if (VNI->isPHIDef()) {
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MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def);
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for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
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PE = MBB->pred_end(); PI != PE; ++PI) {
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VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(*PI));
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for (MachineBasicBlock *P : MBB->predecessors()) {
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VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(P));
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if (PVNI)
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WorkList.push_back(std::make_pair(LI, PVNI));
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}
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@ -920,8 +916,8 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg,
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<< *LIS.getInstructionFromIndex(DefIdx));
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// Replace operands
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for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
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MachineOperand &MO = Ops[i].first->getOperand(Ops[i].second);
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for (const auto &OpPair : Ops) {
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MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
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if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
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MO.setReg(NewVReg);
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MO.setIsKill();
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@ -944,8 +940,7 @@ void InlineSpiller::reMaterializeAll() {
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// Try to remat before all uses of snippets.
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bool anyRemat = false;
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for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
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unsigned Reg = RegsToSpill[i];
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for (unsigned Reg : RegsToSpill) {
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LiveInterval &LI = LIS.getInterval(Reg);
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for (MachineRegisterInfo::reg_bundle_iterator
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RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end();
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@ -963,8 +958,7 @@ void InlineSpiller::reMaterializeAll() {
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return;
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// Remove any values that were completely rematted.
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for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
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unsigned Reg = RegsToSpill[i];
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for (unsigned Reg : RegsToSpill) {
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LiveInterval &LI = LIS.getInterval(Reg);
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for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end();
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I != E; ++I) {
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@ -989,8 +983,7 @@ void InlineSpiller::reMaterializeAll() {
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// Get rid of deleted and empty intervals.
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unsigned ResultPos = 0;
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for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
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unsigned Reg = RegsToSpill[i];
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for (unsigned Reg : RegsToSpill) {
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if (!LIS.hasInterval(Reg))
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continue;
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@ -1098,9 +1091,9 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> > Ops,
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// TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied
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// operands.
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SmallVector<unsigned, 8> FoldOps;
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for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
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unsigned Idx = Ops[i].second;
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assert(MI == Ops[i].first && "Instruction conflict during operand folding");
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for (const auto &OpPair : Ops) {
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unsigned Idx = OpPair.second;
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assert(MI == OpPair.first && "Instruction conflict during operand folding");
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MachineOperand &MO = MI->getOperand(Idx);
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if (MO.isImplicit()) {
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ImpReg = MO.getReg();
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@ -1152,10 +1145,9 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr*, unsigned> > Ops,
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// Insert any new instructions other than FoldMI into the LIS maps.
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assert(!MIS.empty() && "Unexpected empty span of instructions!");
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for (MachineBasicBlock::iterator MII = MIS.begin(), End = MIS.end();
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MII != End; ++MII)
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if (&*MII != FoldMI)
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LIS.InsertMachineInstrInMaps(&*MII);
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for (MachineInstr &MI : MIS)
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if (&MI != FoldMI)
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LIS.InsertMachineInstrInMaps(&MI);
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// TII.foldMemoryOperand may have left some implicit operands on the
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// instruction. Strip them.
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@ -1301,11 +1293,11 @@ void InlineSpiller::spillAroundUses(unsigned Reg) {
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// Rewrite instruction operands.
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bool hasLiveDef = false;
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for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
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MachineOperand &MO = Ops[i].first->getOperand(Ops[i].second);
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for (const auto &OpPair : Ops) {
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MachineOperand &MO = OpPair.first->getOperand(OpPair.second);
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MO.setReg(NewVReg);
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if (MO.isUse()) {
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if (!Ops[i].first->isRegTiedToDefOperand(Ops[i].second))
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if (!OpPair.first->isRegTiedToDefOperand(OpPair.second))
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MO.setIsKill();
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} else {
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if (!MO.isDead())
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@ -1335,14 +1327,14 @@ void InlineSpiller::spillAll() {
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VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot);
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assert(StackInt->getNumValNums() == 1 && "Bad stack interval values");
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for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
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StackInt->MergeSegmentsInAsValue(LIS.getInterval(RegsToSpill[i]),
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for (unsigned Reg : RegsToSpill)
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StackInt->MergeSegmentsInAsValue(LIS.getInterval(Reg),
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StackInt->getValNumInfo(0));
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DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
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// Spill around uses of all RegsToSpill.
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for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
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spillAroundUses(RegsToSpill[i]);
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for (unsigned Reg : RegsToSpill)
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spillAroundUses(Reg);
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// Hoisted spills may cause dead code.
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if (!DeadDefs.empty()) {
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@ -1351,9 +1343,9 @@ void InlineSpiller::spillAll() {
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}
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// Finally delete the SnippetCopies.
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for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i) {
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for (unsigned Reg : RegsToSpill) {
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for (MachineRegisterInfo::reg_instr_iterator
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RI = MRI.reg_instr_begin(RegsToSpill[i]), E = MRI.reg_instr_end();
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RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end();
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RI != E; ) {
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MachineInstr *MI = &*(RI++);
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assert(SnippetCopies.count(MI) && "Remaining use wasn't a snippet copy");
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@ -1364,8 +1356,8 @@ void InlineSpiller::spillAll() {
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}
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// Delete all spilled registers.
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for (unsigned i = 0, e = RegsToSpill.size(); i != e; ++i)
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Edit->eraseVirtReg(RegsToSpill[i]);
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for (unsigned Reg : RegsToSpill)
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Edit->eraseVirtReg(Reg);
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}
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void InlineSpiller::spill(LiveRangeEdit &edit) {
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