forked from OSchip/llvm-project
[AArch64] Add test/CodeGen/AArch64/vecreduce-fadd.ll
This test is added to see difference created by: https://reviews.llvm.org/D59259 llvm-svn: 356054
This commit is contained in:
Sander de Smalen
parent
0a251e4076
commit
72fc7b842c
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; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=generic -asm-verbose=0 -mattr=+fullfp16 | FileCheck %s
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; RUN: llc < %s -mtriple=aarch64-eabi -aarch64-neon-syntax=generic -asm-verbose=0 | FileCheck %s --check-prefix=CHECKNOFP16
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define float @add_HalfS(<2 x float> %bin.rdx) {
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; CHECK-LABEL: add_HalfS:
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; CHECK: faddp s0, v0.2s
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; CHECK-NEXT: ret
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%r = call fast float @llvm.experimental.vector.reduce.fadd.f32.v2f32(<2 x float> undef, <2 x float> %bin.rdx)
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ret float %r
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}
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define half @add_HalfH(<4 x half> %bin.rdx) {
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; CHECK-LABEL: add_HalfH:
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; CHECK: mov h3, v0.h[1]
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; CHECK-NEXT: mov h1, v0.h[3]
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; CHECK-NEXT: mov h2, v0.h[2]
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; CHECK-NEXT: fadd h0, h0, h3
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; CHECK-NEXT: fadd h0, h0, h2
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; CHECK-NEXT: fadd h0, h0, h1
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; CHECK-NEXT: ret
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; CHECKNOFP16-LABEL: add_HalfH:
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; CHECKNOFP16-NOT: faddp
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; CHECKNOFP16-NOT: fadd h{{[0-9]+}}
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; CHECKNOFP16-NOT: fadd v{{[0-9]+}}.{{[0-9]}}h
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; CHECKNOFP16: ret
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%r = call fast half @llvm.experimental.vector.reduce.fadd.f16.v4f16(<4 x half> undef, <4 x half> %bin.rdx)
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ret half %r
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}
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define half @add_H(<8 x half> %bin.rdx) {
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; CHECK-LABEL: add_H:
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; CHECK: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: fadd v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: mov h1, v0.h[1]
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; CHECK-NEXT: mov h2, v0.h[2]
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; CHECK-NEXT: fadd h1, h0, h1
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; CHECK-NEXT: fadd h1, h1, h2
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; CHECK-NEXT: mov h0, v0.h[3]
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; CHECK-NEXT: fadd h0, h1, h0
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; CHECK-NEXT: ret
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; CHECKNOFP16-LABEL: add_H:
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; CHECKNOFP16-NOT: faddp
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; CHECKNOFP16-NOT: fadd h{{[0-9]+}}
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; CHECKNOFP16-NOT: fadd v{{[0-9]+}}.{{[0-9]}}h
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; CHECKNOFP16: ret
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%r = call fast half @llvm.experimental.vector.reduce.fadd.f16.v8f16(<8 x half> undef, <8 x half> %bin.rdx)
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ret half %r
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}
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define float @add_S(<4 x float> %bin.rdx) {
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; CHECK-LABEL: add_S:
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; CHECK: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: fadd v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: faddp s0, v0.2s
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; CHECK-NEXT: ret
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%r = call fast float @llvm.experimental.vector.reduce.fadd.f32.v4f32(<4 x float> undef, <4 x float> %bin.rdx)
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ret float %r
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}
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define double @add_D(<2 x double> %bin.rdx) {
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; CHECK-LABEL: add_D:
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; CHECK: faddp d0, v0.2d
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; CHECK-NEXT: ret
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%r = call fast double @llvm.experimental.vector.reduce.fadd.f64.v2f64(<2 x double> undef, <2 x double> %bin.rdx)
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ret double %r
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}
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define half @add_2H(<16 x half> %bin.rdx) {
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; CHECK-LABEL: add_2H:
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; CHECK: fadd v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: fadd v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: mov h1, v0.h[1]
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; CHECK-NEXT: mov h2, v0.h[2]
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; CHECK-NEXT: fadd h1, h0, h1
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; CHECK-NEXT: fadd h1, h1, h2
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; CHECK-NEXT: mov h0, v0.h[3]
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; CHECK-NEXT: fadd h0, h1, h0
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; CHECK-NEXT: ret
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; CHECKNOFP16-LABEL: add_2H:
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; CHECKNOFP16-NOT: faddp
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; CHECKNOFP16-NOT: fadd h{{[0-9]+}}
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; CHECKNOFP16-NOT: fadd v{{[0-9]+}}.{{[0-9]}}h
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; CHECKNOFP16: ret
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%r = call fast half @llvm.experimental.vector.reduce.fadd.f16.v16f16(<16 x half> undef, <16 x half> %bin.rdx)
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ret half %r
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}
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define float @add_2S(<8 x float> %bin.rdx) {
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; CHECK-LABEL: add_2S:
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; CHECK: fadd v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: fadd v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: faddp s0, v0.2s
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; CHECK-NEXT: ret
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%r = call fast float @llvm.experimental.vector.reduce.fadd.f32.v8f32(<8 x float> undef, <8 x float> %bin.rdx)
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ret float %r
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}
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define double @add_2D(<4 x double> %bin.rdx) {
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; CHECK-LABEL: add_2D:
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; CHECK: fadd v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: faddp d0, v0.2d
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; CHECK-NEXT: ret
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%r = call fast double @llvm.experimental.vector.reduce.fadd.f64.v4f64(<4 x double> undef, <4 x double> %bin.rdx)
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ret double %r
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}
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; Function Attrs: nounwind readnone
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declare half @llvm.experimental.vector.reduce.fadd.f16.v4f16(<4 x half>, <4 x half>)
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declare half @llvm.experimental.vector.reduce.fadd.f16.v8f16(<8 x half>, <8 x half>)
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declare half @llvm.experimental.vector.reduce.fadd.f16.v16f16(<16 x half>, <16 x half>)
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declare float @llvm.experimental.vector.reduce.fadd.f32.v2f32(<2 x float>, <2 x float>)
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declare float @llvm.experimental.vector.reduce.fadd.f32.v4f32(<4 x float>, <4 x float>)
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declare float @llvm.experimental.vector.reduce.fadd.f32.v8f32(<8 x float>, <8 x float>)
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declare double @llvm.experimental.vector.reduce.fadd.f64.v2f64(<2 x double>, <2 x double>)
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declare double @llvm.experimental.vector.reduce.fadd.f64.v4f64(<4 x double>, <4 x double>)
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