forked from OSchip/llvm-project
R600/SI: cleanup SIInstrInfo.td and SIInstrFormat.td
Those two files got mixed up. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175746
This commit is contained in:
Christian Konig
parent
8dbcb98c52
commit
72d5d5c754
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@ -1,4 +1,4 @@
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//===-- SIInstrFormats.td - SI Instruction Formats ------------------------===//
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//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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@ -9,180 +9,418 @@
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//
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// SI Instruction format definitions.
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//
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// Instructions with _32 take 32-bit operands.
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// Instructions with _64 take 64-bit operands.
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//
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// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
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// encoding is the standard encoding, but instruction that make use of
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// any of the instruction modifiers must use the 64-bit encoding.
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//
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// Instructions with _e32 use the 32-bit encoding.
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// Instructions with _e64 use the 64-bit encoding.
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//
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//===----------------------------------------------------------------------===//
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class VOP3_32 <bits<9> op, string opName, list<dag> pattern>
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: VOP3 <op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
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class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
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AMDGPUInst<outs, ins, asm, pattern> {
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class VOP3_64 <bits<9> op, string opName, list<dag> pattern>
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: VOP3 <op, (outs VReg_64:$dst), (ins VSrc_64:$src0, VReg_64:$src1, VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
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field bits<1> VM_CNT = 0;
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field bits<1> EXP_CNT = 0;
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field bits<1> LGKM_CNT = 0;
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class SOP1_32 <bits<8> op, string opName, list<dag> pattern>
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: SOP1 <op, (outs SReg_32:$dst), (ins SSrc_32:$src0), opName, pattern>;
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class SOP1_64 <bits<8> op, string opName, list<dag> pattern>
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: SOP1 <op, (outs SReg_64:$dst), (ins SSrc_64:$src0), opName, pattern>;
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class SOP2_32 <bits<7> op, string opName, list<dag> pattern>
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: SOP2 <op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), opName, pattern>;
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class SOP2_64 <bits<7> op, string opName, list<dag> pattern>
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: SOP2 <op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>;
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class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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string opName, list<dag> pattern> :
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VOP1 <
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op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
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>;
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multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> {
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def _e32: VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>;
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def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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let TSFlags{0} = VM_CNT;
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let TSFlags{1} = EXP_CNT;
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let TSFlags{2} = LGKM_CNT;
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}
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multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> {
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class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI <outs, ins, asm, pattern> {
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def _e32 : VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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def _e64 : VOP3_64 <
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{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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field bits<32> Inst;
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let Size = 4;
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}
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class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
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string opName, list<dag> pattern> :
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VOP2 <
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op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
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>;
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class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI <outs, ins, asm, pattern> {
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multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
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def _e32 : VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern>;
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def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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field bits<64> Inst;
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let Size = 8;
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}
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multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> {
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def _e32: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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//===----------------------------------------------------------------------===//
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// Scalar operations
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//===----------------------------------------------------------------------===//
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def _e64 : VOP3_64 <
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{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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opName, []
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>;
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}
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class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32<outs, ins, asm, pattern> {
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class SOPK_32 <bits<5> op, string opName, list<dag> pattern>
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: SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
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bits<7> SDST;
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bits<8> SSRC0;
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class SOPK_64 <bits<5> op, string opName, list<dag> pattern>
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: SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>;
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let Inst{7-0} = SSRC0;
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let Inst{15-8} = op;
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let Inst{22-16} = SDST;
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let Inst{31-23} = 0x17d; //encoding;
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multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
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string opName, list<dag> pattern> {
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def _e32 : VOPC <op, (ins arc:$src0, vrc:$src1), opName, pattern>;
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def _e64 : VOP3 <
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{0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
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(outs SReg_64:$dst),
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(ins arc:$src0, vrc:$src1,
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InstFlag:$abs, InstFlag:$clamp,
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InstFlag:$omod, InstFlag:$neg),
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opName, pattern
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> {
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let SRC2 = 0x80;
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}
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}
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multiclass VOPC_32 <bits<8> op, string opName, list<dag> pattern>
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: VOPC_Helper <op, VReg_32, VSrc_32, opName, pattern>;
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multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern>
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: VOPC_Helper <op, VReg_64, VSrc_64, opName, pattern>;
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class SOPC_32 <bits<7> op, string opName, list<dag> pattern>
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: SOPC <op, (outs SCCReg:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), opName, pattern>;
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class SOPC_64 <bits<7> op, string opName, list<dag> pattern>
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: SOPC <op, (outs SCCReg:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>;
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class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
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op,
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(outs VReg_128:$vdata),
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(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
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i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
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GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
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asm,
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[]> {
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let mayLoad = 1;
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let mayStore = 0;
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}
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class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
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op,
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(outs),
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(ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
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i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
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GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
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asm,
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[]> {
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let mayStore = 1;
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
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op,
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(outs regClass:$dst),
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(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
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i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
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i1imm:$tfe, SSrc_32:$soffset),
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class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32 <outs, ins, asm, pattern> {
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bits<7> SDST;
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bits<8> SSRC0;
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bits<8> SSRC1;
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let Inst{7-0} = SSRC0;
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let Inst{15-8} = SSRC1;
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let Inst{22-16} = SDST;
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let Inst{29-23} = op;
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let Inst{31-30} = 0x2; // encoding
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32<outs, ins, asm, pattern> {
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bits<8> SSRC0;
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bits<8> SSRC1;
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let Inst{7-0} = SSRC0;
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let Inst{15-8} = SSRC1;
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let Inst{22-16} = op;
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let Inst{31-23} = 0x17e;
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let DisableEncoding = "$dst";
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32 <outs, ins , asm, pattern> {
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bits <7> SDST;
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bits <16> SIMM16;
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let Inst{15-0} = SIMM16;
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let Inst{22-16} = SDST;
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let Inst{27-23} = op;
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let Inst{31-28} = 0xb; //encoding
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
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(outs),
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ins,
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asm,
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[]> {
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pattern > {
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bits <16> SIMM16;
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let Inst{15-0} = SIMM16;
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let Inst{22-16} = op;
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let Inst{31-23} = 0x17f; // encoding
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
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list<dag> pattern> : Enc32<outs, ins, asm, pattern> {
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bits<7> SDST;
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bits<6> SBASE;
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bits<8> OFFSET;
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let Inst{7-0} = OFFSET;
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let Inst{8} = imm;
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let Inst{14-9} = SBASE;
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let Inst{21-15} = SDST;
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let Inst{26-22} = op;
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let Inst{31-27} = 0x18; //encoding
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let LGKM_CNT = 1;
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}
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//===----------------------------------------------------------------------===//
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// Vector ALU operations
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//===----------------------------------------------------------------------===//
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let Uses = [EXEC] in {
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class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32 <outs, ins, asm, pattern> {
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bits<8> VDST;
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bits<9> SRC0;
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let Inst{8-0} = SRC0;
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let Inst{16-9} = op;
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let Inst{24-17} = VDST;
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let Inst{31-25} = 0x3f; //encoding
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32 <outs, ins, asm, pattern> {
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bits<8> VDST;
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bits<9> SRC0;
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bits<8> VSRC1;
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let Inst{8-0} = SRC0;
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let Inst{16-9} = VSRC1;
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let Inst{24-17} = VDST;
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let Inst{30-25} = op;
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let Inst{31} = 0x0; //encoding
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc64 <outs, ins, asm, pattern> {
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bits<8> VDST;
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bits<9> SRC0;
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bits<9> SRC1;
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bits<9> SRC2;
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bits<3> ABS;
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bits<1> CLAMP;
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bits<2> OMOD;
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bits<3> NEG;
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let Inst{7-0} = VDST;
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let Inst{10-8} = ABS;
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let Inst{11} = CLAMP;
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let Inst{25-17} = op;
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = SRC0;
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let Inst{49-41} = SRC1;
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let Inst{58-50} = SRC2;
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let Inst{60-59} = OMOD;
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let Inst{63-61} = NEG;
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc64 <outs, ins, asm, pattern> {
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bits<8> VDST;
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bits<9> SRC0;
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bits<9> SRC1;
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bits<9> SRC2;
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bits<7> SDST;
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bits<2> OMOD;
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bits<3> NEG;
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let Inst{7-0} = VDST;
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let Inst{14-8} = SDST;
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let Inst{25-17} = op;
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let Inst{31-26} = 0x34; //encoding
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let Inst{40-32} = SRC0;
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let Inst{49-41} = SRC1;
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let Inst{58-50} = SRC2;
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let Inst{60-59} = OMOD;
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let Inst{63-61} = NEG;
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
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Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
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bits<9> SRC0;
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bits<8> VSRC1;
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let Inst{8-0} = SRC0;
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let Inst{16-9} = VSRC1;
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let Inst{24-17} = op;
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let Inst{31-25} = 0x3e;
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let DisableEncoding = "$dst";
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let mayLoad = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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}
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class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc32 <outs, ins, asm, pattern> {
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bits<8> VDST;
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bits<8> VSRC;
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bits<2> ATTRCHAN;
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bits<6> ATTR;
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let Inst{7-0} = VSRC;
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let Inst{9-8} = ATTRCHAN;
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let Inst{15-10} = ATTR;
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let Inst{17-16} = op;
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let Inst{25-18} = VDST;
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let Inst{31-26} = 0x32; // encoding
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let neverHasSideEffects = 1;
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let mayLoad = 1;
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let mayStore = 0;
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}
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class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
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op,
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(outs regClass:$dst),
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(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
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i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
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i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
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asm,
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[]> {
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let mayLoad = 1;
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let mayStore = 0;
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} // End Uses = [EXEC]
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|
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//===----------------------------------------------------------------------===//
|
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// Vector I/O operations
|
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//===----------------------------------------------------------------------===//
|
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|
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let Uses = [EXEC] in {
|
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|
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class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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Enc64<outs, ins, asm, pattern> {
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bits<8> VDATA;
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bits<12> OFFSET;
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bits<1> OFFEN;
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bits<1> IDXEN;
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bits<1> GLC;
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bits<1> ADDR64;
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bits<1> LDS;
|
||||
bits<8> VADDR;
|
||||
bits<5> SRSRC;
|
||||
bits<1> SLC;
|
||||
bits<1> TFE;
|
||||
bits<8> SOFFSET;
|
||||
|
||||
let Inst{11-0} = OFFSET;
|
||||
let Inst{12} = OFFEN;
|
||||
let Inst{13} = IDXEN;
|
||||
let Inst{14} = GLC;
|
||||
let Inst{15} = ADDR64;
|
||||
let Inst{16} = LDS;
|
||||
let Inst{24-18} = op;
|
||||
let Inst{31-26} = 0x38; //encoding
|
||||
let Inst{39-32} = VADDR;
|
||||
let Inst{47-40} = VDATA;
|
||||
let Inst{52-48} = SRSRC;
|
||||
let Inst{54} = SLC;
|
||||
let Inst{55} = TFE;
|
||||
let Inst{63-56} = SOFFSET;
|
||||
|
||||
let VM_CNT = 1;
|
||||
let EXP_CNT = 1;
|
||||
|
||||
let neverHasSideEffects = 1;
|
||||
}
|
||||
|
||||
multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
|
||||
def _IMM : SMRD <
|
||||
op, 1,
|
||||
(outs dstClass:$dst),
|
||||
(ins GPR2Align<SReg_64>:$sbase, i32imm:$offset),
|
||||
asm,
|
||||
[]
|
||||
>;
|
||||
class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc64<outs, ins, asm, pattern> {
|
||||
|
||||
def _SGPR : SMRD <
|
||||
op, 0,
|
||||
(outs dstClass:$dst),
|
||||
(ins GPR2Align<SReg_64>:$sbase, SReg_32:$soff),
|
||||
asm,
|
||||
[]
|
||||
>;
|
||||
bits<8> VDATA;
|
||||
bits<12> OFFSET;
|
||||
bits<1> OFFEN;
|
||||
bits<1> IDXEN;
|
||||
bits<1> GLC;
|
||||
bits<1> ADDR64;
|
||||
bits<4> DFMT;
|
||||
bits<3> NFMT;
|
||||
bits<8> VADDR;
|
||||
bits<5> SRSRC;
|
||||
bits<1> SLC;
|
||||
bits<1> TFE;
|
||||
bits<8> SOFFSET;
|
||||
|
||||
let Inst{11-0} = OFFSET;
|
||||
let Inst{12} = OFFEN;
|
||||
let Inst{13} = IDXEN;
|
||||
let Inst{14} = GLC;
|
||||
let Inst{15} = ADDR64;
|
||||
let Inst{18-16} = op;
|
||||
let Inst{22-19} = DFMT;
|
||||
let Inst{25-23} = NFMT;
|
||||
let Inst{31-26} = 0x3a; //encoding
|
||||
let Inst{39-32} = VADDR;
|
||||
let Inst{47-40} = VDATA;
|
||||
let Inst{52-48} = SRSRC;
|
||||
let Inst{54} = SLC;
|
||||
let Inst{55} = TFE;
|
||||
let Inst{63-56} = SOFFSET;
|
||||
|
||||
let VM_CNT = 1;
|
||||
let EXP_CNT = 1;
|
||||
|
||||
let neverHasSideEffects = 1;
|
||||
}
|
||||
|
||||
class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc64 <outs, ins, asm, pattern> {
|
||||
|
||||
bits<8> VDATA;
|
||||
bits<4> DMASK;
|
||||
bits<1> UNORM;
|
||||
bits<1> GLC;
|
||||
bits<1> DA;
|
||||
bits<1> R128;
|
||||
bits<1> TFE;
|
||||
bits<1> LWE;
|
||||
bits<1> SLC;
|
||||
bits<8> VADDR;
|
||||
bits<5> SRSRC;
|
||||
bits<5> SSAMP;
|
||||
|
||||
let Inst{11-8} = DMASK;
|
||||
let Inst{12} = UNORM;
|
||||
let Inst{13} = GLC;
|
||||
let Inst{14} = DA;
|
||||
let Inst{15} = R128;
|
||||
let Inst{16} = TFE;
|
||||
let Inst{17} = LWE;
|
||||
let Inst{24-18} = op;
|
||||
let Inst{25} = SLC;
|
||||
let Inst{31-26} = 0x3c;
|
||||
let Inst{39-32} = VADDR;
|
||||
let Inst{47-40} = VDATA;
|
||||
let Inst{52-48} = SRSRC;
|
||||
let Inst{57-53} = SSAMP;
|
||||
|
||||
let VM_CNT = 1;
|
||||
let EXP_CNT = 1;
|
||||
}
|
||||
|
||||
def EXP : Enc64<
|
||||
(outs),
|
||||
(ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
|
||||
VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
|
||||
"EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
|
||||
[] > {
|
||||
|
||||
bits<4> EN;
|
||||
bits<6> TGT;
|
||||
bits<1> COMPR;
|
||||
bits<1> DONE;
|
||||
bits<1> VM;
|
||||
bits<8> VSRC0;
|
||||
bits<8> VSRC1;
|
||||
bits<8> VSRC2;
|
||||
bits<8> VSRC3;
|
||||
|
||||
let Inst{3-0} = EN;
|
||||
let Inst{9-4} = TGT;
|
||||
let Inst{10} = COMPR;
|
||||
let Inst{11} = DONE;
|
||||
let Inst{12} = VM;
|
||||
let Inst{31-26} = 0x3e;
|
||||
let Inst{39-32} = VSRC0;
|
||||
let Inst{47-40} = VSRC1;
|
||||
let Inst{55-48} = VSRC2;
|
||||
let Inst{63-56} = VSRC3;
|
||||
|
||||
let EXP_CNT = 1;
|
||||
}
|
||||
|
||||
} // End Uses = [EXEC]
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
//===-- SIInstrInfo.td - SI Instruction Encodings ---------*- tablegen -*--===//
|
||||
//===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
|
|
@ -44,31 +44,10 @@ class InlineImm <ValueType vt> : ImmLeaf <vt, [{
|
|||
return -16 <= Imm && Imm <= 64;
|
||||
}]>;
|
||||
|
||||
class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
AMDGPUInst<outs, ins, asm, pattern> {
|
||||
|
||||
field bits<1> VM_CNT = 0;
|
||||
field bits<1> EXP_CNT = 0;
|
||||
field bits<1> LGKM_CNT = 0;
|
||||
|
||||
let TSFlags{0} = VM_CNT;
|
||||
let TSFlags{1} = EXP_CNT;
|
||||
let TSFlags{2} = LGKM_CNT;
|
||||
}
|
||||
|
||||
class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
InstSI <outs, ins, asm, pattern> {
|
||||
|
||||
field bits<32> Inst;
|
||||
let Size = 4;
|
||||
}
|
||||
|
||||
class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
InstSI <outs, ins, asm, pattern> {
|
||||
|
||||
field bits<64> Inst;
|
||||
let Size = 8;
|
||||
}
|
||||
//===----------------------------------------------------------------------===//
|
||||
// SI assembler operands
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class SIOperand <ValueType vt, dag opInfo>: Operand <vt> {
|
||||
let EncoderMethod = "encodeOperand";
|
||||
|
|
@ -85,381 +64,203 @@ class GPR2Align <RegisterClass rc> : Operand <iPTR> {
|
|||
let MIOperandInfo = (ops rc:$reg);
|
||||
}
|
||||
|
||||
let Uses = [EXEC] in {
|
||||
include "SIInstrFormats.td"
|
||||
|
||||
def EXP : Enc64<
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// SI Instruction multiclass helpers.
|
||||
//
|
||||
// Instructions with _32 take 32-bit operands.
|
||||
// Instructions with _64 take 64-bit operands.
|
||||
//
|
||||
// VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
|
||||
// encoding is the standard encoding, but instruction that make use of
|
||||
// any of the instruction modifiers must use the 64-bit encoding.
|
||||
//
|
||||
// Instructions with _e32 use the 32-bit encoding.
|
||||
// Instructions with _e64 use the 64-bit encoding.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Scalar classes
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class SOP1_32 <bits<8> op, string opName, list<dag> pattern>
|
||||
: SOP1 <op, (outs SReg_32:$dst), (ins SSrc_32:$src0), opName, pattern>;
|
||||
|
||||
class SOP1_64 <bits<8> op, string opName, list<dag> pattern>
|
||||
: SOP1 <op, (outs SReg_64:$dst), (ins SSrc_64:$src0), opName, pattern>;
|
||||
|
||||
class SOP2_32 <bits<7> op, string opName, list<dag> pattern>
|
||||
: SOP2 <op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), opName, pattern>;
|
||||
|
||||
class SOP2_64 <bits<7> op, string opName, list<dag> pattern>
|
||||
: SOP2 <op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>;
|
||||
|
||||
class SOPC_32 <bits<7> op, string opName, list<dag> pattern>
|
||||
: SOPC <op, (outs SCCReg:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), opName, pattern>;
|
||||
|
||||
class SOPC_64 <bits<7> op, string opName, list<dag> pattern>
|
||||
: SOPC <op, (outs SCCReg:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>;
|
||||
|
||||
class SOPK_32 <bits<5> op, string opName, list<dag> pattern>
|
||||
: SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
|
||||
|
||||
class SOPK_64 <bits<5> op, string opName, list<dag> pattern>
|
||||
: SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>;
|
||||
|
||||
multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
|
||||
def _IMM : SMRD <
|
||||
op, 1, (outs dstClass:$dst),
|
||||
(ins GPR2Align<SReg_64>:$sbase, i32imm:$offset),
|
||||
asm, []
|
||||
>;
|
||||
|
||||
def _SGPR : SMRD <
|
||||
op, 0, (outs dstClass:$dst),
|
||||
(ins GPR2Align<SReg_64>:$sbase, SReg_32:$soff),
|
||||
asm, []
|
||||
>;
|
||||
}
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector ALU classes
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class VOP3_32 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
|
||||
op, (outs VReg_32:$dst),
|
||||
(ins VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3,
|
||||
i32imm:$src4, i32imm:$src5, i32imm:$src6),
|
||||
opName, pattern
|
||||
>;
|
||||
|
||||
class VOP3_64 <bits<9> op, string opName, list<dag> pattern> : VOP3 <
|
||||
op, (outs VReg_64:$dst),
|
||||
(ins VSrc_64:$src0, VReg_64:$src1, VReg_64:$src2,
|
||||
i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6),
|
||||
opName, pattern
|
||||
>;
|
||||
|
||||
class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
|
||||
string opName, list<dag> pattern> :
|
||||
VOP1 <
|
||||
op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
|
||||
>;
|
||||
|
||||
multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> {
|
||||
def _e32: VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>;
|
||||
def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
|
||||
opName, []
|
||||
>;
|
||||
}
|
||||
|
||||
multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> {
|
||||
|
||||
def _e32 : VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>;
|
||||
|
||||
def _e64 : VOP3_64 <
|
||||
{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
|
||||
opName, []
|
||||
>;
|
||||
}
|
||||
|
||||
class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
|
||||
string opName, list<dag> pattern> :
|
||||
VOP2 <
|
||||
op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
|
||||
>;
|
||||
|
||||
multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
|
||||
|
||||
def _e32 : VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern>;
|
||||
|
||||
def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
|
||||
opName, []
|
||||
>;
|
||||
}
|
||||
|
||||
multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> {
|
||||
def _e32: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>;
|
||||
|
||||
def _e64 : VOP3_64 <
|
||||
{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
|
||||
opName, []
|
||||
>;
|
||||
}
|
||||
|
||||
multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
|
||||
string opName, list<dag> pattern> {
|
||||
|
||||
def _e32 : VOPC <op, (ins arc:$src0, vrc:$src1), opName, pattern>;
|
||||
def _e64 : VOP3 <
|
||||
{0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
|
||||
(outs SReg_64:$dst),
|
||||
(ins arc:$src0, vrc:$src1,
|
||||
InstFlag:$abs, InstFlag:$clamp,
|
||||
InstFlag:$omod, InstFlag:$neg),
|
||||
opName, pattern
|
||||
> {
|
||||
let SRC2 = 0x80;
|
||||
}
|
||||
}
|
||||
|
||||
multiclass VOPC_32 <bits<8> op, string opName, list<dag> pattern>
|
||||
: VOPC_Helper <op, VReg_32, VSrc_32, opName, pattern>;
|
||||
|
||||
multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern>
|
||||
: VOPC_Helper <op, VReg_64, VSrc_64, opName, pattern>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector I/O classes
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
|
||||
op,
|
||||
(outs),
|
||||
(ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
|
||||
VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3),
|
||||
"EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3",
|
||||
[] > {
|
||||
|
||||
bits<4> EN;
|
||||
bits<6> TGT;
|
||||
bits<1> COMPR;
|
||||
bits<1> DONE;
|
||||
bits<1> VM;
|
||||
bits<8> VSRC0;
|
||||
bits<8> VSRC1;
|
||||
bits<8> VSRC2;
|
||||
bits<8> VSRC3;
|
||||
|
||||
let Inst{3-0} = EN;
|
||||
let Inst{9-4} = TGT;
|
||||
let Inst{10} = COMPR;
|
||||
let Inst{11} = DONE;
|
||||
let Inst{12} = VM;
|
||||
let Inst{31-26} = 0x3e;
|
||||
let Inst{39-32} = VSRC0;
|
||||
let Inst{47-40} = VSRC1;
|
||||
let Inst{55-48} = VSRC2;
|
||||
let Inst{63-56} = VSRC3;
|
||||
|
||||
let EXP_CNT = 1;
|
||||
}
|
||||
|
||||
class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc64 <outs, ins, asm, pattern> {
|
||||
|
||||
bits<8> VDATA;
|
||||
bits<4> DMASK;
|
||||
bits<1> UNORM;
|
||||
bits<1> GLC;
|
||||
bits<1> DA;
|
||||
bits<1> R128;
|
||||
bits<1> TFE;
|
||||
bits<1> LWE;
|
||||
bits<1> SLC;
|
||||
bits<8> VADDR;
|
||||
bits<5> SRSRC;
|
||||
bits<5> SSAMP;
|
||||
|
||||
let Inst{11-8} = DMASK;
|
||||
let Inst{12} = UNORM;
|
||||
let Inst{13} = GLC;
|
||||
let Inst{14} = DA;
|
||||
let Inst{15} = R128;
|
||||
let Inst{16} = TFE;
|
||||
let Inst{17} = LWE;
|
||||
let Inst{24-18} = op;
|
||||
let Inst{25} = SLC;
|
||||
let Inst{31-26} = 0x3c;
|
||||
let Inst{39-32} = VADDR;
|
||||
let Inst{47-40} = VDATA;
|
||||
let Inst{52-48} = SRSRC;
|
||||
let Inst{57-53} = SSAMP;
|
||||
|
||||
let VM_CNT = 1;
|
||||
let EXP_CNT = 1;
|
||||
}
|
||||
|
||||
class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc64<outs, ins, asm, pattern> {
|
||||
|
||||
bits<8> VDATA;
|
||||
bits<12> OFFSET;
|
||||
bits<1> OFFEN;
|
||||
bits<1> IDXEN;
|
||||
bits<1> GLC;
|
||||
bits<1> ADDR64;
|
||||
bits<4> DFMT;
|
||||
bits<3> NFMT;
|
||||
bits<8> VADDR;
|
||||
bits<5> SRSRC;
|
||||
bits<1> SLC;
|
||||
bits<1> TFE;
|
||||
bits<8> SOFFSET;
|
||||
|
||||
let Inst{11-0} = OFFSET;
|
||||
let Inst{12} = OFFEN;
|
||||
let Inst{13} = IDXEN;
|
||||
let Inst{14} = GLC;
|
||||
let Inst{15} = ADDR64;
|
||||
let Inst{18-16} = op;
|
||||
let Inst{22-19} = DFMT;
|
||||
let Inst{25-23} = NFMT;
|
||||
let Inst{31-26} = 0x3a; //encoding
|
||||
let Inst{39-32} = VADDR;
|
||||
let Inst{47-40} = VDATA;
|
||||
let Inst{52-48} = SRSRC;
|
||||
let Inst{54} = SLC;
|
||||
let Inst{55} = TFE;
|
||||
let Inst{63-56} = SOFFSET;
|
||||
|
||||
let VM_CNT = 1;
|
||||
let EXP_CNT = 1;
|
||||
|
||||
let neverHasSideEffects = 1;
|
||||
}
|
||||
|
||||
class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc64<outs, ins, asm, pattern> {
|
||||
|
||||
bits<8> VDATA;
|
||||
bits<12> OFFSET;
|
||||
bits<1> OFFEN;
|
||||
bits<1> IDXEN;
|
||||
bits<1> GLC;
|
||||
bits<1> ADDR64;
|
||||
bits<1> LDS;
|
||||
bits<8> VADDR;
|
||||
bits<5> SRSRC;
|
||||
bits<1> SLC;
|
||||
bits<1> TFE;
|
||||
bits<8> SOFFSET;
|
||||
|
||||
let Inst{11-0} = OFFSET;
|
||||
let Inst{12} = OFFEN;
|
||||
let Inst{13} = IDXEN;
|
||||
let Inst{14} = GLC;
|
||||
let Inst{15} = ADDR64;
|
||||
let Inst{16} = LDS;
|
||||
let Inst{24-18} = op;
|
||||
let Inst{31-26} = 0x38; //encoding
|
||||
let Inst{39-32} = VADDR;
|
||||
let Inst{47-40} = VDATA;
|
||||
let Inst{52-48} = SRSRC;
|
||||
let Inst{54} = SLC;
|
||||
let Inst{55} = TFE;
|
||||
let Inst{63-56} = SOFFSET;
|
||||
|
||||
let VM_CNT = 1;
|
||||
let EXP_CNT = 1;
|
||||
|
||||
let neverHasSideEffects = 1;
|
||||
}
|
||||
|
||||
} // End Uses = [EXEC]
|
||||
|
||||
class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
|
||||
list<dag> pattern> : Enc32<outs, ins, asm, pattern> {
|
||||
|
||||
bits<7> SDST;
|
||||
bits<6> SBASE;
|
||||
bits<8> OFFSET;
|
||||
|
||||
let Inst{7-0} = OFFSET;
|
||||
let Inst{8} = imm;
|
||||
let Inst{14-9} = SBASE;
|
||||
let Inst{21-15} = SDST;
|
||||
let Inst{26-22} = op;
|
||||
let Inst{31-27} = 0x18; //encoding
|
||||
|
||||
let LGKM_CNT = 1;
|
||||
}
|
||||
|
||||
class SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc32<outs, ins, asm, pattern> {
|
||||
|
||||
bits<7> SDST;
|
||||
bits<8> SSRC0;
|
||||
|
||||
let Inst{7-0} = SSRC0;
|
||||
let Inst{15-8} = op;
|
||||
let Inst{22-16} = SDST;
|
||||
let Inst{31-23} = 0x17d; //encoding;
|
||||
|
||||
let mayLoad = 0;
|
||||
let mayStore = 0;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc32 <outs, ins, asm, pattern> {
|
||||
|
||||
bits<7> SDST;
|
||||
bits<8> SSRC0;
|
||||
bits<8> SSRC1;
|
||||
|
||||
let Inst{7-0} = SSRC0;
|
||||
let Inst{15-8} = SSRC1;
|
||||
let Inst{22-16} = SDST;
|
||||
let Inst{29-23} = op;
|
||||
let Inst{31-30} = 0x2; // encoding
|
||||
|
||||
let mayLoad = 0;
|
||||
let mayStore = 0;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc32<outs, ins, asm, pattern> {
|
||||
|
||||
bits<8> SSRC0;
|
||||
bits<8> SSRC1;
|
||||
|
||||
let Inst{7-0} = SSRC0;
|
||||
let Inst{15-8} = SSRC1;
|
||||
let Inst{22-16} = op;
|
||||
let Inst{31-23} = 0x17e;
|
||||
|
||||
let DisableEncoding = "$dst";
|
||||
let mayLoad = 0;
|
||||
let mayStore = 0;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc32 <outs, ins , asm, pattern> {
|
||||
|
||||
bits <7> SDST;
|
||||
bits <16> SIMM16;
|
||||
|
||||
let Inst{15-0} = SIMM16;
|
||||
let Inst{22-16} = SDST;
|
||||
let Inst{27-23} = op;
|
||||
let Inst{31-28} = 0xb; //encoding
|
||||
|
||||
let mayLoad = 0;
|
||||
let mayStore = 0;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 <
|
||||
(outs),
|
||||
ins,
|
||||
(ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
|
||||
i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
|
||||
GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
|
||||
asm,
|
||||
pattern > {
|
||||
|
||||
bits <16> SIMM16;
|
||||
|
||||
let Inst{15-0} = SIMM16;
|
||||
let Inst{22-16} = op;
|
||||
let Inst{31-23} = 0x17f; // encoding
|
||||
|
||||
[]> {
|
||||
let mayStore = 1;
|
||||
let mayLoad = 0;
|
||||
let mayStore = 0;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
let Uses = [EXEC] in {
|
||||
|
||||
class VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc32 <outs, ins, asm, pattern> {
|
||||
|
||||
bits<8> VDST;
|
||||
bits<8> VSRC;
|
||||
bits<2> ATTRCHAN;
|
||||
bits<6> ATTR;
|
||||
|
||||
let Inst{7-0} = VSRC;
|
||||
let Inst{9-8} = ATTRCHAN;
|
||||
let Inst{15-10} = ATTR;
|
||||
let Inst{17-16} = op;
|
||||
let Inst{25-18} = VDST;
|
||||
let Inst{31-26} = 0x32; // encoding
|
||||
|
||||
let neverHasSideEffects = 1;
|
||||
class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
|
||||
op,
|
||||
(outs regClass:$dst),
|
||||
(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
|
||||
i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
|
||||
i1imm:$tfe, SSrc_32:$soffset),
|
||||
asm,
|
||||
[]> {
|
||||
let mayLoad = 1;
|
||||
let mayStore = 0;
|
||||
}
|
||||
|
||||
class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc32 <outs, ins, asm, pattern> {
|
||||
|
||||
bits<8> VDST;
|
||||
bits<9> SRC0;
|
||||
|
||||
let Inst{8-0} = SRC0;
|
||||
let Inst{16-9} = op;
|
||||
let Inst{24-17} = VDST;
|
||||
let Inst{31-25} = 0x3f; //encoding
|
||||
|
||||
let mayLoad = 0;
|
||||
class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
|
||||
op,
|
||||
(outs regClass:$dst),
|
||||
(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
|
||||
i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
|
||||
i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset),
|
||||
asm,
|
||||
[]> {
|
||||
let mayLoad = 1;
|
||||
let mayStore = 0;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc32 <outs, ins, asm, pattern> {
|
||||
|
||||
bits<8> VDST;
|
||||
bits<9> SRC0;
|
||||
bits<8> VSRC1;
|
||||
|
||||
let Inst{8-0} = SRC0;
|
||||
let Inst{16-9} = VSRC1;
|
||||
let Inst{24-17} = VDST;
|
||||
let Inst{30-25} = op;
|
||||
let Inst{31} = 0x0; //encoding
|
||||
|
||||
let mayLoad = 0;
|
||||
class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
|
||||
op,
|
||||
(outs VReg_128:$vdata),
|
||||
(ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
|
||||
i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
|
||||
GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
|
||||
asm,
|
||||
[]> {
|
||||
let mayLoad = 1;
|
||||
let mayStore = 0;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
class VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc64 <outs, ins, asm, pattern> {
|
||||
|
||||
bits<8> VDST;
|
||||
bits<9> SRC0;
|
||||
bits<9> SRC1;
|
||||
bits<9> SRC2;
|
||||
bits<3> ABS;
|
||||
bits<1> CLAMP;
|
||||
bits<2> OMOD;
|
||||
bits<3> NEG;
|
||||
|
||||
let Inst{7-0} = VDST;
|
||||
let Inst{10-8} = ABS;
|
||||
let Inst{11} = CLAMP;
|
||||
let Inst{25-17} = op;
|
||||
let Inst{31-26} = 0x34; //encoding
|
||||
let Inst{40-32} = SRC0;
|
||||
let Inst{49-41} = SRC1;
|
||||
let Inst{58-50} = SRC2;
|
||||
let Inst{60-59} = OMOD;
|
||||
let Inst{63-61} = NEG;
|
||||
|
||||
let mayLoad = 0;
|
||||
let mayStore = 0;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
class VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> :
|
||||
Enc64 <outs, ins, asm, pattern> {
|
||||
|
||||
bits<8> VDST;
|
||||
bits<9> SRC0;
|
||||
bits<9> SRC1;
|
||||
bits<9> SRC2;
|
||||
bits<7> SDST;
|
||||
bits<2> OMOD;
|
||||
bits<3> NEG;
|
||||
|
||||
let Inst{7-0} = VDST;
|
||||
let Inst{14-8} = SDST;
|
||||
let Inst{25-17} = op;
|
||||
let Inst{31-26} = 0x34; //encoding
|
||||
let Inst{40-32} = SRC0;
|
||||
let Inst{49-41} = SRC1;
|
||||
let Inst{58-50} = SRC2;
|
||||
let Inst{60-59} = OMOD;
|
||||
let Inst{63-61} = NEG;
|
||||
|
||||
let mayLoad = 0;
|
||||
let mayStore = 0;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> :
|
||||
Enc32 <(outs VCCReg:$dst), ins, asm, pattern> {
|
||||
|
||||
bits<9> SRC0;
|
||||
bits<8> VSRC1;
|
||||
|
||||
let Inst{8-0} = SRC0;
|
||||
let Inst{16-9} = VSRC1;
|
||||
let Inst{24-17} = op;
|
||||
let Inst{31-25} = 0x3e;
|
||||
|
||||
let DisableEncoding = "$dst";
|
||||
let mayLoad = 0;
|
||||
let mayStore = 0;
|
||||
let hasSideEffects = 0;
|
||||
}
|
||||
|
||||
} // End Uses = [EXEC]
|
||||
|
||||
include "SIInstrFormats.td"
|
||||
include "SIInstructions.td"
|
||||
|
|
|
|||
Loading…
Reference in New Issue