forked from OSchip/llvm-project
Reland "[WebAssembly] Emulate v128.const efficiently""
This reverts commit432e4e56d3, which reverted542523a61a. Two issues from the original commit have been fixed. First, MSVC does not like when std::array is initialized with only single braces, so this commit switches to using the more portable double braces. Second, there was a subtle endianness bug that prevented the original commit from working correctly on big-endian machines, which has been fixed by switching to using endianness-agnostic bit twiddling instead of type punning. Differential Revision: https://reviews.llvm.org/D88773
This commit is contained in:
Thomas Lively
parent
b3b4cda104
commit
72c628e835
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@ -31,6 +31,7 @@
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#include "llvm/IR/IntrinsicsWebAssembly.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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@ -1565,6 +1566,7 @@ SDValue WebAssemblyTargetLowering::LowerBUILD_VECTOR(SDValue Op,
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};
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} else if (NumConstantLanes >= NumSplatLanes &&
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Subtarget->hasUnimplementedSIMD128()) {
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// If we support v128.const, emit it directly
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SmallVector<SDValue, 16> ConstLanes;
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for (const SDValue &Lane : Op->op_values()) {
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if (IsConstant(Lane)) {
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@ -1576,11 +1578,59 @@ SDValue WebAssemblyTargetLowering::LowerBUILD_VECTOR(SDValue Op,
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}
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}
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Result = DAG.getBuildVector(VecT, DL, ConstLanes);
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IsLaneConstructed = [&](size_t _, const SDValue &Lane) {
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IsLaneConstructed = [&IsConstant](size_t _, const SDValue &Lane) {
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return IsConstant(Lane);
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};
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}
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if (!Result) {
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} else if (NumConstantLanes >= NumSplatLanes && VecT.isInteger()) {
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// Otherwise, if this is an integer vector, pack the lane values together so
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// we can construct the 128-bit constant from a pair of i64s using a splat
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// followed by at most one i64x2.replace_lane. Also keep track of the lanes
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// that actually matter so we can avoid the replace_lane in more cases.
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std::array<uint64_t, 2> I64s{{0, 0}};
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std::array<uint64_t, 2> ConstLaneMasks{{0, 0}};
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size_t LaneBits = 128 / Lanes;
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size_t HalfLanes = Lanes / 2;
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for (size_t I = 0; I < Lanes; ++I) {
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const SDValue &Lane = Op.getOperand(I);
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if (IsConstant(Lane)) {
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// How much we need to shift Val to position it in an i64
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auto Shift = LaneBits * (I % HalfLanes);
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auto Mask = maskTrailingOnes<uint64_t>(LaneBits);
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auto Val = cast<ConstantSDNode>(Lane.getNode())->getZExtValue() & Mask;
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I64s[I / HalfLanes] |= Val << Shift;
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ConstLaneMasks[I / HalfLanes] |= Mask << Shift;
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}
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}
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// Check whether all constant lanes in the second half of the vector are
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// equivalent in the first half or vice versa to determine whether splatting
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// either side will be sufficient to materialize the constant. As a special
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// case, if the first and second halves have no constant lanes in common, we
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// can just combine them.
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bool FirstHalfSufficient = (I64s[0] & ConstLaneMasks[1]) == I64s[1];
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bool SecondHalfSufficient = (I64s[1] & ConstLaneMasks[0]) == I64s[0];
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bool CombinedSufficient = (ConstLaneMasks[0] & ConstLaneMasks[1]) == 0;
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uint64_t Splatted;
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if (SecondHalfSufficient) {
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Splatted = I64s[1];
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} else if (CombinedSufficient) {
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Splatted = I64s[0] | I64s[1];
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} else {
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Splatted = I64s[0];
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}
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Result = DAG.getSplatBuildVector(MVT::v2i64, DL,
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DAG.getConstant(Splatted, DL, MVT::i64));
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if (!FirstHalfSufficient && !SecondHalfSufficient && !CombinedSufficient) {
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Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, MVT::v2i64, Result,
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DAG.getConstant(I64s[1], DL, MVT::i64),
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DAG.getConstant(1, DL, MVT::i32));
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}
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Result = DAG.getBitcast(VecT, Result);
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IsLaneConstructed = [&IsConstant](size_t _, const SDValue &Lane) {
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return IsConstant(Lane);
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};
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} else {
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// Use a splat, but possibly a load_splat
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LoadSDNode *SplattedLoad;
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if ((SplattedLoad = dyn_cast<LoadSDNode>(SplatValue)) &&
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@ -1593,11 +1643,14 @@ SDValue WebAssemblyTargetLowering::LowerBUILD_VECTOR(SDValue Op,
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} else {
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Result = DAG.getSplatBuildVector(VecT, DL, SplatValue);
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}
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IsLaneConstructed = [&](size_t _, const SDValue &Lane) {
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IsLaneConstructed = [&SplatValue](size_t _, const SDValue &Lane) {
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return Lane == SplatValue;
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};
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}
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assert(Result);
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assert(IsLaneConstructed);
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// Add replace_lane instructions for any unhandled values
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for (size_t I = 0; I < Lanes; ++I) {
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const SDValue &Lane = Op->getOperand(I);
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@ -8,12 +8,95 @@
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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; CHECK-LABEL: emulated_const_trivial_splat:
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; CHECK-NEXT: .functype emulated_const_trivial_splat () -> (v128)
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; SIMD-VM-NEXT: i64.const $push0=, 8589934593
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; SIMD-VM-NEXT: i64x2.splat $push1=, $pop0
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; SIMD-VM-NEXT: return $pop1
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; UNIMP: v128.const
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define <4 x i32> @emulated_const_trivial_splat() {
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ret <4 x i32> <i32 1, i32 2, i32 1, i32 2>
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}
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; CHECK-LABEL: emulated_const_first_sufficient:
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; CHECK-NEXT: .functype emulated_const_first_sufficient () -> (v128)
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; SIMD-VM-NEXT: i64.const $push0=, 8589934593
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; SIMD-VM-NEXT: i64x2.splat $push1=, $pop0
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; SIMD-VM-NEXT: return $pop1
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; UNIMP: v128.const
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define <4 x i32> @emulated_const_first_sufficient() {
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ret <4 x i32> <i32 1, i32 2, i32 undef, i32 2>
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}
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; CHECK-LABEL: emulated_const_second_sufficient:
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; CHECK-NEXT: .functype emulated_const_second_sufficient () -> (v128)
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; SIMD-VM-NEXT: i64.const $push0=, 8589934593
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; SIMD-VM-NEXT: i64x2.splat $push1=, $pop0
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; SIMD-VM-NEXT: return $pop1
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; UNIMP: v128.const
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define <4 x i32> @emulated_const_second_sufficient() {
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ret <4 x i32> <i32 1, i32 undef, i32 1, i32 2>
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}
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; CHECK-LABEL: emulated_const_combined_sufficient:
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; CHECK-NEXT: .functype emulated_const_combined_sufficient () -> (v128)
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; SIMD-VM-NEXT: i64.const $push0=, 8589934593
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; SIMD-VM-NEXT: i64x2.splat $push1=, $pop0
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; SIMD-VM-NEXT: return $pop1
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; UNIMP: v128.const
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define <4 x i32> @emulated_const_combined_sufficient() {
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ret <4 x i32> <i32 1, i32 undef, i32 undef, i32 2>
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}
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; CHECK-LABEL: emulated_const_either_sufficient:
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; CHECK-NEXT: .functype emulated_const_either_sufficient () -> (v128)
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; SIMD-VM-NEXT: i64.const $push0=, 1
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; SIMD-VM-NEXT: i64x2.splat $push1=, $pop0
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; SIMD-VM-NEXT: return $pop1
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; UNIMP: v128.const
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define <4 x i32> @emulated_const_either_sufficient() {
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ret <4 x i32> <i32 1, i32 undef, i32 1, i32 undef>
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}
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; CHECK-LABEL: emulated_const_neither_sufficient:
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; CHECK-NEXT: .functype emulated_const_neither_sufficient () -> (v128)
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; SIMD-VM-NEXT: i64.const $push0=, 8589934593
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; SIMD-VM-NEXT: i64x2.splat $push1=, $pop0
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; SIMD-VM-NEXT: i64.const $push2=, 17179869184
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; SIMD-VM-NEXT: i64x2.replace_lane $push3=, $pop1, 1, $pop2
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; SIMD-VM-NEXT: return $pop3
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define <4 x i32> @emulated_const_neither_sufficient() {
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ret <4 x i32> <i32 1, i32 2, i32 undef, i32 4>
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}
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; CHECK-LABEL: emulated_const_combined_sufficient_large:
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; CHECK-NEXT: .functype emulated_const_combined_sufficient_large () -> (v128)
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; SIMD-VM-NEXT: i64.const $push0=, 506097522914230528
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; SIMD-VM-NEXT: i64x2.splat $push1=, $pop0
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; SIMD-VM-NEXT: return $pop1
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define <16 x i8> @emulated_const_combined_sufficient_large() {
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ret <16 x i8> <i8 0, i8 undef, i8 2, i8 undef, i8 4, i8 undef, i8 6, i8 undef,
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i8 undef, i8 1, i8 undef, i8 3, i8 undef, i8 5, i8 undef, i8 7>
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}
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; CHECK-LABEL: emulated_const_neither_sufficient_large:
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; CHECK-NEXT: .functype emulated_const_neither_sufficient_large () -> (v128)
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; SIMD-VM-NEXT: i64.const $push0=, -70368726997663744
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; SIMD-VM-NEXT: i64x2.splat $push1=, $pop0
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; SIMD-VM-NEXT: i64.const $push2=, 504408655873966336
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; SIMD-VM-NEXT: i64x2.replace_lane $push3=, $pop1, 1, $pop2
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; SIMD-VM-NEXT: return $pop3
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define <16 x i8> @emulated_const_neither_sufficient_large() {
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ret <16 x i8> <i8 0, i8 undef, i8 2, i8 undef, i8 4, i8 undef, i8 6, i8 255,
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i8 undef, i8 1, i8 undef, i8 3, i8 undef, i8 5, i8 undef, i8 7>
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}
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; CHECK-LABEL: same_const_one_replaced_i16x8:
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; CHECK-NEXT: .functype same_const_one_replaced_i16x8 (i32) -> (v128)
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; UNIMP-NEXT: v128.const $push[[L0:[0-9]+]]=, 42, 42, 42, 42, 42, 0, 42, 42
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; UNIMP-NEXT: i16x8.replace_lane $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0
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; UNIMP-NEXT: return $pop[[L1]]
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; SIMD-VM: i16x8.splat
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; SIMD-VM: i64x2.splat
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define <8 x i16> @same_const_one_replaced_i16x8(i16 %x) {
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%v = insertelement
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<8 x i16> <i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42, i16 42>,
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@ -27,7 +110,7 @@ define <8 x i16> @same_const_one_replaced_i16x8(i16 %x) {
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; UNIMP-NEXT: v128.const $push[[L0:[0-9]+]]=, 1, -2, 3, -4, 5, 0, 7, -8
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; UNIMP-NEXT: i16x8.replace_lane $push[[L1:[0-9]+]]=, $pop[[L0]], 5, $0
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; UNIMP-NEXT: return $pop[[L1]]
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; SIMD-VM: i16x8.splat
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; SIMD-VM: i64x2.splat
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define <8 x i16> @different_const_one_replaced_i16x8(i16 %x) {
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%v = insertelement
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<8 x i16> <i16 1, i16 -2, i16 3, i16 -4, i16 5, i16 -6, i16 7, i16 -8>,
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@ -68,7 +151,7 @@ define <4 x float> @different_const_one_replaced_f32x4(float %x) {
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; CHECK-NEXT: .functype splat_common_const_i32x4 () -> (v128)
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; UNIMP-NEXT: v128.const $push[[L0:[0-9]+]]=, 0, 3, 3, 1
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; UNIMP-NEXT: return $pop[[L0]]
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; SIMD-VM: i32x4.splat
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; SIMD-VM: i64x2.splat
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define <4 x i32> @splat_common_const_i32x4() {
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ret <4 x i32> <i32 undef, i32 3, i32 3, i32 1>
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}
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@ -206,7 +289,7 @@ define <16 x i8> @mashup_swizzle_i8x16(<16 x i8> %src, <16 x i8> %mask, i8 %spla
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; UNIMP: i8x16.replace_lane
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; UNIMP: i8x16.replace_lane
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; UNIMP: return
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; SIMD-VM: i8x16.splat
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; SIMD-VM: i64x2.splat
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define <16 x i8> @mashup_const_i8x16(<16 x i8> %src, <16 x i8> %mask, i8 %splatted) {
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; swizzle 0
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%m0 = extractelement <16 x i8> %mask, i32 0
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