forked from OSchip/llvm-project
GlobalISel: Implement moreElementsVector for phi
llvm-svn: 355047
This commit is contained in:
Matt Arsenault
parent
52b751088b
commit
72bcf15dbf
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@ -186,6 +186,9 @@ private:
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LegalizeResult
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fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
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LegalizeResult moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
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LLT MoreTy);
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LegalizeResult
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reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
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@ -2392,6 +2392,25 @@ LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
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return Legalized;
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
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LLT MoreTy) {
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assert(TypeIdx == 0 && "Expecting only Idx 0");
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Observer.changingInstr(MI);
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for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
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MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
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MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
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moreElementsVectorSrc(MI, MoreTy, I);
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}
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MachineBasicBlock &MBB = *MI.getParent();
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MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
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moreElementsVectorDst(MI, MoreTy, 0);
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Observer.changedInstr(MI);
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return Legalized;
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}
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LegalizerHelper::LegalizeResult
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LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
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LLT MoreTy) {
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@ -2441,6 +2460,8 @@ LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
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moreElementsVectorDst(MI, MoreTy, 0);
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Observer.changedInstr(MI);
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return Legalized;
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case TargetOpcode::G_PHI:
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return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
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default:
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return UnableToLegalize;
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}
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@ -159,6 +159,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST,
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.legalFor(AddrSpaces32)
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.clampScalar(0, S32, S256)
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.widenScalarToNextPow2(0, 32)
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.moreElementsIf(isSmallOddVector(0), oneMoreElement(0))
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.legalIf(isPointer(0));
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@ -102,7 +102,80 @@ body: |
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$vgpr0 = COPY %6
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S_SETPC_B64 undef $sgpr30_sgpr31
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...
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---
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name: test_phi_v3s16
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: test_phi_v3s16
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
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; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $vgpr0_vgpr1
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; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
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; CHECK: [[EXTRACT:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[COPY]](<4 x s16>), 0
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; CHECK: [[DEF:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
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; CHECK: [[INSERT:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF]], [[EXTRACT]](<3 x s16>), 0
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; CHECK: G_BRCOND [[ICMP]](s1), %bb.1
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; CHECK: G_BR %bb.2
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
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; CHECK: [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[EXTRACT]](<3 x s16>)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16)
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; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[UV3]](s16)
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; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT]], [[ANYEXT1]]
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; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
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; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16)
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; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV4]](s16)
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; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT2]], [[ANYEXT3]]
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; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD1]](s32)
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; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16)
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; CHECK: [[ANYEXT5:%[0-9]+]]:_(s32) = G_ANYEXT [[UV5]](s16)
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; CHECK: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[ANYEXT4]], [[ANYEXT5]]
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; CHECK: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[ADD2]](s32)
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; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16), [[TRUNC2]](s16)
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; CHECK: [[DEF1:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
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; CHECK: [[INSERT1:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF1]], [[BUILD_VECTOR]](<3 x s16>), 0
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; CHECK: G_BR %bb.2
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; CHECK: bb.2:
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; CHECK: [[PHI:%[0-9]+]]:_(<4 x s16>) = G_PHI [[INSERT]](<4 x s16>), %bb.0, [[INSERT1]](<4 x s16>), %bb.1
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; CHECK: [[EXTRACT1:%[0-9]+]]:_(<3 x s16>) = G_EXTRACT [[PHI]](<4 x s16>), 0
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; CHECK: [[DEF2:%[0-9]+]]:_(<4 x s16>) = G_IMPLICIT_DEF
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; CHECK: [[INSERT2:%[0-9]+]]:_(<4 x s16>) = G_INSERT [[DEF2]], [[EXTRACT1]](<3 x s16>), 0
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; CHECK: $vgpr0_vgpr1 = COPY [[INSERT2]](<4 x s16>)
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; CHECK: S_SETPC_B64 undef $sgpr30_sgpr31
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bb.0:
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successors: %bb.1, %bb.2
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liveins: $vgpr0_vgpr1, $vgpr2
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%0:_(<4 x s16>) = COPY $vgpr0_vgpr1
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%1:_(s32) = COPY $vgpr2
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(s1) = G_ICMP intpred(eq), %1, %2
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%4:_(<3 x s16>) = G_EXTRACT %0, 0
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G_BRCOND %3, %bb.1
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G_BR %bb.2
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bb.1:
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successors: %bb.2
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%5:_(<3 x s16>) = G_ADD %4, %4
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G_BR %bb.2
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bb.2:
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%6:_(<3 x s16>) = G_PHI %4, %bb.0, %5, %bb.1
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%7:_(<4 x s16>) = G_IMPLICIT_DEF
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%8:_(<4 x s16>) = G_INSERT %7, %6, 0
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$vgpr0_vgpr1 = COPY %8
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S_SETPC_B64 undef $sgpr30_sgpr31
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...
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---
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name: test_phi_v4s16
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tracksRegLiveness: true
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