forked from OSchip/llvm-project
[TargetLowering] Add BuildSDiv support for division by one or negone.
This reduces most of the sdiv stages (the MULHS, shifts etc.) to just zero/identity values and use the numerator scale factor to multiply by +1/-1. llvm-svn: 340260
This commit is contained in:
Simon Pilgrim
parent
3cd1d27b58
commit
72b324de4d
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@ -3524,27 +3524,35 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
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if (N->getFlags().hasExact())
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return BuildExactSDIV(*this, N, dl, DAG, Created);
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SmallVector<SDValue, 16> MagicFactors, Factors, Shifts;
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SmallVector<SDValue, 16> MagicFactors, Factors, Shifts, ShiftMasks;
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auto BuildSDIVPattern = [&](ConstantSDNode *C) {
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// TODO: Handle sdiv by one and neg-one.
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if (C->isNullValue() || C->isOne() || C->isAllOnesValue())
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if (C->isNullValue())
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return false;
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const APInt &Divisor = C->getAPIntValue();
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APInt::ms magics = Divisor.magic();
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int NumeratorFactor = 0;
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int ShiftMask = -1;
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// If d > 0 and m < 0, add the numerator.
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if (Divisor.isStrictlyPositive() && magics.m.isNegative())
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if (Divisor.isOneValue() || Divisor.isAllOnesValue()) {
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// If d is +1/-1, we just multiply the numerator by +1/-1.
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NumeratorFactor = Divisor.getSExtValue();
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magics.m = 0;
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magics.s = 0;
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ShiftMask = 0;
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} else if (Divisor.isStrictlyPositive() && magics.m.isNegative()) {
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// If d > 0 and m < 0, add the numerator.
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NumeratorFactor = 1;
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// If d < 0 and m > 0, subtract the numerator.
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else if (Divisor.isNegative() && magics.m.isStrictlyPositive())
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} else if (Divisor.isNegative() && magics.m.isStrictlyPositive()) {
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// If d < 0 and m > 0, subtract the numerator.
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NumeratorFactor = -1;
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}
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MagicFactors.push_back(DAG.getConstant(magics.m, dl, SVT));
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Factors.push_back(DAG.getConstant(NumeratorFactor, dl, SVT));
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Shifts.push_back(DAG.getConstant(magics.s, dl, ShSVT));
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ShiftMasks.push_back(DAG.getConstant(ShiftMask, dl, SVT));
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return true;
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};
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@ -3555,19 +3563,21 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
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if (!ISD::matchUnaryPredicate(N1, BuildSDIVPattern))
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return SDValue();
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SDValue MagicFactor, Factor, Shift;
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SDValue MagicFactor, Factor, Shift, ShiftMask;
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if (VT.isVector()) {
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MagicFactor = DAG.getBuildVector(VT, dl, MagicFactors);
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Factor = DAG.getBuildVector(VT, dl, Factors);
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Shift = DAG.getBuildVector(ShVT, dl, Shifts);
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ShiftMask = DAG.getBuildVector(VT, dl, ShiftMasks);
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} else {
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MagicFactor = MagicFactors[0];
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Factor = Factors[0];
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Shift = Shifts[0];
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ShiftMask = ShiftMasks[0];
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}
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// Multiply the numerator (operand 0) by the magic value
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// FIXME: We should support doing a MUL in a wider type
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// Multiply the numerator (operand 0) by the magic value.
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// FIXME: We should support doing a MUL in a wider type.
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SDValue Q;
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if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT)
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: isOperationLegalOrCustom(ISD::MULHS, VT))
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@ -3578,7 +3588,7 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
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DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), N0, MagicFactor);
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Q = SDValue(LoHi.getNode(), 1);
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} else
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return SDValue(); // No mulhs or equivalent
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return SDValue(); // No mulhs or equivalent.
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Created.push_back(Q.getNode());
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// (Optionally) Add/subtract the numerator using Factor.
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@ -3591,9 +3601,11 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
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Q = DAG.getNode(ISD::SRA, dl, VT, Q, Shift);
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Created.push_back(Q.getNode());
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// Extract the sign bit and add it to the quotient
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SDValue T =
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DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(EltBits - 1, dl, ShVT));
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// Extract the sign bit, mask it and add it to the quotient.
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SDValue SignShift = DAG.getConstant(EltBits - 1, dl, ShVT);
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SDValue T = DAG.getNode(ISD::SRL, dl, VT, Q, SignShift);
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Created.push_back(T.getNode());
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T = DAG.getNode(ISD::AND, dl, VT, T, ShiftMask);
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Created.push_back(T.getNode());
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return DAG.getNode(ISD::ADD, dl, VT, Q, T);
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}
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@ -2378,124 +2378,101 @@ define <8 x i16> @combine_vec_sdiv_nonuniform5(<8 x i16> %x) {
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define <8 x i16> @combine_vec_sdiv_nonuniform6(<8 x i16> %x) {
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; SSE-LABEL: combine_vec_sdiv_nonuniform6:
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; SSE: # %bb.0:
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; SSE-NEXT: pextrw $5, %xmm0, %eax
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; SSE-NEXT: movswl %ax, %ecx
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; SSE-NEXT: imull $-32639, %ecx, %ecx # imm = 0x8081
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; SSE-NEXT: shrl $16, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: movzwl %cx, %eax
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; SSE-NEXT: sarw $7, %cx
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; SSE-NEXT: shrl $15, %eax
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; SSE-NEXT: addl %ecx, %eax
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; SSE-NEXT: pextrw $2, %xmm0, %ecx
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; SSE-NEXT: movswl %cx, %edx
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; SSE-NEXT: imull $32703, %edx, %edx # imm = 0x7FBF
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; SSE-NEXT: shrl $16, %edx
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; SSE-NEXT: subl %ecx, %edx
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; SSE-NEXT: movzwl %dx, %ecx
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; SSE-NEXT: sarw $8, %dx
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; SSE-NEXT: shrl $15, %ecx
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; SSE-NEXT: addl %edx, %ecx
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; SSE-NEXT: pextrw $1, %xmm0, %edx
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; SSE-NEXT: movl %edx, %esi
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; SSE-NEXT: sarw $15, %si
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; SSE-NEXT: movzwl %si, %esi
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; SSE-NEXT: shrl $7, %esi
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; SSE-NEXT: addl %edx, %esi
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; SSE-NEXT: sarw $9, %si
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; SSE-NEXT: negl %esi
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; SSE-NEXT: pextrw $0, %xmm0, %edx
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; SSE-NEXT: xorl %edi, %edi
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; SSE-NEXT: cmpl $32768, %edx # imm = 0x8000
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; SSE-NEXT: sete %dil
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; SSE-NEXT: movd %edi, %xmm1
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; SSE-NEXT: pinsrw $1, %esi, %xmm1
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; SSE-NEXT: pinsrw $2, %ecx, %xmm1
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; SSE-NEXT: pextrw $3, %xmm0, %ecx
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; SSE-NEXT: negl %ecx
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; SSE-NEXT: pinsrw $3, %ecx, %xmm1
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4],xmm1[5,6,7]
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; SSE-NEXT: pinsrw $5, %eax, %xmm1
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; SSE-NEXT: pextrw $6, %xmm0, %eax
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: sarw $15, %cx
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; SSE-NEXT: movzwl %cx, %ecx
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; SSE-NEXT: shrl $7, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: sarw $9, %cx
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; SSE-NEXT: pinsrw $6, %ecx, %xmm1
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; SSE-NEXT: pextrw $7, %xmm0, %eax
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; SSE-NEXT: cwtl
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; SSE-NEXT: movl %eax, %ecx
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; SSE-NEXT: shll $14, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: movl %ecx, %eax
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; SSE-NEXT: shrl $31, %eax
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; SSE-NEXT: sarl $29, %ecx
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; SSE-NEXT: addl %eax, %ecx
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; SSE-NEXT: pinsrw $7, %ecx, %xmm1
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; SSE-NEXT: movdqa {{.*#+}} xmm1 = [65535,65535,65535,65535,1,1,1,0]
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; SSE-NEXT: pmullw %xmm0, %xmm1
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; SSE-NEXT: pmulhw {{.*}}(%rip), %xmm0
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; SSE-NEXT: paddw %xmm1, %xmm0
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; SSE-NEXT: movdqa %xmm0, %xmm1
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; SSE-NEXT: psraw $8, %xmm1
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[3,4,5],xmm1[6,7]
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; SSE-NEXT: movdqa %xmm1, %xmm2
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; SSE-NEXT: psraw $4, %xmm2
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; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0],xmm1[1,2,3,4],xmm2[5],xmm1[6],xmm2[7]
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; SSE-NEXT: movdqa %xmm2, %xmm3
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; SSE-NEXT: psraw $2, %xmm3
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; SSE-NEXT: pblendw {{.*#+}} xmm3 = xmm3[0],xmm2[1,2,3,4],xmm3[5],xmm2[6,7]
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; SSE-NEXT: movdqa %xmm3, %xmm1
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; SSE-NEXT: psraw $1, %xmm1
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; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm3[0,1,2,3,4],xmm1[5],xmm3[6],xmm1[7]
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; SSE-NEXT: psrlw $15, %xmm0
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; SSE-NEXT: pxor %xmm2, %xmm2
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; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm0[0,1,2],xmm2[3,4],xmm0[5,6,7]
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; SSE-NEXT: paddw %xmm2, %xmm1
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; SSE-NEXT: movdqa %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: combine_vec_sdiv_nonuniform6:
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; AVX: # %bb.0:
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; AVX-NEXT: vpextrw $5, %xmm0, %eax
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; AVX-NEXT: movswl %ax, %ecx
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; AVX-NEXT: imull $-32639, %ecx, %ecx # imm = 0x8081
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; AVX-NEXT: shrl $16, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: movzwl %cx, %eax
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; AVX-NEXT: sarw $7, %cx
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; AVX-NEXT: shrl $15, %eax
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; AVX-NEXT: addl %ecx, %eax
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; AVX-NEXT: vpextrw $2, %xmm0, %ecx
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; AVX-NEXT: movswl %cx, %edx
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; AVX-NEXT: imull $32703, %edx, %edx # imm = 0x7FBF
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; AVX-NEXT: shrl $16, %edx
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; AVX-NEXT: subl %ecx, %edx
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; AVX-NEXT: movzwl %dx, %ecx
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; AVX-NEXT: sarw $8, %dx
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; AVX-NEXT: shrl $15, %ecx
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; AVX-NEXT: addl %edx, %ecx
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; AVX-NEXT: vpextrw $1, %xmm0, %edx
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; AVX-NEXT: movl %edx, %esi
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; AVX-NEXT: sarw $15, %si
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; AVX-NEXT: movzwl %si, %esi
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; AVX-NEXT: shrl $7, %esi
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; AVX-NEXT: addl %edx, %esi
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; AVX-NEXT: sarw $9, %si
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; AVX-NEXT: negl %esi
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; AVX-NEXT: vpextrw $0, %xmm0, %edx
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; AVX-NEXT: xorl %edi, %edi
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; AVX-NEXT: cmpl $32768, %edx # imm = 0x8000
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; AVX-NEXT: sete %dil
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; AVX-NEXT: vmovd %edi, %xmm1
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; AVX-NEXT: vpinsrw $1, %esi, %xmm1, %xmm1
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; AVX-NEXT: vpinsrw $2, %ecx, %xmm1, %xmm1
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; AVX-NEXT: vpextrw $3, %xmm0, %ecx
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; AVX-NEXT: negl %ecx
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; AVX-NEXT: vpinsrw $3, %ecx, %xmm1, %xmm1
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; AVX-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4],xmm1[5,6,7]
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; AVX-NEXT: vpinsrw $5, %eax, %xmm1, %xmm1
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; AVX-NEXT: vpextrw $6, %xmm0, %eax
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: sarw $15, %cx
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; AVX-NEXT: movzwl %cx, %ecx
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; AVX-NEXT: shrl $7, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: sarw $9, %cx
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; AVX-NEXT: vpinsrw $6, %ecx, %xmm1, %xmm1
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; AVX-NEXT: vpextrw $7, %xmm0, %eax
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; AVX-NEXT: cwtl
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; AVX-NEXT: movl %eax, %ecx
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; AVX-NEXT: shll $14, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: movl %ecx, %eax
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; AVX-NEXT: shrl $31, %eax
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; AVX-NEXT: sarl $29, %ecx
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; AVX-NEXT: addl %eax, %ecx
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; AVX-NEXT: vpinsrw $7, %ecx, %xmm1, %xmm0
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; AVX-NEXT: retq
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; AVX1-LABEL: combine_vec_sdiv_nonuniform6:
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; AVX1: # %bb.0:
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; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm1
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; AVX1-NEXT: vpmulhw {{.*}}(%rip), %xmm0, %xmm0
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; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm0
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; AVX1-NEXT: vpsraw $8, %xmm0, %xmm1
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2],xmm0[3,4,5],xmm1[6,7]
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; AVX1-NEXT: vpsraw $4, %xmm1, %xmm2
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3,4],xmm2[5],xmm1[6],xmm2[7]
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; AVX1-NEXT: vpsraw $2, %xmm1, %xmm2
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0],xmm1[1,2,3,4],xmm2[5],xmm1[6,7]
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; AVX1-NEXT: vpsraw $1, %xmm1, %xmm2
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; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4],xmm2[5],xmm1[6],xmm2[7]
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; AVX1-NEXT: vpsrlw $15, %xmm0, %xmm0
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; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[3,4],xmm0[5,6,7]
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; AVX1-NEXT: vpaddw %xmm0, %xmm1, %xmm0
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; AVX1-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_sdiv_nonuniform6:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm1
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; AVX2-NEXT: vpmulhw {{.*}}(%rip), %xmm0, %xmm0
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; AVX2-NEXT: vpaddw %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpmovsxwd %xmm0, %ymm1
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; AVX2-NEXT: vpsravd {{.*}}(%rip), %ymm1, %ymm1
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; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm2
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; AVX2-NEXT: vpackssdw %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpsrlw $15, %xmm0, %xmm0
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; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX2-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2],xmm2[3,4],xmm0[5,6,7]
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; AVX2-NEXT: vpaddw %xmm0, %xmm1, %xmm0
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; AVX2-NEXT: vzeroupper
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; AVX2-NEXT: retq
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;
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; AVX512F-LABEL: combine_vec_sdiv_nonuniform6:
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; AVX512F: # %bb.0:
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; AVX512F-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm1
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; AVX512F-NEXT: vpmulhw {{.*}}(%rip), %xmm0, %xmm0
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; AVX512F-NEXT: vpaddw %xmm1, %xmm0, %xmm0
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; AVX512F-NEXT: vpsrlw $15, %xmm0, %xmm1
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; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX512F-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3,4],xmm1[5,6,7]
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; AVX512F-NEXT: vpmovsxwd %xmm0, %ymm0
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; AVX512F-NEXT: vpsravd {{.*}}(%rip), %ymm0, %ymm0
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; AVX512F-NEXT: vpmovdw %zmm0, %ymm0
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; AVX512F-NEXT: vpaddw %xmm1, %xmm0, %xmm0
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; AVX512F-NEXT: vzeroupper
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; AVX512F-NEXT: retq
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;
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; AVX512BW-LABEL: combine_vec_sdiv_nonuniform6:
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; AVX512BW: # %bb.0:
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; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm1
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; AVX512BW-NEXT: vpmulhw {{.*}}(%rip), %xmm0, %xmm0
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; AVX512BW-NEXT: vpaddw %xmm1, %xmm0, %xmm0
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; AVX512BW-NEXT: vpsrlw $15, %xmm0, %xmm1
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; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX512BW-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3,4],xmm1[5,6,7]
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; AVX512BW-NEXT: vpsravw {{.*}}(%rip), %xmm0, %xmm0
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; AVX512BW-NEXT: vpaddw %xmm1, %xmm0, %xmm0
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; AVX512BW-NEXT: retq
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;
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; XOP-LABEL: combine_vec_sdiv_nonuniform6:
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; XOP: # %bb.0:
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; XOP-NEXT: vpmulhw {{.*}}(%rip), %xmm0, %xmm1
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; XOP-NEXT: vpmacsww %xmm1, {{.*}}(%rip), %xmm0, %xmm0
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; XOP-NEXT: vpsrlw $15, %xmm0, %xmm1
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; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; XOP-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3,4],xmm1[5,6,7]
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; XOP-NEXT: vpshaw {{.*}}(%rip), %xmm0, %xmm0
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; XOP-NEXT: vpaddw %xmm1, %xmm0, %xmm0
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; XOP-NEXT: retq
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%1 = sdiv <8 x i16> %x, <i16 -32768, i16 -512, i16 -511, i16 -1, i16 1, i16 255, i16 512, i16 32767>
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ret <8 x i16> %1
|
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}
|
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|
|
|
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Loading…
Reference in New Issue